sound/pci/cmipci.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Driver for C-Media CMI8338 and 8738 PCI soundcards.
   4  * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
   5  */
   6
   7 /* Does not work. Warning may block system in capture mode */
   8 /* #define USE_VAR48KRATE */
   9
  10 #include <linux/io.h>
  11 #include <linux/delay.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/slab.h>
  16 #include <linux/gameport.h>
  17 #include <linux/module.h>
  18 #include <linux/mutex.h>
  19 #include <sound/core.h>
  20 #include <sound/info.h>
  21 #include <sound/control.h>
  22 #include <sound/pcm.h>
  23 #include <sound/rawmidi.h>
  24 #include <sound/mpu401.h>
  25 #include <sound/opl3.h>
  26 #include <sound/sb.h>
  27 #include <sound/asoundef.h>
  28 #include <sound/initval.h>
  29
  30 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
  31 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
  32 MODULE_LICENSE("GPL");
  33 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
  34                 "{C-Media,CMI8738B},"
  35                 "{C-Media,CMI8338A},"
  36                 "{C-Media,CMI8338B}}");
  37
  38 #if IS_REACHABLE(CONFIG_GAMEPORT)
  39 #define SUPPORT_JOYSTICK 1
  40 #endif
  41
  42 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  43 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  44 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable switches */
  45 static long mpu_port[SNDRV_CARDS];
  46 static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
  47 static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
  48 #ifdef SUPPORT_JOYSTICK
  49 static int joystick_port[SNDRV_CARDS];
  50 #endif
  51
  52 module_param_array(index, int, NULL, 0444);
  53 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
  54 module_param_array(id, charp, NULL, 0444);
  55 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
  56 module_param_array(enable, bool, NULL, 0444);
  57 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
  58 module_param_hw_array(mpu_port, long, ioport, NULL, 0444);
  59 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
  60 module_param_hw_array(fm_port, long, ioport, NULL, 0444);
  61 MODULE_PARM_DESC(fm_port, "FM port.");
  62 module_param_array(soft_ac3, bool, NULL, 0444);
  63 MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only).");
  64 #ifdef SUPPORT_JOYSTICK
  65 module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
  66 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
  67 #endif
  68
  69 /*
  70  * CM8x38 registers definition
  71  */
  72
  73 #define CM_REG_FUNCTRL0         0x00
  74 #define CM_RST_CH1              0x00080000
  75 #define CM_RST_CH0              0x00040000
  76 #define CM_CHEN1                0x00020000      /* ch1: enable */
  77 #define CM_CHEN0                0x00010000      /* ch0: enable */
  78 #define CM_PAUSE1               0x00000008      /* ch1: pause */
  79 #define CM_PAUSE0               0x00000004      /* ch0: pause */
  80 #define CM_CHADC1               0x00000002      /* ch1, 0:playback, 1:record */
  81 #define CM_CHADC0               0x00000001      /* ch0, 0:playback, 1:record */
  82
  83 #define CM_REG_FUNCTRL1         0x04
  84 #define CM_DSFC_MASK            0x0000E000      /* channel 1 (DAC?) sampling frequency */
  85 #define CM_DSFC_SHIFT           13
  86 #define CM_ASFC_MASK            0x00001C00      /* channel 0 (ADC?) sampling frequency */
  87 #define CM_ASFC_SHIFT           10
  88 #define CM_SPDF_1               0x00000200      /* SPDIF IN/OUT at channel B */
  89 #define CM_SPDF_0               0x00000100      /* SPDIF OUT only channel A */
  90 #define CM_SPDFLOOP             0x00000080      /* ext. SPDIIF/IN -> OUT loopback */
  91 #define CM_SPDO2DAC             0x00000040      /* SPDIF/OUT can be heard from internal DAC */
  92 #define CM_INTRM                0x00000020      /* master control block (MCB) interrupt enabled */
  93 #define CM_BREQ                 0x00000010      /* bus master enabled */
  94 #define CM_VOICE_EN             0x00000008      /* legacy voice (SB16,FM) */
  95 #define CM_UART_EN              0x00000004      /* legacy UART */
  96 #define CM_JYSTK_EN             0x00000002      /* legacy joystick */
  97 #define CM_ZVPORT               0x00000001      /* ZVPORT */
  98
  99 #define CM_REG_CHFORMAT         0x08
 100
 101 #define CM_CHB3D5C              0x80000000      /* 5,6 channels */
 102 #define CM_FMOFFSET2            0x40000000      /* initial FM PCM offset 2 when Fmute=1 */
 103 #define CM_CHB3D                0x20000000      /* 4 channels */
 104
 105 #define CM_CHIP_MASK1           0x1f000000
 106 #define CM_CHIP_037             0x01000000
 107 #define CM_SETLAT48             0x00800000      /* set latency timer 48h */
 108 #define CM_EDGEIRQ              0x00400000      /* emulated edge trigger legacy IRQ */
 109 #define CM_SPD24SEL39           0x00200000      /* 24-bit spdif: model 039 */
 110 #define CM_AC3EN1               0x00100000      /* enable AC3: model 037 */
 111 #define CM_SPDIF_SELECT1        0x00080000      /* for model <= 037 ? */
 112 #define CM_SPD24SEL             0x00020000      /* 24bit spdif: model 037 */
 113 /* #define CM_SPDIF_INVERSE     0x00010000 */ /* ??? */
 114
 115 #define CM_ADCBITLEN_MASK       0x0000C000
 116 #define CM_ADCBITLEN_16         0x00000000
 117 #define CM_ADCBITLEN_15         0x00004000
 118 #define CM_ADCBITLEN_14         0x00008000
 119 #define CM_ADCBITLEN_13         0x0000C000
 120
 121 #define CM_ADCDACLEN_MASK       0x00003000      /* model 037 */
 122 #define CM_ADCDACLEN_060        0x00000000
 123 #define CM_ADCDACLEN_066        0x00001000
 124 #define CM_ADCDACLEN_130        0x00002000
 125 #define CM_ADCDACLEN_280        0x00003000
 126
 127 #define CM_ADCDLEN_MASK         0x00003000      /* model 039 */
 128 #define CM_ADCDLEN_ORIGINAL     0x00000000
 129 #define CM_ADCDLEN_EXTRA        0x00001000
 130 #define CM_ADCDLEN_24K          0x00002000
 131 #define CM_ADCDLEN_WEIGHT       0x00003000
 132
 133 #define CM_CH1_SRATE_176K       0x00000800
 134 #define CM_CH1_SRATE_96K        0x00000800      /* model 055? */
 135 #define CM_CH1_SRATE_88K        0x00000400
 136 #define CM_CH0_SRATE_176K       0x00000200
 137 #define CM_CH0_SRATE_96K        0x00000200      /* model 055? */
 138 #define CM_CH0_SRATE_88K        0x00000100
 139 #define CM_CH0_SRATE_128K       0x00000300
 140 #define CM_CH0_SRATE_MASK       0x00000300
 141
 142 #define CM_SPDIF_INVERSE2       0x00000080      /* model 055? */
 143 #define CM_DBLSPDS              0x00000040      /* double SPDIF sample rate 88.2/96 */
 144 #define CM_POLVALID             0x00000020      /* inverse SPDIF/IN valid bit */
 145 #define CM_SPDLOCKED            0x00000010
 146
 147 #define CM_CH1FMT_MASK          0x0000000C      /* bit 3: 16 bits, bit 2: stereo */
 148 #define CM_CH1FMT_SHIFT         2
 149 #define CM_CH0FMT_MASK          0x00000003      /* bit 1: 16 bits, bit 0: stereo */
 150 #define CM_CH0FMT_SHIFT         0
 151
 152 #define CM_REG_INT_HLDCLR       0x0C
 153 #define CM_CHIP_MASK2           0xff000000
 154 #define CM_CHIP_8768            0x20000000
 155 #define CM_CHIP_055             0x08000000
 156 #define CM_CHIP_039             0x04000000
 157 #define CM_CHIP_039_6CH         0x01000000
 158 #define CM_UNKNOWN_INT_EN       0x00080000      /* ? */
 159 #define CM_TDMA_INT_EN          0x00040000
 160 #define CM_CH1_INT_EN           0x00020000
 161 #define CM_CH0_INT_EN           0x00010000
 162
 163 #define CM_REG_INT_STATUS       0x10
 164 #define CM_INTR                 0x80000000
 165 #define CM_VCO                  0x08000000      /* Voice Control? CMI8738 */
 166 #define CM_MCBINT               0x04000000      /* Master Control Block abort cond.? */
 167 #define CM_UARTINT              0x00010000
 168 #define CM_LTDMAINT             0x00008000
 169 #define CM_HTDMAINT             0x00004000
 170 #define CM_XDO46                0x00000080      /* Modell 033? Direct programming EEPROM (read data register) */
 171 #define CM_LHBTOG               0x00000040      /* High/Low status from DMA ctrl register */
 172 #define CM_LEG_HDMA             0x00000020      /* Legacy is in High DMA channel */
 173 #define CM_LEG_STEREO           0x00000010      /* Legacy is in Stereo mode */
 174 #define CM_CH1BUSY              0x00000008
 175 #define CM_CH0BUSY              0x00000004
 176 #define CM_CHINT1               0x00000002
 177 #define CM_CHINT0               0x00000001
 178
 179 #define CM_REG_LEGACY_CTRL      0x14
 180 #define CM_NXCHG                0x80000000      /* don't map base reg dword->sample */
 181 #define CM_VMPU_MASK            0x60000000      /* MPU401 i/o port address */
 182 #define CM_VMPU_330             0x00000000
 183 #define CM_VMPU_320             0x20000000
 184 #define CM_VMPU_310             0x40000000
 185 #define CM_VMPU_300             0x60000000
 186 #define CM_ENWR8237             0x10000000      /* enable bus master to write 8237 base reg */
 187 #define CM_VSBSEL_MASK          0x0C000000      /* SB16 base address */
 188 #define CM_VSBSEL_220           0x00000000
 189 #define CM_VSBSEL_240           0x04000000
 190 #define CM_VSBSEL_260           0x08000000
 191 #define CM_VSBSEL_280           0x0C000000
 192 #define CM_FMSEL_MASK           0x03000000      /* FM OPL3 base address */
 193 #define CM_FMSEL_388            0x00000000
 194 #define CM_FMSEL_3C8            0x01000000
 195 #define CM_FMSEL_3E0            0x02000000
 196 #define CM_FMSEL_3E8            0x03000000
 197 #define CM_ENSPDOUT             0x00800000      /* enable XSPDIF/OUT to I/O interface */
 198 #define CM_SPDCOPYRHT           0x00400000      /* spdif in/out copyright bit */
 199 #define CM_DAC2SPDO             0x00200000      /* enable wave+fm_midi -> SPDIF/OUT */
 200 #define CM_INVIDWEN             0x00100000      /* internal vendor ID write enable, model 039? */
 201 #define CM_SETRETRY             0x00100000      /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
 202 #define CM_C_EEACCESS           0x00080000      /* direct programming eeprom regs */
 203 #define CM_C_EECS               0x00040000
 204 #define CM_C_EEDI46             0x00020000
 205 #define CM_C_EECK46             0x00010000
 206 #define CM_CHB3D6C              0x00008000      /* 5.1 channels support */
 207 #define CM_CENTR2LIN            0x00004000      /* line-in as center out */
 208 #define CM_BASE2LIN             0x00002000      /* line-in as bass out */
 209 #define CM_EXBASEN              0x00001000      /* external bass input enable */
 210
 211 #define CM_REG_MISC_CTRL        0x18
 212 #define CM_PWD                  0x80000000      /* power down */
 213 #define CM_RESET                0x40000000
 214 #define CM_SFIL_MASK            0x30000000      /* filter control at front end DAC, model 037? */
 215 #define CM_VMGAIN               0x10000000      /* analog master amp +6dB, model 039? */
 216 #define CM_TXVX                 0x08000000      /* model 037? */
 217 #define CM_N4SPK3D              0x04000000      /* copy front to rear */
 218 #define CM_SPDO5V               0x02000000      /* 5V spdif output (1 = 0.5v (coax)) */
 219 #define CM_SPDIF48K             0x01000000      /* write */
 220 #define CM_SPATUS48K            0x01000000      /* read */
 221 #define CM_ENDBDAC              0x00800000      /* enable double dac */
 222 #define CM_XCHGDAC              0x00400000      /* 0: front=ch0, 1: front=ch1 */
 223 #define CM_SPD32SEL             0x00200000      /* 0: 16bit SPDIF, 1: 32bit */
 224 #define CM_SPDFLOOPI            0x00100000      /* int. SPDIF-OUT -> int. IN */
 225 #define CM_FM_EN                0x00080000      /* enable legacy FM */
 226 #define CM_AC3EN2               0x00040000      /* enable AC3: model 039 */
 227 #define CM_ENWRASID             0x00010000      /* choose writable internal SUBID (audio) */
 228 #define CM_VIDWPDSB             0x00010000      /* model 037? */
 229 #define CM_SPDF_AC97            0x00008000      /* 0: SPDIF/OUT 44.1K, 1: 48K */
 230 #define CM_MASK_EN              0x00004000      /* activate channel mask on legacy DMA */
 231 #define CM_ENWRMSID             0x00002000      /* choose writable internal SUBID (modem) */
 232 #define CM_VIDWPPRT             0x00002000      /* model 037? */
 233 #define CM_SFILENB              0x00001000      /* filter stepping at front end DAC, model 037? */
 234 #define CM_MMODE_MASK           0x00000E00      /* model DAA interface mode */
 235 #define CM_SPDIF_SELECT2        0x00000100      /* for model > 039 ? */
 236 #define CM_ENCENTER             0x00000080
 237 #define CM_FLINKON              0x00000040      /* force modem link detection on, model 037 */
 238 #define CM_MUTECH1              0x00000040      /* mute PCI ch1 to DAC */
 239 #define CM_FLINKOFF             0x00000020      /* force modem link detection off, model 037 */
 240 #define CM_MIDSMP               0x00000010      /* 1/2 interpolation at front end DAC */
 241 #define CM_UPDDMA_MASK          0x0000000C      /* TDMA position update notification */
 242 #define CM_UPDDMA_2048          0x00000000
 243 #define CM_UPDDMA_1024          0x00000004
 244 #define CM_UPDDMA_512           0x00000008
 245 #define CM_UPDDMA_256           0x0000000C
 246 #define CM_TWAIT_MASK           0x00000003      /* model 037 */
 247 #define CM_TWAIT1               0x00000002      /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
 248 #define CM_TWAIT0               0x00000001      /* i/o cycle, 0: 4, 1: 6 PCICLKs */
 249
 250 #define CM_REG_TDMA_POSITION    0x1C
 251 #define CM_TDMA_CNT_MASK        0xFFFF0000      /* current byte/word count */
 252 #define CM_TDMA_ADR_MASK        0x0000FFFF      /* current address */
 253
 254         /* byte */
 255 #define CM_REG_MIXER0           0x20
 256 #define CM_REG_SBVR             0x20            /* write: sb16 version */
 257 #define CM_REG_DEV              0x20            /* read: hardware device version */
 258
 259 #define CM_REG_MIXER21          0x21
 260 #define CM_UNKNOWN_21_MASK      0x78            /* ? */
 261 #define CM_X_ADPCM              0x04            /* SB16 ADPCM enable */
 262 #define CM_PROINV               0x02            /* SBPro left/right channel switching */
 263 #define CM_X_SB16               0x01            /* SB16 compatible */
 264
 265 #define CM_REG_SB16_DATA        0x22
 266 #define CM_REG_SB16_ADDR        0x23
 267
 268 #define CM_REFFREQ_XIN          (315*1000*1000)/22      /* 14.31818 Mhz reference clock frequency pin XIN */
 269 #define CM_ADCMULT_XIN          512                     /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
 270 #define CM_TOLERANCE_RATE       0.001                   /* Tolerance sample rate pitch (1000ppm) */
 271 #define CM_MAXIMUM_RATE         80000000                /* Note more than 80MHz */
 272
 273 #define CM_REG_MIXER1           0x24
 274 #define CM_FMMUTE               0x80    /* mute FM */
 275 #define CM_FMMUTE_SHIFT         7
 276 #define CM_WSMUTE               0x40    /* mute PCM */
 277 #define CM_WSMUTE_SHIFT         6
 278 #define CM_REAR2LIN             0x20    /* lin-in -> rear line out */
 279 #define CM_REAR2LIN_SHIFT       5
 280 #define CM_REAR2FRONT           0x10    /* exchange rear/front */
 281 #define CM_REAR2FRONT_SHIFT     4
 282 #define CM_WAVEINL              0x08    /* digital wave rec. left chan */
 283 #define CM_WAVEINL_SHIFT        3
 284 #define CM_WAVEINR              0x04    /* digical wave rec. right */
 285 #define CM_WAVEINR_SHIFT        2
 286 #define CM_X3DEN                0x02    /* 3D surround enable */
 287 #define CM_X3DEN_SHIFT          1
 288 #define CM_CDPLAY               0x01    /* enable SPDIF/IN PCM -> DAC */
 289 #define CM_CDPLAY_SHIFT         0
 290
 291 #define CM_REG_MIXER2           0x25
 292 #define CM_RAUXREN              0x80    /* AUX right capture */
 293 #define CM_RAUXREN_SHIFT        7
 294 #define CM_RAUXLEN              0x40    /* AUX left capture */
 295 #define CM_RAUXLEN_SHIFT        6
 296 #define CM_VAUXRM               0x20    /* AUX right mute */
 297 #define CM_VAUXRM_SHIFT         5
 298 #define CM_VAUXLM               0x10    /* AUX left mute */
 299 #define CM_VAUXLM_SHIFT         4
 300 #define CM_VADMIC_MASK          0x0e    /* mic gain level (0-3) << 1 */
 301 #define CM_VADMIC_SHIFT         1
 302 #define CM_MICGAINZ             0x01    /* mic boost */
 303 #define CM_MICGAINZ_SHIFT       0
 304
 305 #define CM_REG_AUX_VOL          0x26
 306 #define CM_VAUXL_MASK           0xf0
 307 #define CM_VAUXR_MASK           0x0f
 308
 309 #define CM_REG_MISC             0x27
 310 #define CM_UNKNOWN_27_MASK      0xd8    /* ? */
 311 #define CM_XGPO1                0x20
 312 // #define CM_XGPBIO            0x04
 313 #define CM_MIC_CENTER_LFE       0x04    /* mic as center/lfe out? (model 039 or later?) */
 314 #define CM_SPDIF_INVERSE        0x04    /* spdif input phase inverse (model 037) */
 315 #define CM_SPDVALID             0x02    /* spdif input valid check */
 316 #define CM_DMAUTO               0x01    /* SB16 DMA auto detect */
 317
 318 #define CM_REG_AC97             0x28    /* hmmm.. do we have ac97 link? */
 319 /*
 320  * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
 321  * or identical with AC97 codec?
 322  */
 323 #define CM_REG_EXTERN_CODEC     CM_REG_AC97
 324
 325 /*
 326  * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
 327  */
 328 #define CM_REG_MPU_PCI          0x40
 329
 330 /*
 331  * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
 332  */
 333 #define CM_REG_FM_PCI           0x50
 334
 335 /*
 336  * access from SB-mixer port
 337  */
 338 #define CM_REG_EXTENT_IND       0xf0
 339 #define CM_VPHONE_MASK          0xe0    /* Phone volume control (0-3) << 5 */
 340 #define CM_VPHONE_SHIFT         5
 341 #define CM_VPHOM                0x10    /* Phone mute control */
 342 #define CM_VSPKM                0x08    /* Speaker mute control, default high */
 343 #define CM_RLOOPREN             0x04    /* Rec. R-channel enable */
 344 #define CM_RLOOPLEN             0x02    /* Rec. L-channel enable */
 345 #define CM_VADMIC3              0x01    /* Mic record boost */
 346
 347 /*
 348  * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
 349  * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
 350  * unit (readonly?).
 351  */
 352 #define CM_REG_PLL              0xf8
 353
 354 /*
 355  * extended registers
 356  */
 357 #define CM_REG_CH0_FRAME1       0x80    /* write: base address */
 358 #define CM_REG_CH0_FRAME2       0x84    /* read: current address */
 359 #define CM_REG_CH1_FRAME1       0x88    /* 0-15: count of samples at bus master; buffer size */
 360 #define CM_REG_CH1_FRAME2       0x8C    /* 16-31: count of samples at codec; fragment size */
 361
 362 #define CM_REG_EXT_MISC         0x90
 363 #define CM_ADC48K44K            0x10000000      /* ADC parameters group, 0: 44k, 1: 48k */
 364 #define CM_CHB3D8C              0x00200000      /* 7.1 channels support */
 365 #define CM_SPD32FMT             0x00100000      /* SPDIF/IN 32k sample rate */
 366 #define CM_ADC2SPDIF            0x00080000      /* ADC output to SPDIF/OUT */
 367 #define CM_SHAREADC             0x00040000      /* DAC in ADC as Center/LFE */
 368 #define CM_REALTCMP             0x00020000      /* monitor the CMPL/CMPR of ADC */
 369 #define CM_INVLRCK              0x00010000      /* invert ZVPORT's LRCK */
 370 #define CM_UNKNOWN_90_MASK      0x0000FFFF      /* ? */
 371
 372 /*
 373  * size of i/o region
 374  */
 375 #define CM_EXTENT_CODEC   0x100
 376 #define CM_EXTENT_MIDI    0x2
 377 #define CM_EXTENT_SYNTH   0x4
 378
 379
 380 /*
 381  * channels for playback / capture
 382  */
 383 #define CM_CH_PLAY      0
 384 #define CM_CH_CAPT      1
 385
 386 /*
 387  * flags to check device open/close
 388  */
 389 #define CM_OPEN_NONE    0
 390 #define CM_OPEN_CH_MASK 0x01
 391 #define CM_OPEN_DAC     0x10
 392 #define CM_OPEN_ADC     0x20
 393 #define CM_OPEN_SPDIF   0x40
 394 #define CM_OPEN_MCHAN   0x80
 395 #define CM_OPEN_PLAYBACK        (CM_CH_PLAY | CM_OPEN_DAC)
 396 #define CM_OPEN_PLAYBACK2       (CM_CH_CAPT | CM_OPEN_DAC)
 397 #define CM_OPEN_PLAYBACK_MULTI  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
 398 #define CM_OPEN_CAPTURE         (CM_CH_CAPT | CM_OPEN_ADC)
 399 #define CM_OPEN_SPDIF_PLAYBACK  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
 400 #define CM_OPEN_SPDIF_CAPTURE   (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
 401
 402
 403 #if CM_CH_PLAY == 1
 404 #define CM_PLAYBACK_SRATE_176K  CM_CH1_SRATE_176K
 405 #define CM_PLAYBACK_SPDF        CM_SPDF_1
 406 #define CM_CAPTURE_SPDF         CM_SPDF_0
 407 #else
 408 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
 409 #define CM_PLAYBACK_SPDF        CM_SPDF_0
 410 #define CM_CAPTURE_SPDF         CM_SPDF_1
 411 #endif
 412
 413
 414 /*
 415  * driver data
 416  */
 417
 418 struct cmipci_pcm {
 419         struct snd_pcm_substream *substream;
 420         u8 running;             /* dac/adc running? */
 421         u8 fmt;                 /* format bits */
 422         u8 is_dac;
 423         u8 needs_silencing;
 424         unsigned int dma_size;  /* in frames */
 425         unsigned int shift;
 426         unsigned int ch;        /* channel (0/1) */
 427         unsigned int offset;    /* physical address of the buffer */
 428 };
 429
 430 /* mixer elements toggled/resumed during ac3 playback */
 431 struct cmipci_mixer_auto_switches {
 432         const char *name;       /* switch to toggle */
 433         int toggle_on;          /* value to change when ac3 mode */
 434 };
 435 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
 436         {"PCM Playback Switch", 0},
 437         {"IEC958 Output Switch", 1},
 438         {"IEC958 Mix Analog", 0},
 439         // {"IEC958 Out To DAC", 1}, // no longer used
 440         {"IEC958 Loop", 0},
 441 };
 442 #define CM_SAVED_MIXERS         ARRAY_SIZE(cm_saved_mixer)
 443
 444 struct cmipci {
 445         struct snd_card *card;
 446
 447         struct pci_dev *pci;
 448         unsigned int device;    /* device ID */
 449         int irq;
 450
 451         unsigned long iobase;
 452         unsigned int ctrl;      /* FUNCTRL0 current value */
 453
 454         struct snd_pcm *pcm;            /* DAC/ADC PCM */
 455         struct snd_pcm *pcm2;   /* 2nd DAC */
 456         struct snd_pcm *pcm_spdif;      /* SPDIF */
 457
 458         int chip_version;
 459         int max_channels;
 460         unsigned int can_ac3_sw: 1;
 461         unsigned int can_ac3_hw: 1;
 462         unsigned int can_multi_ch: 1;
 463         unsigned int can_96k: 1;        /* samplerate above 48k */
 464         unsigned int do_soft_ac3: 1;
 465
 466         unsigned int spdif_playback_avail: 1;   /* spdif ready? */
 467         unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
 468         int spdif_counter;      /* for software AC3 */
 469
 470         unsigned int dig_status;
 471         unsigned int dig_pcm_status;
 472
 473         struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
 474
 475         int opened[2];  /* open mode */
 476         struct mutex open_mutex;
 477
 478         unsigned int mixer_insensitive: 1;
 479         struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
 480         int mixer_res_status[CM_SAVED_MIXERS];
 481
 482         struct cmipci_pcm channel[2];   /* ch0 - DAC, ch1 - ADC or 2nd DAC */
 483
 484         /* external MIDI */
 485         struct snd_rawmidi *rmidi;
 486
 487 #ifdef SUPPORT_JOYSTICK
 488         struct gameport *gameport;
 489 #endif
 490
 491         spinlock_t reg_lock;
 492
 493 #ifdef CONFIG_PM_SLEEP
 494         unsigned int saved_regs[0x20];
 495         unsigned char saved_mixers[0x20];
 496 #endif
 497 };
 498
 499
 500 /* read/write operations for dword register */
 501 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
 502 {
 503         outl(data, cm->iobase + cmd);
 504 }
 505
 506 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
 507 {
 508         return inl(cm->iobase + cmd);
 509 }
 510
 511 /* read/write operations for word register */
 512 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
 513 {
 514         outw(data, cm->iobase + cmd);
 515 }
 516
 517 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
 518 {
 519         return inw(cm->iobase + cmd);
 520 }
 521
 522 /* read/write operations for byte register */
 523 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
 524 {
 525         outb(data, cm->iobase + cmd);
 526 }
 527
 528 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
 529 {
 530         return inb(cm->iobase + cmd);
 531 }
 532
 533 /* bit operations for dword register */
 534 static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
 535 {
 536         unsigned int val, oval;
 537         val = oval = inl(cm->iobase + cmd);
 538         val |= flag;
 539         if (val == oval)
 540                 return 0;
 541         outl(val, cm->iobase + cmd);
 542         return 1;
 543 }
 544
 545 static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
 546 {
 547         unsigned int val, oval;
 548         val = oval = inl(cm->iobase + cmd);
 549         val &= ~flag;
 550         if (val == oval)
 551                 return 0;
 552         outl(val, cm->iobase + cmd);
 553         return 1;
 554 }
 555
 556 /* bit operations for byte register */
 557 static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
 558 {
 559         unsigned char val, oval;
 560         val = oval = inb(cm->iobase + cmd);
 561         val |= flag;
 562         if (val == oval)
 563                 return 0;
 564         outb(val, cm->iobase + cmd);
 565         return 1;
 566 }
 567
 568 static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
 569 {
 570         unsigned char val, oval;
 571         val = oval = inb(cm->iobase + cmd);
 572         val &= ~flag;
 573         if (val == oval)
 574                 return 0;
 575         outb(val, cm->iobase + cmd);
 576         return 1;
 577 }
 578
 579
 580 /*
 581  * PCM interface
 582  */
 583
 584 /*
 585  * calculate frequency
 586  */
 587
 588 static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
 589
 590 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
 591 {
 592         unsigned int i;
 593
 594         for (i = 0; i < ARRAY_SIZE(rates); i++) {
 595                 if (rates[i] == rate)
 596                         return i;
 597         }
 598         snd_BUG();
 599         return 0;
 600 }
 601
 602 #ifdef USE_VAR48KRATE
 603 /*
 604  * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
 605  * does it this way .. maybe not.  Never get any information from C-Media about
 606  * that <werner@suse.de>.
 607  */
 608 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
 609 {
 610         unsigned int delta, tolerance;
 611         int xm, xn, xr;
 612
 613         for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
 614                 rate <<= 1;
 615         *n = -1;
 616         if (*r > 0xff)
 617                 goto out;
 618         tolerance = rate*CM_TOLERANCE_RATE;
 619
 620         for (xn = (1+2); xn < (0x1f+2); xn++) {
 621                 for (xm = (1+2); xm < (0xff+2); xm++) {
 622                         xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
 623
 624                         if (xr < rate)
 625                                 delta = rate - xr;
 626                         else
 627                                 delta = xr - rate;
 628
 629                         /*
 630                          * If we found one, remember this,
 631                          * and try to find a closer one
 632                          */
 633                         if (delta < tolerance) {
 634                                 tolerance = delta;
 635                                 *m = xm - 2;
 636                                 *n = xn - 2;
 637                         }
 638                 }
 639         }
 640 out:
 641         return (*n > -1);
 642 }
 643
 644 /*
 645  * Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff
 646  * are mapped onto the 8 ADC/DAC sampling frequency which can be chosen
 647  * at the register CM_REG_FUNCTRL1 (0x04).
 648  * Problem: other ways are also possible (any information about that?)
 649  */
 650 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
 651 {
 652         unsigned int reg = CM_REG_PLL + slot;
 653         /*
 654          * Guess that this programs at reg. 0x04 the pos 15:13/12:10
 655          * for DSFC/ASFC (000 up to 111).
 656          */
 657
 658         /* FIXME: Init (Do we've to set an other register first before programming?) */
 659
 660         /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
 661         snd_cmipci_write_b(cm, reg, rate>>8);
 662         snd_cmipci_write_b(cm, reg, rate&0xff);
 663
 664         /* FIXME: Setup (Do we've to set an other register first to enable this?) */
 665 }
 666 #endif /* USE_VAR48KRATE */
 667
 668 static int snd_cmipci_hw_params(struct snd_pcm_substream *substream,
 669                                 struct snd_pcm_hw_params *hw_params)
 670 {
 671         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 672 }
 673
 674 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
 675                                           struct snd_pcm_hw_params *hw_params)
 676 {
 677         struct cmipci *cm = snd_pcm_substream_chip(substream);
 678         if (params_channels(hw_params) > 2) {
 679                 mutex_lock(&cm->open_mutex);
 680                 if (cm->opened[CM_CH_PLAY]) {
 681                         mutex_unlock(&cm->open_mutex);
 682                         return -EBUSY;
 683                 }
 684                 /* reserve the channel A */
 685                 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
 686                 mutex_unlock(&cm->open_mutex);
 687         }
 688         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 689 }
 690
 691 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
 692 {
 693         int reset = CM_RST_CH0 << (cm->channel[ch].ch);
 694         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
 695         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
 696         udelay(10);
 697 }
 698
 699 static int snd_cmipci_hw_free(struct snd_pcm_substream *substream)
 700 {
 701         return snd_pcm_lib_free_pages(substream);
 702 }
 703
 704
 705 /*
 706  */
 707
 708 static const unsigned int hw_channels[] = {1, 2, 4, 6, 8};
 709 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
 710         .count = 3,
 711         .list = hw_channels,
 712         .mask = 0,
 713 };
 714 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
 715         .count = 4,
 716         .list = hw_channels,
 717         .mask = 0,
 718 };
 719 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
 720         .count = 5,
 721         .list = hw_channels,
 722         .mask = 0,
 723 };
 724
 725 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
 726 {
 727         if (channels > 2) {
 728                 if (!cm->can_multi_ch || !rec->ch)
 729                         return -EINVAL;
 730                 if (rec->fmt != 0x03) /* stereo 16bit only */
 731                         return -EINVAL;
 732         }
 733
 734         if (cm->can_multi_ch) {
 735                 spin_lock_irq(&cm->reg_lock);
 736                 if (channels > 2) {
 737                         snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
 738                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
 739                 } else {
 740                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
 741                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
 742                 }
 743                 if (channels == 8)
 744                         snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
 745                 else
 746                         snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
 747                 if (channels == 6) {
 748                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 749                         snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 750                 } else {
 751                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 752                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 753                 }
 754                 if (channels == 4)
 755                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 756                 else
 757                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 758                 spin_unlock_irq(&cm->reg_lock);
 759         }
 760         return 0;
 761 }
 762
 763
 764 /*
 765  * prepare playback/capture channel
 766  * channel to be used must have been set in rec->ch.
 767  */
 768 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
 769                                  struct snd_pcm_substream *substream)
 770 {
 771         unsigned int reg, freq, freq_ext, val;
 772         unsigned int period_size;
 773         struct snd_pcm_runtime *runtime = substream->runtime;
 774
 775         rec->fmt = 0;
 776         rec->shift = 0;
 777         if (snd_pcm_format_width(runtime->format) >= 16) {
 778                 rec->fmt |= 0x02;
 779                 if (snd_pcm_format_width(runtime->format) > 16)
 780                         rec->shift++; /* 24/32bit */
 781         }
 782         if (runtime->channels > 1)
 783                 rec->fmt |= 0x01;
 784         if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
 785                 dev_dbg(cm->card->dev, "cannot set dac channels\n");
 786                 return -EINVAL;
 787         }
 788
 789         rec->offset = runtime->dma_addr;
 790         /* buffer and period sizes in frame */
 791         rec->dma_size = runtime->buffer_size << rec->shift;
 792         period_size = runtime->period_size << rec->shift;
 793         if (runtime->channels > 2) {
 794                 /* multi-channels */
 795                 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
 796                 period_size = (period_size * runtime->channels) / 2;
 797         }
 798
 799         spin_lock_irq(&cm->reg_lock);
 800
 801         /* set buffer address */
 802         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
 803         snd_cmipci_write(cm, reg, rec->offset);
 804         /* program sample counts */
 805         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
 806         snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
 807         snd_cmipci_write_w(cm, reg + 2, period_size - 1);
 808
 809         /* set adc/dac flag */
 810         val = rec->ch ? CM_CHADC1 : CM_CHADC0;
 811         if (rec->is_dac)
 812                 cm->ctrl &= ~val;
 813         else
 814                 cm->ctrl |= val;
 815         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 816         /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
 817
 818         /* set sample rate */
 819         freq = 0;
 820         freq_ext = 0;
 821         if (runtime->rate > 48000)
 822                 switch (runtime->rate) {
 823                 case 88200:  freq_ext = CM_CH0_SRATE_88K; break;
 824                 case 96000:  freq_ext = CM_CH0_SRATE_96K; break;
 825                 case 128000: freq_ext = CM_CH0_SRATE_128K; break;
 826                 default:     snd_BUG(); break;
 827                 }
 828         else
 829                 freq = snd_cmipci_rate_freq(runtime->rate);
 830         val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
 831         if (rec->ch) {
 832                 val &= ~CM_DSFC_MASK;
 833                 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
 834         } else {
 835                 val &= ~CM_ASFC_MASK;
 836                 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
 837         }
 838         snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
 839         dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
 840
 841         /* set format */
 842         val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
 843         if (rec->ch) {
 844                 val &= ~CM_CH1FMT_MASK;
 845                 val |= rec->fmt << CM_CH1FMT_SHIFT;
 846         } else {
 847                 val &= ~CM_CH0FMT_MASK;
 848                 val |= rec->fmt << CM_CH0FMT_SHIFT;
 849         }
 850         if (cm->can_96k) {
 851                 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
 852                 val |= freq_ext << (rec->ch * 2);
 853         }
 854         snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
 855         dev_dbg(cm->card->dev, "chformat = %08x\n", val);
 856
 857         if (!rec->is_dac && cm->chip_version) {
 858                 if (runtime->rate > 44100)
 859                         snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
 860                 else
 861                         snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
 862         }
 863
 864         rec->running = 0;
 865         spin_unlock_irq(&cm->reg_lock);
 866
 867         return 0;
 868 }
 869
 870 /*
 871  * PCM trigger/stop
 872  */
 873 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
 874                                   int cmd)
 875 {
 876         unsigned int inthld, chen, reset, pause;
 877         int result = 0;
 878
 879         inthld = CM_CH0_INT_EN << rec->ch;
 880         chen = CM_CHEN0 << rec->ch;
 881         reset = CM_RST_CH0 << rec->ch;
 882         pause = CM_PAUSE0 << rec->ch;
 883
 884         spin_lock(&cm->reg_lock);
 885         switch (cmd) {
 886         case SNDRV_PCM_TRIGGER_START:
 887                 rec->running = 1;
 888                 /* set interrupt */
 889                 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
 890                 cm->ctrl |= chen;
 891                 /* enable channel */
 892                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 893                 dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
 894                 break;
 895         case SNDRV_PCM_TRIGGER_STOP:
 896                 rec->running = 0;
 897                 /* disable interrupt */
 898                 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
 899                 /* reset */
 900                 cm->ctrl &= ~chen;
 901                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
 902                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
 903                 rec->needs_silencing = rec->is_dac;
 904                 break;
 905         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 906         case SNDRV_PCM_TRIGGER_SUSPEND:
 907                 cm->ctrl |= pause;
 908                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 909                 break;
 910         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 911         case SNDRV_PCM_TRIGGER_RESUME:
 912                 cm->ctrl &= ~pause;
 913                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 914                 break;
 915         default:
 916                 result = -EINVAL;
 917                 break;
 918         }
 919         spin_unlock(&cm->reg_lock);
 920         return result;
 921 }
 922
 923 /*
 924  * return the current pointer
 925  */
 926 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
 927                                                 struct snd_pcm_substream *substream)
 928 {
 929         size_t ptr;
 930         unsigned int reg, rem, tries;
 931
 932         if (!rec->running)
 933                 return 0;
 934 #if 1 // this seems better..
 935         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
 936         for (tries = 0; tries < 3; tries++) {
 937                 rem = snd_cmipci_read_w(cm, reg);
 938                 if (rem < rec->dma_size)
 939                         goto ok;
 940         }
 941         dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
 942         return SNDRV_PCM_POS_XRUN;
 943 ok:
 944         ptr = (rec->dma_size - (rem + 1)) >> rec->shift;
 945 #else
 946         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
 947         ptr = snd_cmipci_read(cm, reg) - rec->offset;
 948         ptr = bytes_to_frames(substream->runtime, ptr);
 949 #endif
 950         if (substream->runtime->channels > 2)
 951                 ptr = (ptr * 2) / substream->runtime->channels;
 952         return ptr;
 953 }
 954
 955 /*
 956  * playback
 957  */
 958
 959 static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
 960                                        int cmd)
 961 {
 962         struct cmipci *cm = snd_pcm_substream_chip(substream);
 963         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
 964 }
 965
 966 static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
 967 {
 968         struct cmipci *cm = snd_pcm_substream_chip(substream);
 969         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
 970 }
 971
 972
 973
 974 /*
 975  * capture
 976  */
 977
 978 static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
 979                                      int cmd)
 980 {
 981         struct cmipci *cm = snd_pcm_substream_chip(substream);
 982         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
 983 }
 984
 985 static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
 986 {
 987         struct cmipci *cm = snd_pcm_substream_chip(substream);
 988         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
 989 }
 990
 991
 992 /*
 993  * hw preparation for spdif
 994  */
 995
 996 static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
 997                                          struct snd_ctl_elem_info *uinfo)
 998 {
 999         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1000         uinfo->count = 1;
1001         return 0;
1002 }
1003
1004 static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
1005                                         struct snd_ctl_elem_value *ucontrol)
1006 {
1007         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1008         int i;
1009
1010         spin_lock_irq(&chip->reg_lock);
1011         for (i = 0; i < 4; i++)
1012                 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
1013         spin_unlock_irq(&chip->reg_lock);
1014         return 0;
1015 }
1016
1017 static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1018                                          struct snd_ctl_elem_value *ucontrol)
1019 {
1020         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1021         int i, change;
1022         unsigned int val;
1023
1024         val = 0;
1025         spin_lock_irq(&chip->reg_lock);
1026         for (i = 0; i < 4; i++)
1027                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1028         change = val != chip->dig_status;
1029         chip->dig_status = val;
1030         spin_unlock_irq(&chip->reg_lock);
1031         return change;
1032 }
1033
1034 static const struct snd_kcontrol_new snd_cmipci_spdif_default =
1035 {
1036         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1037         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1038         .info =         snd_cmipci_spdif_default_info,
1039         .get =          snd_cmipci_spdif_default_get,
1040         .put =          snd_cmipci_spdif_default_put
1041 };
1042
1043 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1044                                       struct snd_ctl_elem_info *uinfo)
1045 {
1046         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1047         uinfo->count = 1;
1048         return 0;
1049 }
1050
1051 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1052                                      struct snd_ctl_elem_value *ucontrol)
1053 {
1054         ucontrol->value.iec958.status[0] = 0xff;
1055         ucontrol->value.iec958.status[1] = 0xff;
1056         ucontrol->value.iec958.status[2] = 0xff;
1057         ucontrol->value.iec958.status[3] = 0xff;
1058         return 0;
1059 }
1060
1061 static const struct snd_kcontrol_new snd_cmipci_spdif_mask =
1062 {
1063         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1064         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1065         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1066         .info =         snd_cmipci_spdif_mask_info,
1067         .get =          snd_cmipci_spdif_mask_get,
1068 };
1069
1070 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1071                                         struct snd_ctl_elem_info *uinfo)
1072 {
1073         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1074         uinfo->count = 1;
1075         return 0;
1076 }
1077
1078 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1079                                        struct snd_ctl_elem_value *ucontrol)
1080 {
1081         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1082         int i;
1083
1084         spin_lock_irq(&chip->reg_lock);
1085         for (i = 0; i < 4; i++)
1086                 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1087         spin_unlock_irq(&chip->reg_lock);
1088         return 0;
1089 }
1090
1091 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1092                                        struct snd_ctl_elem_value *ucontrol)
1093 {
1094         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1095         int i, change;
1096         unsigned int val;
1097
1098         val = 0;
1099         spin_lock_irq(&chip->reg_lock);
1100         for (i = 0; i < 4; i++)
1101                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1102         change = val != chip->dig_pcm_status;
1103         chip->dig_pcm_status = val;
1104         spin_unlock_irq(&chip->reg_lock);
1105         return change;
1106 }
1107
1108 static const struct snd_kcontrol_new snd_cmipci_spdif_stream =
1109 {
1110         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1111         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1112         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1113         .info =         snd_cmipci_spdif_stream_info,
1114         .get =          snd_cmipci_spdif_stream_get,
1115         .put =          snd_cmipci_spdif_stream_put
1116 };
1117
1118 /*
1119  */
1120
1121 /* save mixer setting and mute for AC3 playback */
1122 static int save_mixer_state(struct cmipci *cm)
1123 {
1124         if (! cm->mixer_insensitive) {
1125                 struct snd_ctl_elem_value *val;
1126                 unsigned int i;
1127
1128                 val = kmalloc(sizeof(*val), GFP_KERNEL);
1129                 if (!val)
1130                         return -ENOMEM;
1131                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1132                         struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1133                         if (ctl) {
1134                                 int event;
1135                                 memset(val, 0, sizeof(*val));
1136                                 ctl->get(ctl, val);
1137                                 cm->mixer_res_status[i] = val->value.integer.value[0];
1138                                 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1139                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1140                                 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1141                                         ctl->put(ctl, val); /* toggle */
1142                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1143                                 }
1144                                 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1145                                 snd_ctl_notify(cm->card, event, &ctl->id);
1146                         }
1147                 }
1148                 kfree(val);
1149                 cm->mixer_insensitive = 1;
1150         }
1151         return 0;
1152 }
1153
1154
1155 /* restore the previously saved mixer status */
1156 static void restore_mixer_state(struct cmipci *cm)
1157 {
1158         if (cm->mixer_insensitive) {
1159                 struct snd_ctl_elem_value *val;
1160                 unsigned int i;
1161
1162                 val = kmalloc(sizeof(*val), GFP_KERNEL);
1163                 if (!val)
1164                         return;
1165                 cm->mixer_insensitive = 0; /* at first clear this;
1166                                               otherwise the changes will be ignored */
1167                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1168                         struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1169                         if (ctl) {
1170                                 int event;
1171
1172                                 memset(val, 0, sizeof(*val));
1173                                 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1174                                 ctl->get(ctl, val);
1175                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1176                                 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1177                                         val->value.integer.value[0] = cm->mixer_res_status[i];
1178                                         ctl->put(ctl, val);
1179                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1180                                 }
1181                                 snd_ctl_notify(cm->card, event, &ctl->id);
1182                         }
1183                 }
1184                 kfree(val);
1185         }
1186 }
1187
1188 /* spinlock held! */
1189 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1190 {
1191         if (do_ac3) {
1192                 /* AC3EN for 037 */
1193                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1194                 /* AC3EN for 039 */
1195                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1196
1197                 if (cm->can_ac3_hw) {
1198                         /* SPD24SEL for 037, 0x02 */
1199                         /* SPD24SEL for 039, 0x20, but cannot be set */
1200                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1201                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1202                 } else { /* can_ac3_sw */
1203                         /* SPD32SEL for 037 & 039, 0x20 */
1204                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1205                         /* set 176K sample rate to fix 033 HW bug */
1206                         if (cm->chip_version == 33) {
1207                                 if (rate >= 48000) {
1208                                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1209                                 } else {
1210                                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1211                                 }
1212                         }
1213                 }
1214
1215         } else {
1216                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1217                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1218
1219                 if (cm->can_ac3_hw) {
1220                         /* chip model >= 37 */
1221                         if (snd_pcm_format_width(subs->runtime->format) > 16) {
1222                                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1223                                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1224                         } else {
1225                                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1226                                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1227                         }
1228                 } else {
1229                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1230                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1231                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1232                 }
1233         }
1234 }
1235
1236 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1237 {
1238         int rate, err;
1239
1240         rate = subs->runtime->rate;
1241
1242         if (up && do_ac3)
1243                 if ((err = save_mixer_state(cm)) < 0)
1244                         return err;
1245
1246         spin_lock_irq(&cm->reg_lock);
1247         cm->spdif_playback_avail = up;
1248         if (up) {
1249                 /* they are controlled via "IEC958 Output Switch" */
1250                 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1251                 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1252                 if (cm->spdif_playback_enabled)
1253                         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1254                 setup_ac3(cm, subs, do_ac3, rate);
1255
1256                 if (rate == 48000 || rate == 96000)
1257                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1258                 else
1259                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1260                 if (rate > 48000)
1261                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1262                 else
1263                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1264         } else {
1265                 /* they are controlled via "IEC958 Output Switch" */
1266                 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1267                 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1268                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1269                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1270                 setup_ac3(cm, subs, 0, 0);
1271         }
1272         spin_unlock_irq(&cm->reg_lock);
1273         return 0;
1274 }
1275
1276
1277 /*
1278  * preparation
1279  */
1280
1281 /* playback - enable spdif only on the certain condition */
1282 static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1283 {
1284         struct cmipci *cm = snd_pcm_substream_chip(substream);
1285         int rate = substream->runtime->rate;
1286         int err, do_spdif, do_ac3 = 0;
1287
1288         do_spdif = (rate >= 44100 && rate <= 96000 &&
1289                     substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1290                     substream->runtime->channels == 2);
1291         if (do_spdif && cm->can_ac3_hw)
1292                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1293         if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1294                 return err;
1295         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1296 }
1297
1298 /* playback  (via device #2) - enable spdif always */
1299 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1300 {
1301         struct cmipci *cm = snd_pcm_substream_chip(substream);
1302         int err, do_ac3;
1303
1304         if (cm->can_ac3_hw)
1305                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1306         else
1307                 do_ac3 = 1; /* doesn't matter */
1308         if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1309                 return err;
1310         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1311 }
1312
1313 /*
1314  * Apparently, the samples last played on channel A stay in some buffer, even
1315  * after the channel is reset, and get added to the data for the rear DACs when
1316  * playing a multichannel stream on channel B.  This is likely to generate
1317  * wraparounds and thus distortions.
1318  * To avoid this, we play at least one zero sample after the actual stream has
1319  * stopped.
1320  */
1321 static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1322 {
1323         struct snd_pcm_runtime *runtime = rec->substream->runtime;
1324         unsigned int reg, val;
1325
1326         if (rec->needs_silencing && runtime && runtime->dma_area) {
1327                 /* set up a small silence buffer */
1328                 memset(runtime->dma_area, 0, PAGE_SIZE);
1329                 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1330                 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1331                 snd_cmipci_write(cm, reg, val);
1332
1333                 /* configure for 16 bits, 2 channels, 8 kHz */
1334                 if (runtime->channels > 2)
1335                         set_dac_channels(cm, rec, 2);
1336                 spin_lock_irq(&cm->reg_lock);
1337                 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1338                 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1339                 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1340                 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1341                 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1342                 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1343                 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1344                 if (cm->can_96k)
1345                         val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1346                 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1347
1348                 /* start stream (we don't need interrupts) */
1349                 cm->ctrl |= CM_CHEN0 << rec->ch;
1350                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1351                 spin_unlock_irq(&cm->reg_lock);
1352
1353                 msleep(1);
1354
1355                 /* stop and reset stream */
1356                 spin_lock_irq(&cm->reg_lock);
1357                 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1358                 val = CM_RST_CH0 << rec->ch;
1359                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1360                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1361                 spin_unlock_irq(&cm->reg_lock);
1362
1363                 rec->needs_silencing = 0;
1364         }
1365 }
1366
1367 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1368 {
1369         struct cmipci *cm = snd_pcm_substream_chip(substream);
1370         setup_spdif_playback(cm, substream, 0, 0);
1371         restore_mixer_state(cm);
1372         snd_cmipci_silence_hack(cm, &cm->channel[0]);
1373         return snd_cmipci_hw_free(substream);
1374 }
1375
1376 static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1377 {
1378         struct cmipci *cm = snd_pcm_substream_chip(substream);
1379         snd_cmipci_silence_hack(cm, &cm->channel[1]);
1380         return snd_cmipci_hw_free(substream);
1381 }
1382
1383 /* capture */
1384 static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1385 {
1386         struct cmipci *cm = snd_pcm_substream_chip(substream);
1387         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1388 }
1389
1390 /* capture with spdif (via device #2) */
1391 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1392 {
1393         struct cmipci *cm = snd_pcm_substream_chip(substream);
1394
1395         spin_lock_irq(&cm->reg_lock);
1396         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1397         if (cm->can_96k) {
1398                 if (substream->runtime->rate > 48000)
1399                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1400                 else
1401                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1402         }
1403         if (snd_pcm_format_width(substream->runtime->format) > 16)
1404                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1405         else
1406                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1407
1408         spin_unlock_irq(&cm->reg_lock);
1409
1410         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1411 }
1412
1413 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1414 {
1415         struct cmipci *cm = snd_pcm_substream_chip(subs);
1416
1417         spin_lock_irq(&cm->reg_lock);
1418         snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1419         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1420         spin_unlock_irq(&cm->reg_lock);
1421
1422         return snd_cmipci_hw_free(subs);
1423 }
1424
1425
1426 /*
1427  * interrupt handler
1428  */
1429 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1430 {
1431         struct cmipci *cm = dev_id;
1432         unsigned int status, mask = 0;
1433
1434         /* fastpath out, to ease interrupt sharing */
1435         status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1436         if (!(status & CM_INTR))
1437                 return IRQ_NONE;
1438
1439         /* acknowledge interrupt */
1440         spin_lock(&cm->reg_lock);
1441         if (status & CM_CHINT0)
1442                 mask |= CM_CH0_INT_EN;
1443         if (status & CM_CHINT1)
1444                 mask |= CM_CH1_INT_EN;
1445         snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1446         snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1447         spin_unlock(&cm->reg_lock);
1448
1449         if (cm->rmidi && (status & CM_UARTINT))
1450                 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1451
1452         if (cm->pcm) {
1453                 if ((status & CM_CHINT0) && cm->channel[0].running)
1454                         snd_pcm_period_elapsed(cm->channel[0].substream);
1455                 if ((status & CM_CHINT1) && cm->channel[1].running)
1456                         snd_pcm_period_elapsed(cm->channel[1].substream);
1457         }
1458         return IRQ_HANDLED;
1459 }
1460
1461 /*
1462  * h/w infos
1463  */
1464
1465 /* playback on channel A */
1466 static const struct snd_pcm_hardware snd_cmipci_playback =
1467 {
1468         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1469                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1470                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1471         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1472         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1473         .rate_min =             5512,
1474         .rate_max =             48000,
1475         .channels_min =         1,
1476         .channels_max =         2,
1477         .buffer_bytes_max =     (128*1024),
1478         .period_bytes_min =     64,
1479         .period_bytes_max =     (128*1024),
1480         .periods_min =          2,
1481         .periods_max =          1024,
1482         .fifo_size =            0,
1483 };
1484
1485 /* capture on channel B */
1486 static const struct snd_pcm_hardware snd_cmipci_capture =
1487 {
1488         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1489                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1490                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1491         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1492         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1493         .rate_min =             5512,
1494         .rate_max =             48000,
1495         .channels_min =         1,
1496         .channels_max =         2,
1497         .buffer_bytes_max =     (128*1024),
1498         .period_bytes_min =     64,
1499         .period_bytes_max =     (128*1024),
1500         .periods_min =          2,
1501         .periods_max =          1024,
1502         .fifo_size =            0,
1503 };
1504
1505 /* playback on channel B - stereo 16bit only? */
1506 static const struct snd_pcm_hardware snd_cmipci_playback2 =
1507 {
1508         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1509                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1510                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1511         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1512         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1513         .rate_min =             5512,
1514         .rate_max =             48000,
1515         .channels_min =         2,
1516         .channels_max =         2,
1517         .buffer_bytes_max =     (128*1024),
1518         .period_bytes_min =     64,
1519         .period_bytes_max =     (128*1024),
1520         .periods_min =          2,
1521         .periods_max =          1024,
1522         .fifo_size =            0,
1523 };
1524
1525 /* spdif playback on channel A */
1526 static const struct snd_pcm_hardware snd_cmipci_playback_spdif =
1527 {
1528         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1529                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1530                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1531         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1532         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1533         .rate_min =             44100,
1534         .rate_max =             48000,
1535         .channels_min =         2,
1536         .channels_max =         2,
1537         .buffer_bytes_max =     (128*1024),
1538         .period_bytes_min =     64,
1539         .period_bytes_max =     (128*1024),
1540         .periods_min =          2,
1541         .periods_max =          1024,
1542         .fifo_size =            0,
1543 };
1544
1545 /* spdif playback on channel A (32bit, IEC958 subframes) */
1546 static const struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1547 {
1548         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1549                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1550                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1551         .formats =              SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1552         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1553         .rate_min =             44100,
1554         .rate_max =             48000,
1555         .channels_min =         2,
1556         .channels_max =         2,
1557         .buffer_bytes_max =     (128*1024),
1558         .period_bytes_min =     64,
1559         .period_bytes_max =     (128*1024),
1560         .periods_min =          2,
1561         .periods_max =          1024,
1562         .fifo_size =            0,
1563 };
1564
1565 /* spdif capture on channel B */
1566 static const struct snd_pcm_hardware snd_cmipci_capture_spdif =
1567 {
1568         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1569                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1570                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1571         .formats =              SNDRV_PCM_FMTBIT_S16_LE |
1572                                 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1573         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1574         .rate_min =             44100,
1575         .rate_max =             48000,
1576         .channels_min =         2,
1577         .channels_max =         2,
1578         .buffer_bytes_max =     (128*1024),
1579         .period_bytes_min =     64,
1580         .period_bytes_max =     (128*1024),
1581         .periods_min =          2,
1582         .periods_max =          1024,
1583         .fifo_size =            0,
1584 };
1585
1586 static const unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
1587                         32000, 44100, 48000, 88200, 96000, 128000 };
1588 static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1589                 .count = ARRAY_SIZE(rate_constraints),
1590                 .list = rate_constraints,
1591                 .mask = 0,
1592 };
1593
1594 /*
1595  * check device open/close
1596  */
1597 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1598 {
1599         int ch = mode & CM_OPEN_CH_MASK;
1600
1601         /* FIXME: a file should wait until the device becomes free
1602          * when it's opened on blocking mode.  however, since the current
1603          * pcm framework doesn't pass file pointer before actually opened,
1604          * we can't know whether blocking mode or not in open callback..
1605          */
1606         mutex_lock(&cm->open_mutex);
1607         if (cm->opened[ch]) {
1608                 mutex_unlock(&cm->open_mutex);
1609                 return -EBUSY;
1610         }
1611         cm->opened[ch] = mode;
1612         cm->channel[ch].substream = subs;
1613         if (! (mode & CM_OPEN_DAC)) {
1614                 /* disable dual DAC mode */
1615                 cm->channel[ch].is_dac = 0;
1616                 spin_lock_irq(&cm->reg_lock);
1617                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1618                 spin_unlock_irq(&cm->reg_lock);
1619         }
1620         mutex_unlock(&cm->open_mutex);
1621         return 0;
1622 }
1623
1624 static void close_device_check(struct cmipci *cm, int mode)
1625 {
1626         int ch = mode & CM_OPEN_CH_MASK;
1627
1628         mutex_lock(&cm->open_mutex);
1629         if (cm->opened[ch] == mode) {
1630                 if (cm->channel[ch].substream) {
1631                         snd_cmipci_ch_reset(cm, ch);
1632                         cm->channel[ch].running = 0;
1633                         cm->channel[ch].substream = NULL;
1634                 }
1635                 cm->opened[ch] = 0;
1636                 if (! cm->channel[ch].is_dac) {
1637                         /* enable dual DAC mode again */
1638                         cm->channel[ch].is_dac = 1;
1639                         spin_lock_irq(&cm->reg_lock);
1640                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1641                         spin_unlock_irq(&cm->reg_lock);
1642                 }
1643         }
1644         mutex_unlock(&cm->open_mutex);
1645 }
1646
1647 /*
1648  */
1649
1650 static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1651 {
1652         struct cmipci *cm = snd_pcm_substream_chip(substream);
1653         struct snd_pcm_runtime *runtime = substream->runtime;
1654         int err;
1655
1656         if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1657                 return err;
1658         runtime->hw = snd_cmipci_playback;
1659         if (cm->chip_version == 68) {
1660                 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1661                                      SNDRV_PCM_RATE_96000;
1662                 runtime->hw.rate_max = 96000;
1663         } else if (cm->chip_version == 55) {
1664                 err = snd_pcm_hw_constraint_list(runtime, 0,
1665                         SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1666                 if (err < 0)
1667                         return err;
1668                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1669                 runtime->hw.rate_max = 128000;
1670         }
1671         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1672         cm->dig_pcm_status = cm->dig_status;
1673         return 0;
1674 }
1675
1676 static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1677 {
1678         struct cmipci *cm = snd_pcm_substream_chip(substream);
1679         struct snd_pcm_runtime *runtime = substream->runtime;
1680         int err;
1681
1682         if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1683                 return err;
1684         runtime->hw = snd_cmipci_capture;
1685         if (cm->chip_version == 68) {   // 8768 only supports 44k/48k recording
1686                 runtime->hw.rate_min = 41000;
1687                 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1688         } else if (cm->chip_version == 55) {
1689                 err = snd_pcm_hw_constraint_list(runtime, 0,
1690                         SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1691                 if (err < 0)
1692                         return err;
1693                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1694                 runtime->hw.rate_max = 128000;
1695         }
1696         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1697         return 0;
1698 }
1699
1700 static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1701 {
1702         struct cmipci *cm = snd_pcm_substream_chip(substream);
1703         struct snd_pcm_runtime *runtime = substream->runtime;
1704         int err;
1705
1706         if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1707                 return err;
1708         runtime->hw = snd_cmipci_playback2;
1709         mutex_lock(&cm->open_mutex);
1710         if (! cm->opened[CM_CH_PLAY]) {
1711                 if (cm->can_multi_ch) {
1712                         runtime->hw.channels_max = cm->max_channels;
1713                         if (cm->max_channels == 4)
1714                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1715                         else if (cm->max_channels == 6)
1716                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1717                         else if (cm->max_channels == 8)
1718                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1719                 }
1720         }
1721         mutex_unlock(&cm->open_mutex);
1722         if (cm->chip_version == 68) {
1723                 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1724                                      SNDRV_PCM_RATE_96000;
1725                 runtime->hw.rate_max = 96000;
1726         } else if (cm->chip_version == 55) {
1727                 err = snd_pcm_hw_constraint_list(runtime, 0,
1728                         SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1729                 if (err < 0)
1730                         return err;
1731                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1732                 runtime->hw.rate_max = 128000;
1733         }
1734         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1735         return 0;
1736 }
1737
1738 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1739 {
1740         struct cmipci *cm = snd_pcm_substream_chip(substream);
1741         struct snd_pcm_runtime *runtime = substream->runtime;
1742         int err;
1743
1744         if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1745                 return err;
1746         if (cm->can_ac3_hw) {
1747                 runtime->hw = snd_cmipci_playback_spdif;
1748                 if (cm->chip_version >= 37) {
1749                         runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1750                         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1751                 }
1752                 if (cm->can_96k) {
1753                         runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1754                                              SNDRV_PCM_RATE_96000;
1755                         runtime->hw.rate_max = 96000;
1756                 }
1757         } else {
1758                 runtime->hw = snd_cmipci_playback_iec958_subframe;
1759         }
1760         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1761         cm->dig_pcm_status = cm->dig_status;
1762         return 0;
1763 }
1764
1765 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1766 {
1767         struct cmipci *cm = snd_pcm_substream_chip(substream);
1768         struct snd_pcm_runtime *runtime = substream->runtime;
1769         int err;
1770
1771         if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1772                 return err;
1773         runtime->hw = snd_cmipci_capture_spdif;
1774         if (cm->can_96k && !(cm->chip_version == 68)) {
1775                 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1776                                      SNDRV_PCM_RATE_96000;
1777                 runtime->hw.rate_max = 96000;
1778         }
1779         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1780         return 0;
1781 }
1782
1783
1784 /*
1785  */
1786
1787 static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1788 {
1789         struct cmipci *cm = snd_pcm_substream_chip(substream);
1790         close_device_check(cm, CM_OPEN_PLAYBACK);
1791         return 0;
1792 }
1793
1794 static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1795 {
1796         struct cmipci *cm = snd_pcm_substream_chip(substream);
1797         close_device_check(cm, CM_OPEN_CAPTURE);
1798         return 0;
1799 }
1800
1801 static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1802 {
1803         struct cmipci *cm = snd_pcm_substream_chip(substream);
1804         close_device_check(cm, CM_OPEN_PLAYBACK2);
1805         close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1806         return 0;
1807 }
1808
1809 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1810 {
1811         struct cmipci *cm = snd_pcm_substream_chip(substream);
1812         close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1813         return 0;
1814 }
1815
1816 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1817 {
1818         struct cmipci *cm = snd_pcm_substream_chip(substream);
1819         close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1820         return 0;
1821 }
1822
1823
1824 /*
1825  */
1826
1827 static const struct snd_pcm_ops snd_cmipci_playback_ops = {
1828         .open =         snd_cmipci_playback_open,
1829         .close =        snd_cmipci_playback_close,
1830         .ioctl =        snd_pcm_lib_ioctl,
1831         .hw_params =    snd_cmipci_hw_params,
1832         .hw_free =      snd_cmipci_playback_hw_free,
1833         .prepare =      snd_cmipci_playback_prepare,
1834         .trigger =      snd_cmipci_playback_trigger,
1835         .pointer =      snd_cmipci_playback_pointer,
1836 };
1837
1838 static const struct snd_pcm_ops snd_cmipci_capture_ops = {
1839         .open =         snd_cmipci_capture_open,
1840         .close =        snd_cmipci_capture_close,
1841         .ioctl =        snd_pcm_lib_ioctl,
1842         .hw_params =    snd_cmipci_hw_params,
1843         .hw_free =      snd_cmipci_hw_free,
1844         .prepare =      snd_cmipci_capture_prepare,
1845         .trigger =      snd_cmipci_capture_trigger,
1846         .pointer =      snd_cmipci_capture_pointer,
1847 };
1848
1849 static const struct snd_pcm_ops snd_cmipci_playback2_ops = {
1850         .open =         snd_cmipci_playback2_open,
1851         .close =        snd_cmipci_playback2_close,
1852         .ioctl =        snd_pcm_lib_ioctl,
1853         .hw_params =    snd_cmipci_playback2_hw_params,
1854         .hw_free =      snd_cmipci_playback2_hw_free,
1855         .prepare =      snd_cmipci_capture_prepare,     /* channel B */
1856         .trigger =      snd_cmipci_capture_trigger,     /* channel B */
1857         .pointer =      snd_cmipci_capture_pointer,     /* channel B */
1858 };
1859
1860 static const struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1861         .open =         snd_cmipci_playback_spdif_open,
1862         .close =        snd_cmipci_playback_spdif_close,
1863         .ioctl =        snd_pcm_lib_ioctl,
1864         .hw_params =    snd_cmipci_hw_params,
1865         .hw_free =      snd_cmipci_playback_hw_free,
1866         .prepare =      snd_cmipci_playback_spdif_prepare,      /* set up rate */
1867         .trigger =      snd_cmipci_playback_trigger,
1868         .pointer =      snd_cmipci_playback_pointer,
1869 };
1870
1871 static const struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1872         .open =         snd_cmipci_capture_spdif_open,
1873         .close =        snd_cmipci_capture_spdif_close,
1874         .ioctl =        snd_pcm_lib_ioctl,
1875         .hw_params =    snd_cmipci_hw_params,
1876         .hw_free =      snd_cmipci_capture_spdif_hw_free,
1877         .prepare =      snd_cmipci_capture_spdif_prepare,
1878         .trigger =      snd_cmipci_capture_trigger,
1879         .pointer =      snd_cmipci_capture_pointer,
1880 };
1881
1882
1883 /*
1884  */
1885
1886 static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
1887 {
1888         struct snd_pcm *pcm;
1889         int err;
1890
1891         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1892         if (err < 0)
1893                 return err;
1894
1895         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1896         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1897
1898         pcm->private_data = cm;
1899         pcm->info_flags = 0;
1900         strcpy(pcm->name, "C-Media PCI DAC/ADC");
1901         cm->pcm = pcm;
1902
1903         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1904                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1905
1906         return 0;
1907 }
1908
1909 static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1910 {
1911         struct snd_pcm *pcm;
1912         int err;
1913
1914         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1915         if (err < 0)
1916                 return err;
1917
1918         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1919
1920         pcm->private_data = cm;
1921         pcm->info_flags = 0;
1922         strcpy(pcm->name, "C-Media PCI 2nd DAC");
1923         cm->pcm2 = pcm;
1924
1925         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1926                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1927
1928         return 0;
1929 }
1930
1931 static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1932 {
1933         struct snd_pcm *pcm;
1934         int err;
1935
1936         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1937         if (err < 0)
1938                 return err;
1939
1940         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1941         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1942
1943         pcm->private_data = cm;
1944         pcm->info_flags = 0;
1945         strcpy(pcm->name, "C-Media PCI IEC958");
1946         cm->pcm_spdif = pcm;
1947
1948         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1949                                               snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1950
1951         err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1952                                      snd_pcm_alt_chmaps, cm->max_channels, 0,
1953                                      NULL);
1954         if (err < 0)
1955                 return err;
1956
1957         return 0;
1958 }
1959
1960 /*
1961  * mixer interface:
1962  * - CM8338/8738 has a compatible mixer interface with SB16, but
1963  *   lack of some elements like tone control, i/o gain and AGC.
1964  * - Access to native registers:
1965  *   - A 3D switch
1966  *   - Output mute switches
1967  */
1968
1969 static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1970 {
1971         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1972         outb(data, s->iobase + CM_REG_SB16_DATA);
1973 }
1974
1975 static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1976 {
1977         unsigned char v;
1978
1979         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1980         v = inb(s->iobase + CM_REG_SB16_DATA);
1981         return v;
1982 }
1983
1984 /*
1985  * general mixer element
1986  */
1987 struct cmipci_sb_reg {
1988         unsigned int left_reg, right_reg;
1989         unsigned int left_shift, right_shift;
1990         unsigned int mask;
1991         unsigned int invert: 1;
1992         unsigned int stereo: 1;
1993 };
1994
1995 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1996  ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1997
1998 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1999 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2000   .info = snd_cmipci_info_volume, \
2001   .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
2002   .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
2003 }
2004
2005 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
2006 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
2007 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
2008 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
2009
2010 static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
2011 {
2012         r->left_reg = val & 0xff;
2013         r->right_reg = (val >> 8) & 0xff;
2014         r->left_shift = (val >> 16) & 0x07;
2015         r->right_shift = (val >> 19) & 0x07;
2016         r->invert = (val >> 22) & 1;
2017         r->stereo = (val >> 23) & 1;
2018         r->mask = (val >> 24) & 0xff;
2019 }
2020
2021 static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
2022                                   struct snd_ctl_elem_info *uinfo)
2023 {
2024         struct cmipci_sb_reg reg;
2025
2026         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2027         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2028         uinfo->count = reg.stereo + 1;
2029         uinfo->value.integer.min = 0;
2030         uinfo->value.integer.max = reg.mask;
2031         return 0;
2032 }
2033
2034 static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
2035                                  struct snd_ctl_elem_value *ucontrol)
2036 {
2037         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2038         struct cmipci_sb_reg reg;
2039         int val;
2040
2041         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2042         spin_lock_irq(&cm->reg_lock);
2043         val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2044         if (reg.invert)
2045                 val = reg.mask - val;
2046         ucontrol->value.integer.value[0] = val;
2047         if (reg.stereo) {
2048                 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2049                 if (reg.invert)
2050                         val = reg.mask - val;
2051                 ucontrol->value.integer.value[1] = val;
2052         }
2053         spin_unlock_irq(&cm->reg_lock);
2054         return 0;
2055 }
2056
2057 static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2058                                  struct snd_ctl_elem_value *ucontrol)
2059 {
2060         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2061         struct cmipci_sb_reg reg;
2062         int change;
2063         int left, right, oleft, oright;
2064
2065         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2066         left = ucontrol->value.integer.value[0] & reg.mask;
2067         if (reg.invert)
2068                 left = reg.mask - left;
2069         left <<= reg.left_shift;
2070         if (reg.stereo) {
2071                 right = ucontrol->value.integer.value[1] & reg.mask;
2072                 if (reg.invert)
2073                         right = reg.mask - right;
2074                 right <<= reg.right_shift;
2075         } else
2076                 right = 0;
2077         spin_lock_irq(&cm->reg_lock);
2078         oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2079         left |= oleft & ~(reg.mask << reg.left_shift);
2080         change = left != oleft;
2081         if (reg.stereo) {
2082                 if (reg.left_reg != reg.right_reg) {
2083                         snd_cmipci_mixer_write(cm, reg.left_reg, left);
2084                         oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2085                 } else
2086                         oright = left;
2087                 right |= oright & ~(reg.mask << reg.right_shift);
2088                 change |= right != oright;
2089                 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2090         } else
2091                 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2092         spin_unlock_irq(&cm->reg_lock);
2093         return change;
2094 }
2095
2096 /*
2097  * input route (left,right) -> (left,right)
2098  */
2099 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2100 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2101   .info = snd_cmipci_info_input_sw, \
2102   .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2103   .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2104 }
2105
2106 static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2107                                     struct snd_ctl_elem_info *uinfo)
2108 {
2109         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2110         uinfo->count = 4;
2111         uinfo->value.integer.min = 0;
2112         uinfo->value.integer.max = 1;
2113         return 0;
2114 }
2115
2116 static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2117                                    struct snd_ctl_elem_value *ucontrol)
2118 {
2119         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2120         struct cmipci_sb_reg reg;
2121         int val1, val2;
2122
2123         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2124         spin_lock_irq(&cm->reg_lock);
2125         val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2126         val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2127         spin_unlock_irq(&cm->reg_lock);
2128         ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2129         ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2130         ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2131         ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2132         return 0;
2133 }
2134
2135 static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2136                                    struct snd_ctl_elem_value *ucontrol)
2137 {
2138         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2139         struct cmipci_sb_reg reg;
2140         int change;
2141         int val1, val2, oval1, oval2;
2142
2143         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2144         spin_lock_irq(&cm->reg_lock);
2145         oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2146         oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2147         val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2148         val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2149         val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2150         val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2151         val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2152         val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2153         change = val1 != oval1 || val2 != oval2;
2154         snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2155         snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2156         spin_unlock_irq(&cm->reg_lock);
2157         return change;
2158 }
2159
2160 /*
2161  * native mixer switches/volumes
2162  */
2163
2164 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2165 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2166   .info = snd_cmipci_info_native_mixer, \
2167   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2168   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2169 }
2170
2171 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2172 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2173   .info = snd_cmipci_info_native_mixer, \
2174   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2175   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2176 }
2177
2178 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2179 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2180   .info = snd_cmipci_info_native_mixer, \
2181   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2182   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2183 }
2184
2185 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2186 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2187   .info = snd_cmipci_info_native_mixer, \
2188   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2189   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2190 }
2191
2192 static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2193                                         struct snd_ctl_elem_info *uinfo)
2194 {
2195         struct cmipci_sb_reg reg;
2196
2197         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2198         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2199         uinfo->count = reg.stereo + 1;
2200         uinfo->value.integer.min = 0;
2201         uinfo->value.integer.max = reg.mask;
2202         return 0;
2203
2204 }
2205
2206 static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2207                                        struct snd_ctl_elem_value *ucontrol)
2208 {
2209         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2210         struct cmipci_sb_reg reg;
2211         unsigned char oreg, val;
2212
2213         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2214         spin_lock_irq(&cm->reg_lock);
2215         oreg = inb(cm->iobase + reg.left_reg);
2216         val = (oreg >> reg.left_shift) & reg.mask;
2217         if (reg.invert)
2218                 val = reg.mask - val;
2219         ucontrol->value.integer.value[0] = val;
2220         if (reg.stereo) {
2221                 val = (oreg >> reg.right_shift) & reg.mask;
2222                 if (reg.invert)
2223                         val = reg.mask - val;
2224                 ucontrol->value.integer.value[1] = val;
2225         }
2226         spin_unlock_irq(&cm->reg_lock);
2227         return 0;
2228 }
2229
2230 static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2231                                        struct snd_ctl_elem_value *ucontrol)
2232 {
2233         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2234         struct cmipci_sb_reg reg;
2235         unsigned char oreg, nreg, val;
2236
2237         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2238         spin_lock_irq(&cm->reg_lock);
2239         oreg = inb(cm->iobase + reg.left_reg);
2240         val = ucontrol->value.integer.value[0] & reg.mask;
2241         if (reg.invert)
2242                 val = reg.mask - val;
2243         nreg = oreg & ~(reg.mask << reg.left_shift);
2244         nreg |= (val << reg.left_shift);
2245         if (reg.stereo) {
2246                 val = ucontrol->value.integer.value[1] & reg.mask;
2247                 if (reg.invert)
2248                         val = reg.mask - val;
2249                 nreg &= ~(reg.mask << reg.right_shift);
2250                 nreg |= (val << reg.right_shift);
2251         }
2252         outb(nreg, cm->iobase + reg.left_reg);
2253         spin_unlock_irq(&cm->reg_lock);
2254         return (nreg != oreg);
2255 }
2256
2257 /*
2258  * special case - check mixer sensitivity
2259  */
2260 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2261                                                  struct snd_ctl_elem_value *ucontrol)
2262 {
2263         //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2264         return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2265 }
2266
2267 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2268                                                  struct snd_ctl_elem_value *ucontrol)
2269 {
2270         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2271         if (cm->mixer_insensitive) {
2272                 /* ignored */
2273                 return 0;
2274         }
2275         return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2276 }
2277
2278
2279 static struct snd_kcontrol_new snd_cmipci_mixers[] = {
2280         CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2281         CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2282         CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2283         //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2284         { /* switch with sensitivity */
2285                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2286                 .name = "PCM Playback Switch",
2287                 .info = snd_cmipci_info_native_mixer,
2288                 .get = snd_cmipci_get_native_mixer_sensitive,
2289                 .put = snd_cmipci_put_native_mixer_sensitive,
2290                 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2291         },
2292         CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2293         CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2294         CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2295         CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2296         CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2297         CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2298         CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2299         CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2300         CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2301         CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2302         CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2303         CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2304         CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2305         CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2306         CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2307         CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2308         CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2309         CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2310         CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2311         CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2312         CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2313         CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2314         CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2315 };
2316
2317 /*
2318  * other switches
2319  */
2320
2321 struct cmipci_switch_args {
2322         int reg;                /* register index */
2323         unsigned int mask;      /* mask bits */
2324         unsigned int mask_on;   /* mask bits to turn on */
2325         unsigned int is_byte: 1;                /* byte access? */
2326         unsigned int ac3_sensitive: 1;  /* access forbidden during
2327                                          * non-audio operation?
2328                                          */
2329 };
2330
2331 #define snd_cmipci_uswitch_info         snd_ctl_boolean_mono_info
2332
2333 static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2334                                    struct snd_ctl_elem_value *ucontrol,
2335                                    struct cmipci_switch_args *args)
2336 {
2337         unsigned int val;
2338         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2339
2340         spin_lock_irq(&cm->reg_lock);
2341         if (args->ac3_sensitive && cm->mixer_insensitive) {
2342                 ucontrol->value.integer.value[0] = 0;
2343                 spin_unlock_irq(&cm->reg_lock);
2344                 return 0;
2345         }
2346         if (args->is_byte)
2347                 val = inb(cm->iobase + args->reg);
2348         else
2349                 val = snd_cmipci_read(cm, args->reg);
2350         ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2351         spin_unlock_irq(&cm->reg_lock);
2352         return 0;
2353 }
2354
2355 static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2356                                   struct snd_ctl_elem_value *ucontrol)
2357 {
2358         struct cmipci_switch_args *args;
2359         args = (struct cmipci_switch_args *)kcontrol->private_value;
2360         if (snd_BUG_ON(!args))
2361                 return -EINVAL;
2362         return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2363 }
2364
2365 static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2366                                    struct snd_ctl_elem_value *ucontrol,
2367                                    struct cmipci_switch_args *args)
2368 {
2369         unsigned int val;
2370         int change;
2371         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2372
2373         spin_lock_irq(&cm->reg_lock);
2374         if (args->ac3_sensitive && cm->mixer_insensitive) {
2375                 /* ignored */
2376                 spin_unlock_irq(&cm->reg_lock);
2377                 return 0;
2378         }
2379         if (args->is_byte)
2380                 val = inb(cm->iobase + args->reg);
2381         else
2382                 val = snd_cmipci_read(cm, args->reg);
2383         change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2384                         args->mask_on : (args->mask & ~args->mask_on));
2385         if (change) {
2386                 val &= ~args->mask;
2387                 if (ucontrol->value.integer.value[0])
2388                         val |= args->mask_on;
2389                 else
2390                         val |= (args->mask & ~args->mask_on);
2391                 if (args->is_byte)
2392                         outb((unsigned char)val, cm->iobase + args->reg);
2393                 else
2394                         snd_cmipci_write(cm, args->reg, val);
2395         }
2396         spin_unlock_irq(&cm->reg_lock);
2397         return change;
2398 }
2399
2400 static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2401                                   struct snd_ctl_elem_value *ucontrol)
2402 {
2403         struct cmipci_switch_args *args;
2404         args = (struct cmipci_switch_args *)kcontrol->private_value;
2405         if (snd_BUG_ON(!args))
2406                 return -EINVAL;
2407         return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2408 }
2409
2410 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2411 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2412   .reg = xreg, \
2413   .mask = xmask, \
2414   .mask_on = xmask_on, \
2415   .is_byte = xis_byte, \
2416   .ac3_sensitive = xac3, \
2417 }
2418
2419 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2420         DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2421
2422 #if 0 /* these will be controlled in pcm device */
2423 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2424 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2425 #endif
2426 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2427 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2428 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2429 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2430 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2431 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2432 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2433 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2434 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2435 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2436 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2437 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2438 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2439 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2440 #if CM_CH_PLAY == 1
2441 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2442 #else
2443 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2444 #endif
2445 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2446 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2447 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2448 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2449 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2450
2451 #define DEFINE_SWITCH(sname, stype, sarg) \
2452 { .name = sname, \
2453   .iface = stype, \
2454   .info = snd_cmipci_uswitch_info, \
2455   .get = snd_cmipci_uswitch_get, \
2456   .put = snd_cmipci_uswitch_put, \
2457   .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2458 }
2459
2460 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2461 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2462
2463
2464 /*
2465  * callbacks for spdif output switch
2466  * needs toggle two registers..
2467  */
2468 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2469                                         struct snd_ctl_elem_value *ucontrol)
2470 {
2471         int changed;
2472         changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2473         changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2474         return changed;
2475 }
2476
2477 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2478                                         struct snd_ctl_elem_value *ucontrol)
2479 {
2480         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2481         int changed;
2482         changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2483         changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2484         if (changed) {
2485                 if (ucontrol->value.integer.value[0]) {
2486                         if (chip->spdif_playback_avail)
2487                                 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2488                 } else {
2489                         if (chip->spdif_playback_avail)
2490                                 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2491                 }
2492         }
2493         chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2494         return changed;
2495 }
2496
2497
2498 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2499                                         struct snd_ctl_elem_info *uinfo)
2500 {
2501         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2502         static const char *const texts[3] = {
2503                 "Line-In", "Rear Output", "Bass Output"
2504         };
2505
2506         return snd_ctl_enum_info(uinfo, 1,
2507                                  cm->chip_version >= 39 ? 3 : 2, texts);
2508 }
2509
2510 static inline unsigned int get_line_in_mode(struct cmipci *cm)
2511 {
2512         unsigned int val;
2513         if (cm->chip_version >= 39) {
2514                 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2515                 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2516                         return 2;
2517         }
2518         val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2519         if (val & CM_REAR2LIN)
2520                 return 1;
2521         return 0;
2522 }
2523
2524 static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2525                                        struct snd_ctl_elem_value *ucontrol)
2526 {
2527         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2528
2529         spin_lock_irq(&cm->reg_lock);
2530         ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2531         spin_unlock_irq(&cm->reg_lock);
2532         return 0;
2533 }
2534
2535 static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2536                                        struct snd_ctl_elem_value *ucontrol)
2537 {
2538         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2539         int change;
2540
2541         spin_lock_irq(&cm->reg_lock);
2542         if (ucontrol->value.enumerated.item[0] == 2)
2543                 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2544         else
2545                 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2546         if (ucontrol->value.enumerated.item[0] == 1)
2547                 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2548         else
2549                 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2550         spin_unlock_irq(&cm->reg_lock);
2551         return change;
2552 }
2553
2554 static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2555                                        struct snd_ctl_elem_info *uinfo)
2556 {
2557         static const char *const texts[2] = { "Mic-In", "Center/LFE Output" };
2558
2559         return snd_ctl_enum_info(uinfo, 1, 2, texts);
2560 }
2561
2562 static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2563                                       struct snd_ctl_elem_value *ucontrol)
2564 {
2565         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2566         /* same bit as spdi_phase */
2567         spin_lock_irq(&cm->reg_lock);
2568         ucontrol->value.enumerated.item[0] =
2569                 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2570         spin_unlock_irq(&cm->reg_lock);
2571         return 0;
2572 }
2573
2574 static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2575                                       struct snd_ctl_elem_value *ucontrol)
2576 {
2577         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2578         int change;
2579
2580         spin_lock_irq(&cm->reg_lock);
2581         if (ucontrol->value.enumerated.item[0])
2582                 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2583         else
2584                 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2585         spin_unlock_irq(&cm->reg_lock);
2586         return change;
2587 }
2588
2589 /* both for CM8338/8738 */
2590 static struct snd_kcontrol_new snd_cmipci_mixer_switches[] = {
2591         DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2592         {
2593                 .name = "Line-In Mode",
2594                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2595                 .info = snd_cmipci_line_in_mode_info,
2596                 .get = snd_cmipci_line_in_mode_get,
2597                 .put = snd_cmipci_line_in_mode_put,
2598         },
2599 };
2600
2601 /* for non-multichannel chips */
2602 static struct snd_kcontrol_new snd_cmipci_nomulti_switch =
2603 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2604
2605 /* only for CM8738 */
2606 static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = {
2607 #if 0 /* controlled in pcm device */
2608         DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2609         DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2610         DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2611 #endif
2612         // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2613         { .name = "IEC958 Output Switch",
2614           .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2615           .info = snd_cmipci_uswitch_info,
2616           .get = snd_cmipci_spdout_enable_get,
2617           .put = snd_cmipci_spdout_enable_put,
2618         },
2619         DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2620         DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2621         DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2622 //      DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2623         DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2624         DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2625 };
2626
2627 /* only for model 033/037 */
2628 static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = {
2629         DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2630         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2631         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2632 };
2633
2634 /* only for model 039 or later */
2635 static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = {
2636         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2637         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2638         {
2639                 .name = "Mic-In Mode",
2640                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2641                 .info = snd_cmipci_mic_in_mode_info,
2642                 .get = snd_cmipci_mic_in_mode_get,
2643                 .put = snd_cmipci_mic_in_mode_put,
2644         }
2645 };
2646
2647 /* card control switches */
2648 static struct snd_kcontrol_new snd_cmipci_modem_switch =
2649 DEFINE_CARD_SWITCH("Modem", modem);
2650
2651
2652 static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2653 {
2654         struct snd_card *card;
2655         struct snd_kcontrol_new *sw;
2656         struct snd_kcontrol *kctl;
2657         unsigned int idx;
2658         int err;
2659
2660         if (snd_BUG_ON(!cm || !cm->card))
2661                 return -EINVAL;
2662
2663         card = cm->card;
2664
2665         strcpy(card->mixername, "CMedia PCI");
2666
2667         spin_lock_irq(&cm->reg_lock);
2668         snd_cmipci_mixer_write(cm, 0x00, 0x00);         /* mixer reset */
2669         spin_unlock_irq(&cm->reg_lock);
2670
2671         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2672                 if (cm->chip_version == 68) {   // 8768 has no PCM volume
2673                         if (!strcmp(snd_cmipci_mixers[idx].name,
2674                                 "PCM Playback Volume"))
2675                                 continue;
2676                 }
2677                 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2678                         return err;
2679         }
2680
2681         /* mixer switches */
2682         sw = snd_cmipci_mixer_switches;
2683         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2684                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2685                 if (err < 0)
2686                         return err;
2687         }
2688         if (! cm->can_multi_ch) {
2689                 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2690                 if (err < 0)
2691                         return err;
2692         }
2693         if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2694             cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2695                 sw = snd_cmipci_8738_mixer_switches;
2696                 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2697                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2698                         if (err < 0)
2699                                 return err;
2700                 }
2701                 if (cm->can_ac3_hw) {
2702                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2703                                 return err;
2704                         kctl->id.device = pcm_spdif_device;
2705                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2706                                 return err;
2707                         kctl->id.device = pcm_spdif_device;
2708                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2709                                 return err;
2710                         kctl->id.device = pcm_spdif_device;
2711                 }
2712                 if (cm->chip_version <= 37) {
2713                         sw = snd_cmipci_old_mixer_switches;
2714                         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2715                                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2716                                 if (err < 0)
2717                                         return err;
2718                         }
2719                 }
2720         }
2721         if (cm->chip_version >= 39) {
2722                 sw = snd_cmipci_extra_mixer_switches;
2723                 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2724                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2725                         if (err < 0)
2726                                 return err;
2727                 }
2728         }
2729
2730         /* card switches */
2731         /*
2732          * newer chips don't have the register bits to force modem link
2733          * detection; the bit that was FLINKON now mutes CH1
2734          */
2735         if (cm->chip_version < 39) {
2736                 err = snd_ctl_add(cm->card,
2737                                   snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2738                 if (err < 0)
2739                         return err;
2740         }
2741
2742         for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2743                 struct snd_ctl_elem_id elem_id;
2744                 struct snd_kcontrol *ctl;
2745                 memset(&elem_id, 0, sizeof(elem_id));
2746                 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2747                 strcpy(elem_id.name, cm_saved_mixer[idx].name);
2748                 ctl = snd_ctl_find_id(cm->card, &elem_id);
2749                 if (ctl)
2750                         cm->mixer_res_ctl[idx] = ctl;
2751         }
2752
2753         return 0;
2754 }
2755
2756
2757 /*
2758  * proc interface
2759  */
2760
2761 static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2762                                  struct snd_info_buffer *buffer)
2763 {
2764         struct cmipci *cm = entry->private_data;
2765         int i, v;
2766
2767         snd_iprintf(buffer, "%s\n", cm->card->longname);
2768         for (i = 0; i < 0x94; i++) {
2769                 if (i == 0x28)
2770                         i = 0x90;
2771                 v = inb(cm->iobase + i);
2772                 if (i % 4 == 0)
2773                         snd_iprintf(buffer, "\n%02x:", i);
2774                 snd_iprintf(buffer, " %02x", v);
2775         }
2776         snd_iprintf(buffer, "\n");
2777 }
2778
2779 static void snd_cmipci_proc_init(struct cmipci *cm)
2780 {
2781         snd_card_ro_proc_new(cm->card, "cmipci", cm, snd_cmipci_proc_read);
2782 }
2783
2784 static const struct pci_device_id snd_cmipci_ids[] = {
2785         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0},
2786         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0},
2787         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2788         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0},
2789         {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2790         {0,},
2791 };
2792
2793
2794 /*
2795  * check chip version and capabilities
2796  * driver name is modified according to the chip model
2797  */
2798 static void query_chip(struct cmipci *cm)
2799 {
2800         unsigned int detect;
2801
2802         /* check reg 0Ch, bit 24-31 */
2803         detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2804         if (! detect) {
2805                 /* check reg 08h, bit 24-28 */
2806                 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2807                 switch (detect) {
2808                 case 0:
2809                         cm->chip_version = 33;
2810                         if (cm->do_soft_ac3)
2811                                 cm->can_ac3_sw = 1;
2812                         else
2813                                 cm->can_ac3_hw = 1;
2814                         break;
2815                 case CM_CHIP_037:
2816                         cm->chip_version = 37;
2817                         cm->can_ac3_hw = 1;
2818                         break;
2819                 default:
2820                         cm->chip_version = 39;
2821                         cm->can_ac3_hw = 1;
2822                         break;
2823                 }
2824                 cm->max_channels = 2;
2825         } else {
2826                 if (detect & CM_CHIP_039) {
2827                         cm->chip_version = 39;
2828                         if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2829                                 cm->max_channels = 6;
2830                         else
2831                                 cm->max_channels = 4;
2832                 } else if (detect & CM_CHIP_8768) {
2833                         cm->chip_version = 68;
2834                         cm->max_channels = 8;
2835                         cm->can_96k = 1;
2836                 } else {
2837                         cm->chip_version = 55;
2838                         cm->max_channels = 6;
2839                         cm->can_96k = 1;
2840                 }
2841                 cm->can_ac3_hw = 1;
2842                 cm->can_multi_ch = 1;
2843         }
2844 }
2845
2846 #ifdef SUPPORT_JOYSTICK
2847 static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2848 {
2849         static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2850         struct gameport *gp;
2851         struct resource *r = NULL;
2852         int i, io_port = 0;
2853
2854         if (joystick_port[dev] == 0)
2855                 return -ENODEV;
2856
2857         if (joystick_port[dev] == 1) { /* auto-detect */
2858                 for (i = 0; ports[i]; i++) {
2859                         io_port = ports[i];
2860                         r = request_region(io_port, 1, "CMIPCI gameport");
2861                         if (r)
2862                                 break;
2863                 }
2864         } else {
2865                 io_port = joystick_port[dev];
2866                 r = request_region(io_port, 1, "CMIPCI gameport");
2867         }
2868
2869         if (!r) {
2870                 dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
2871                 return -EBUSY;
2872         }
2873
2874         cm->gameport = gp = gameport_allocate_port();
2875         if (!gp) {
2876                 dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
2877                 release_and_free_resource(r);
2878                 return -ENOMEM;
2879         }
2880         gameport_set_name(gp, "C-Media Gameport");
2881         gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2882         gameport_set_dev_parent(gp, &cm->pci->dev);
2883         gp->io = io_port;
2884         gameport_set_port_data(gp, r);
2885
2886         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2887
2888         gameport_register_port(cm->gameport);
2889
2890         return 0;
2891 }
2892
2893 static void snd_cmipci_free_gameport(struct cmipci *cm)
2894 {
2895         if (cm->gameport) {
2896                 struct resource *r = gameport_get_port_data(cm->gameport);
2897
2898                 gameport_unregister_port(cm->gameport);
2899                 cm->gameport = NULL;
2900
2901                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2902                 release_and_free_resource(r);
2903         }
2904 }
2905 #else
2906 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2907 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2908 #endif
2909
2910 static int snd_cmipci_free(struct cmipci *cm)
2911 {
2912         if (cm->irq >= 0) {
2913                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2914                 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2915                 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);  /* disable ints */
2916                 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2917                 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2918                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2919                 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2920
2921                 /* reset mixer */
2922                 snd_cmipci_mixer_write(cm, 0, 0);
2923
2924                 free_irq(cm->irq, cm);
2925         }
2926
2927         snd_cmipci_free_gameport(cm);
2928         pci_release_regions(cm->pci);
2929         pci_disable_device(cm->pci);
2930         kfree(cm);
2931         return 0;
2932 }
2933
2934 static int snd_cmipci_dev_free(struct snd_device *device)
2935 {
2936         struct cmipci *cm = device->device_data;
2937         return snd_cmipci_free(cm);
2938 }
2939
2940 static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2941 {
2942         long iosynth;
2943         unsigned int val;
2944         struct snd_opl3 *opl3;
2945         int err;
2946
2947         if (!fm_port)
2948                 goto disable_fm;
2949
2950         if (cm->chip_version >= 39) {
2951                 /* first try FM regs in PCI port range */
2952                 iosynth = cm->iobase + CM_REG_FM_PCI;
2953                 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2954                                       OPL3_HW_OPL3, 1, &opl3);
2955         } else {
2956                 err = -EIO;
2957         }
2958         if (err < 0) {
2959                 /* then try legacy ports */
2960                 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2961                 iosynth = fm_port;
2962                 switch (iosynth) {
2963                 case 0x3E8: val |= CM_FMSEL_3E8; break;
2964                 case 0x3E0: val |= CM_FMSEL_3E0; break;
2965                 case 0x3C8: val |= CM_FMSEL_3C8; break;
2966                 case 0x388: val |= CM_FMSEL_388; break;
2967                 default:
2968                         goto disable_fm;
2969                 }
2970                 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2971                 /* enable FM */
2972                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2973
2974                 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2975                                     OPL3_HW_OPL3, 0, &opl3) < 0) {
2976                         dev_err(cm->card->dev,
2977                                 "no OPL device at %#lx, skipping...\n",
2978                                 iosynth);
2979                         goto disable_fm;
2980                 }
2981         }
2982         if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
2983                 dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
2984                 return err;
2985         }
2986         return 0;
2987
2988  disable_fm:
2989         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2990         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2991         return 0;
2992 }
2993
2994 static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2995                              int dev, struct cmipci **rcmipci)
2996 {
2997         struct cmipci *cm;
2998         int err;
2999         static struct snd_device_ops ops = {
3000                 .dev_free =     snd_cmipci_dev_free,
3001         };
3002         unsigned int val;
3003         long iomidi = 0;
3004         int integrated_midi = 0;
3005         char modelstr[16];
3006         int pcm_index, pcm_spdif_index;
3007         static const struct pci_device_id intel_82437vx[] = {
3008                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
3009                 { },
3010         };
3011
3012         *rcmipci = NULL;
3013
3014         if ((err = pci_enable_device(pci)) < 0)
3015                 return err;
3016
3017         cm = kzalloc(sizeof(*cm), GFP_KERNEL);
3018         if (cm == NULL) {
3019                 pci_disable_device(pci);
3020                 return -ENOMEM;
3021         }
3022
3023         spin_lock_init(&cm->reg_lock);
3024         mutex_init(&cm->open_mutex);
3025         cm->device = pci->device;
3026         cm->card = card;
3027         cm->pci = pci;
3028         cm->irq = -1;
3029         cm->channel[0].ch = 0;
3030         cm->channel[1].ch = 1;
3031         cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
3032
3033         if ((err = pci_request_regions(pci, card->driver)) < 0) {
3034                 kfree(cm);
3035                 pci_disable_device(pci);
3036                 return err;
3037         }
3038         cm->iobase = pci_resource_start(pci, 0);
3039
3040         if (request_irq(pci->irq, snd_cmipci_interrupt,
3041                         IRQF_SHARED, KBUILD_MODNAME, cm)) {
3042                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3043                 snd_cmipci_free(cm);
3044                 return -EBUSY;
3045         }
3046         cm->irq = pci->irq;
3047
3048         pci_set_master(cm->pci);
3049
3050         /*
3051          * check chip version, max channels and capabilities
3052          */
3053
3054         cm->chip_version = 0;
3055         cm->max_channels = 2;
3056         cm->do_soft_ac3 = soft_ac3[dev];
3057
3058         if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3059             pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3060                 query_chip(cm);
3061         /* added -MCx suffix for chip supporting multi-channels */
3062         if (cm->can_multi_ch)
3063                 sprintf(cm->card->driver + strlen(cm->card->driver),
3064                         "-MC%d", cm->max_channels);
3065         else if (cm->can_ac3_sw)
3066                 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3067
3068         cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3069         cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3070
3071 #if CM_CH_PLAY == 1
3072         cm->ctrl = CM_CHADC0;   /* default FUNCNTRL0 */
3073 #else
3074         cm->ctrl = CM_CHADC1;   /* default FUNCNTRL0 */
3075 #endif
3076
3077         /* initialize codec registers */
3078         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3079         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3080         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);     /* disable ints */
3081         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3082         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3083         snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0);       /* disable channels */
3084         snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3085
3086         snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3087         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3088 #if CM_CH_PLAY == 1
3089         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3090 #else
3091         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3092 #endif
3093         if (cm->chip_version) {
3094                 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3095                 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3096         }
3097         /* Set Bus Master Request */
3098         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3099
3100         /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3101         switch (pci->device) {
3102         case PCI_DEVICE_ID_CMEDIA_CM8738:
3103         case PCI_DEVICE_ID_CMEDIA_CM8738B:
3104                 if (!pci_dev_present(intel_82437vx))
3105                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3106                 break;
3107         default:
3108                 break;
3109         }
3110
3111         if (cm->chip_version < 68) {
3112                 val = pci->device < 0x110 ? 8338 : 8738;
3113         } else {
3114                 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3115                 case 0:
3116                         val = 8769;
3117                         break;
3118                 case 2:
3119                         val = 8762;
3120                         break;
3121                 default:
3122                         switch ((pci->subsystem_vendor << 16) |
3123                                 pci->subsystem_device) {
3124                         case 0x13f69761:
3125                         case 0x584d3741:
3126                         case 0x584d3751:
3127                         case 0x584d3761:
3128                         case 0x584d3771:
3129                         case 0x72848384:
3130                                 val = 8770;
3131                                 break;
3132                         default:
3133                                 val = 8768;
3134                                 break;
3135                         }
3136                 }
3137         }
3138         sprintf(card->shortname, "C-Media CMI%d", val);
3139         if (cm->chip_version < 68)
3140                 sprintf(modelstr, " (model %d)", cm->chip_version);
3141         else
3142                 modelstr[0] = '\0';
3143         sprintf(card->longname, "%s%s at %#lx, irq %i",
3144                 card->shortname, modelstr, cm->iobase, cm->irq);
3145
3146         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
3147                 snd_cmipci_free(cm);
3148                 return err;
3149         }
3150
3151         if (cm->chip_version >= 39) {
3152                 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3153                 if (val != 0x00 && val != 0xff) {
3154                         iomidi = cm->iobase + CM_REG_MPU_PCI;
3155                         integrated_midi = 1;
3156                 }
3157         }
3158         if (!integrated_midi) {
3159                 val = 0;
3160                 iomidi = mpu_port[dev];
3161                 switch (iomidi) {
3162                 case 0x320: val = CM_VMPU_320; break;
3163                 case 0x310: val = CM_VMPU_310; break;
3164                 case 0x300: val = CM_VMPU_300; break;
3165                 case 0x330: val = CM_VMPU_330; break;
3166                 default:
3167                             iomidi = 0; break;
3168                 }
3169                 if (iomidi > 0) {
3170                         snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3171                         /* enable UART */
3172                         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3173                         if (inb(iomidi + 1) == 0xff) {
3174                                 dev_err(cm->card->dev,
3175                                         "cannot enable MPU-401 port at %#lx\n",
3176                                         iomidi);
3177                                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3178                                                      CM_UART_EN);
3179                                 iomidi = 0;
3180                         }
3181                 }
3182         }
3183
3184         if (cm->chip_version < 68) {
3185                 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3186                 if (err < 0)
3187                         return err;
3188         }
3189
3190         /* reset mixer */
3191         snd_cmipci_mixer_write(cm, 0, 0);
3192
3193         snd_cmipci_proc_init(cm);
3194
3195         /* create pcm devices */
3196         pcm_index = pcm_spdif_index = 0;
3197         if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3198                 return err;
3199         pcm_index++;
3200         if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3201                 return err;
3202         pcm_index++;
3203         if (cm->can_ac3_hw || cm->can_ac3_sw) {
3204                 pcm_spdif_index = pcm_index;
3205                 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3206                         return err;
3207         }
3208
3209         /* create mixer interface & switches */
3210         if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3211                 return err;
3212
3213         if (iomidi > 0) {
3214                 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3215                                                iomidi,
3216                                                (integrated_midi ?
3217                                                 MPU401_INFO_INTEGRATED : 0) |
3218                                                MPU401_INFO_IRQ_HOOK,
3219                                                -1, &cm->rmidi)) < 0) {
3220                         dev_err(cm->card->dev,
3221                                 "no UART401 device at 0x%lx\n", iomidi);
3222                 }
3223         }
3224
3225 #ifdef USE_VAR48KRATE
3226         for (val = 0; val < ARRAY_SIZE(rates); val++)
3227                 snd_cmipci_set_pll(cm, rates[val], val);
3228
3229         /*
3230          * (Re-)Enable external switch spdo_48k
3231          */
3232         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3233 #endif /* USE_VAR48KRATE */
3234
3235         if (snd_cmipci_create_gameport(cm, dev) < 0)
3236                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3237
3238         *rcmipci = cm;
3239         return 0;
3240 }
3241
3242 /*
3243  */
3244
3245 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3246
3247 static int snd_cmipci_probe(struct pci_dev *pci,
3248                             const struct pci_device_id *pci_id)
3249 {
3250         static int dev;
3251         struct snd_card *card;
3252         struct cmipci *cm;
3253         int err;
3254
3255         if (dev >= SNDRV_CARDS)
3256                 return -ENODEV;
3257         if (! enable[dev]) {
3258                 dev++;
3259                 return -ENOENT;
3260         }
3261
3262         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3263                            0, &card);
3264         if (err < 0)
3265                 return err;
3266
3267         switch (pci->device) {
3268         case PCI_DEVICE_ID_CMEDIA_CM8738:
3269         case PCI_DEVICE_ID_CMEDIA_CM8738B:
3270                 strcpy(card->driver, "CMI8738");
3271                 break;
3272         case PCI_DEVICE_ID_CMEDIA_CM8338A:
3273         case PCI_DEVICE_ID_CMEDIA_CM8338B:
3274                 strcpy(card->driver, "CMI8338");
3275                 break;
3276         default:
3277                 strcpy(card->driver, "CMIPCI");
3278                 break;
3279         }
3280
3281         err = snd_cmipci_create(card, pci, dev, &cm);
3282         if (err < 0)
3283                 goto free_card;
3284
3285         card->private_data = cm;
3286
3287         err = snd_card_register(card);
3288         if (err < 0)
3289                 goto free_card;
3290
3291         pci_set_drvdata(pci, card);
3292         dev++;
3293         return 0;
3294
3295 free_card:
3296         snd_card_free(card);
3297         return err;
3298 }
3299
3300 static void snd_cmipci_remove(struct pci_dev *pci)
3301 {
3302         snd_card_free(pci_get_drvdata(pci));
3303 }
3304
3305
3306 #ifdef CONFIG_PM_SLEEP
3307 /*
3308  * power management
3309  */
3310 static unsigned char saved_regs[] = {
3311         CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3312         CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_AUX_VOL, CM_REG_PLL,
3313         CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3314         CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3315         CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3316 };
3317
3318 static unsigned char saved_mixers[] = {
3319         SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3320         SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3321         SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3322         SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3323         SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3324         SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3325         CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3326         SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3327 };
3328
3329 static int snd_cmipci_suspend(struct device *dev)
3330 {
3331         struct snd_card *card = dev_get_drvdata(dev);
3332         struct cmipci *cm = card->private_data;
3333         int i;
3334
3335         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3336
3337         /* save registers */
3338         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3339                 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3340         for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3341                 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3342
3343         /* disable ints */
3344         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3345         return 0;
3346 }
3347
3348 static int snd_cmipci_resume(struct device *dev)
3349 {
3350         struct snd_card *card = dev_get_drvdata(dev);
3351         struct cmipci *cm = card->private_data;
3352         int i;
3353
3354         /* reset / initialize to a sane state */
3355         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3356         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3357         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3358         snd_cmipci_mixer_write(cm, 0, 0);
3359
3360         /* restore registers */
3361         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3362                 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3363         for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3364                 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3365
3366         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3367         return 0;
3368 }
3369
3370 static SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume);
3371 #define SND_CMIPCI_PM_OPS       &snd_cmipci_pm
3372 #else
3373 #define SND_CMIPCI_PM_OPS       NULL
3374 #endif /* CONFIG_PM_SLEEP */
3375
3376 static struct pci_driver cmipci_driver = {
3377         .name = KBUILD_MODNAME,
3378         .id_table = snd_cmipci_ids,
3379         .probe = snd_cmipci_probe,
3380         .remove = snd_cmipci_remove,
3381         .driver = {
3382                 .pm = SND_CMIPCI_PM_OPS,
3383         },
3384 };
3385
3386 module_pci_driver(cmipci_driver);