sound/pci/cmipci.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Driver for C-Media CMI8338 and 8738 PCI soundcards.
   4  * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
   5  */
   6
   7 /* Does not work. Warning may block system in capture mode */
   8 /* #define USE_VAR48KRATE */
   9
  10 #include <linux/io.h>
  11 #include <linux/delay.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/slab.h>
  16 #include <linux/gameport.h>
  17 #include <linux/module.h>
  18 #include <linux/mutex.h>
  19 #include <sound/core.h>
  20 #include <sound/info.h>
  21 #include <sound/control.h>
  22 #include <sound/pcm.h>
  23 #include <sound/rawmidi.h>
  24 #include <sound/mpu401.h>
  25 #include <sound/opl3.h>
  26 #include <sound/sb.h>
  27 #include <sound/asoundef.h>
  28 #include <sound/initval.h>
  29
  30 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
  31 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
  32 MODULE_LICENSE("GPL");
  33 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
  34                 "{C-Media,CMI8738B},"
  35                 "{C-Media,CMI8338A},"
  36                 "{C-Media,CMI8338B}}");
  37
  38 #if IS_REACHABLE(CONFIG_GAMEPORT)
  39 #define SUPPORT_JOYSTICK 1
  40 #endif
  41
  42 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  43 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  44 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable switches */
  45 static long mpu_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 1};
  46 static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
  47 static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
  48 #ifdef SUPPORT_JOYSTICK
  49 static int joystick_port[SNDRV_CARDS];
  50 #endif
  51
  52 module_param_array(index, int, NULL, 0444);
  53 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
  54 module_param_array(id, charp, NULL, 0444);
  55 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
  56 module_param_array(enable, bool, NULL, 0444);
  57 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
  58 module_param_hw_array(mpu_port, long, ioport, NULL, 0444);
  59 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
  60 module_param_hw_array(fm_port, long, ioport, NULL, 0444);
  61 MODULE_PARM_DESC(fm_port, "FM port.");
  62 module_param_array(soft_ac3, bool, NULL, 0444);
  63 MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only).");
  64 #ifdef SUPPORT_JOYSTICK
  65 module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
  66 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
  67 #endif
  68
  69 /*
  70  * CM8x38 registers definition
  71  */
  72
  73 #define CM_REG_FUNCTRL0         0x00
  74 #define CM_RST_CH1              0x00080000
  75 #define CM_RST_CH0              0x00040000
  76 #define CM_CHEN1                0x00020000      /* ch1: enable */
  77 #define CM_CHEN0                0x00010000      /* ch0: enable */
  78 #define CM_PAUSE1               0x00000008      /* ch1: pause */
  79 #define CM_PAUSE0               0x00000004      /* ch0: pause */
  80 #define CM_CHADC1               0x00000002      /* ch1, 0:playback, 1:record */
  81 #define CM_CHADC0               0x00000001      /* ch0, 0:playback, 1:record */
  82
  83 #define CM_REG_FUNCTRL1         0x04
  84 #define CM_DSFC_MASK            0x0000E000      /* channel 1 (DAC?) sampling frequency */
  85 #define CM_DSFC_SHIFT           13
  86 #define CM_ASFC_MASK            0x00001C00      /* channel 0 (ADC?) sampling frequency */
  87 #define CM_ASFC_SHIFT           10
  88 #define CM_SPDF_1               0x00000200      /* SPDIF IN/OUT at channel B */
  89 #define CM_SPDF_0               0x00000100      /* SPDIF OUT only channel A */
  90 #define CM_SPDFLOOP             0x00000080      /* ext. SPDIIF/IN -> OUT loopback */
  91 #define CM_SPDO2DAC             0x00000040      /* SPDIF/OUT can be heard from internal DAC */
  92 #define CM_INTRM                0x00000020      /* master control block (MCB) interrupt enabled */
  93 #define CM_BREQ                 0x00000010      /* bus master enabled */
  94 #define CM_VOICE_EN             0x00000008      /* legacy voice (SB16,FM) */
  95 #define CM_UART_EN              0x00000004      /* legacy UART */
  96 #define CM_JYSTK_EN             0x00000002      /* legacy joystick */
  97 #define CM_ZVPORT               0x00000001      /* ZVPORT */
  98
  99 #define CM_REG_CHFORMAT         0x08
 100
 101 #define CM_CHB3D5C              0x80000000      /* 5,6 channels */
 102 #define CM_FMOFFSET2            0x40000000      /* initial FM PCM offset 2 when Fmute=1 */
 103 #define CM_CHB3D                0x20000000      /* 4 channels */
 104
 105 #define CM_CHIP_MASK1           0x1f000000
 106 #define CM_CHIP_037             0x01000000
 107 #define CM_SETLAT48             0x00800000      /* set latency timer 48h */
 108 #define CM_EDGEIRQ              0x00400000      /* emulated edge trigger legacy IRQ */
 109 #define CM_SPD24SEL39           0x00200000      /* 24-bit spdif: model 039 */
 110 #define CM_AC3EN1               0x00100000      /* enable AC3: model 037 */
 111 #define CM_SPDIF_SELECT1        0x00080000      /* for model <= 037 ? */
 112 #define CM_SPD24SEL             0x00020000      /* 24bit spdif: model 037 */
 113 /* #define CM_SPDIF_INVERSE     0x00010000 */ /* ??? */
 114
 115 #define CM_ADCBITLEN_MASK       0x0000C000
 116 #define CM_ADCBITLEN_16         0x00000000
 117 #define CM_ADCBITLEN_15         0x00004000
 118 #define CM_ADCBITLEN_14         0x00008000
 119 #define CM_ADCBITLEN_13         0x0000C000
 120
 121 #define CM_ADCDACLEN_MASK       0x00003000      /* model 037 */
 122 #define CM_ADCDACLEN_060        0x00000000
 123 #define CM_ADCDACLEN_066        0x00001000
 124 #define CM_ADCDACLEN_130        0x00002000
 125 #define CM_ADCDACLEN_280        0x00003000
 126
 127 #define CM_ADCDLEN_MASK         0x00003000      /* model 039 */
 128 #define CM_ADCDLEN_ORIGINAL     0x00000000
 129 #define CM_ADCDLEN_EXTRA        0x00001000
 130 #define CM_ADCDLEN_24K          0x00002000
 131 #define CM_ADCDLEN_WEIGHT       0x00003000
 132
 133 #define CM_CH1_SRATE_176K       0x00000800
 134 #define CM_CH1_SRATE_96K        0x00000800      /* model 055? */
 135 #define CM_CH1_SRATE_88K        0x00000400
 136 #define CM_CH0_SRATE_176K       0x00000200
 137 #define CM_CH0_SRATE_96K        0x00000200      /* model 055? */
 138 #define CM_CH0_SRATE_88K        0x00000100
 139 #define CM_CH0_SRATE_128K       0x00000300
 140 #define CM_CH0_SRATE_MASK       0x00000300
 141
 142 #define CM_SPDIF_INVERSE2       0x00000080      /* model 055? */
 143 #define CM_DBLSPDS              0x00000040      /* double SPDIF sample rate 88.2/96 */
 144 #define CM_POLVALID             0x00000020      /* inverse SPDIF/IN valid bit */
 145 #define CM_SPDLOCKED            0x00000010
 146
 147 #define CM_CH1FMT_MASK          0x0000000C      /* bit 3: 16 bits, bit 2: stereo */
 148 #define CM_CH1FMT_SHIFT         2
 149 #define CM_CH0FMT_MASK          0x00000003      /* bit 1: 16 bits, bit 0: stereo */
 150 #define CM_CH0FMT_SHIFT         0
 151
 152 #define CM_REG_INT_HLDCLR       0x0C
 153 #define CM_CHIP_MASK2           0xff000000
 154 #define CM_CHIP_8768            0x20000000
 155 #define CM_CHIP_055             0x08000000
 156 #define CM_CHIP_039             0x04000000
 157 #define CM_CHIP_039_6CH         0x01000000
 158 #define CM_UNKNOWN_INT_EN       0x00080000      /* ? */
 159 #define CM_TDMA_INT_EN          0x00040000
 160 #define CM_CH1_INT_EN           0x00020000
 161 #define CM_CH0_INT_EN           0x00010000
 162
 163 #define CM_REG_INT_STATUS       0x10
 164 #define CM_INTR                 0x80000000
 165 #define CM_VCO                  0x08000000      /* Voice Control? CMI8738 */
 166 #define CM_MCBINT               0x04000000      /* Master Control Block abort cond.? */
 167 #define CM_UARTINT              0x00010000
 168 #define CM_LTDMAINT             0x00008000
 169 #define CM_HTDMAINT             0x00004000
 170 #define CM_XDO46                0x00000080      /* Modell 033? Direct programming EEPROM (read data register) */
 171 #define CM_LHBTOG               0x00000040      /* High/Low status from DMA ctrl register */
 172 #define CM_LEG_HDMA             0x00000020      /* Legacy is in High DMA channel */
 173 #define CM_LEG_STEREO           0x00000010      /* Legacy is in Stereo mode */
 174 #define CM_CH1BUSY              0x00000008
 175 #define CM_CH0BUSY              0x00000004
 176 #define CM_CHINT1               0x00000002
 177 #define CM_CHINT0               0x00000001
 178
 179 #define CM_REG_LEGACY_CTRL      0x14
 180 #define CM_NXCHG                0x80000000      /* don't map base reg dword->sample */
 181 #define CM_VMPU_MASK            0x60000000      /* MPU401 i/o port address */
 182 #define CM_VMPU_330             0x00000000
 183 #define CM_VMPU_320             0x20000000
 184 #define CM_VMPU_310             0x40000000
 185 #define CM_VMPU_300             0x60000000
 186 #define CM_ENWR8237             0x10000000      /* enable bus master to write 8237 base reg */
 187 #define CM_VSBSEL_MASK          0x0C000000      /* SB16 base address */
 188 #define CM_VSBSEL_220           0x00000000
 189 #define CM_VSBSEL_240           0x04000000
 190 #define CM_VSBSEL_260           0x08000000
 191 #define CM_VSBSEL_280           0x0C000000
 192 #define CM_FMSEL_MASK           0x03000000      /* FM OPL3 base address */
 193 #define CM_FMSEL_388            0x00000000
 194 #define CM_FMSEL_3C8            0x01000000
 195 #define CM_FMSEL_3E0            0x02000000
 196 #define CM_FMSEL_3E8            0x03000000
 197 #define CM_ENSPDOUT             0x00800000      /* enable XSPDIF/OUT to I/O interface */
 198 #define CM_SPDCOPYRHT           0x00400000      /* spdif in/out copyright bit */
 199 #define CM_DAC2SPDO             0x00200000      /* enable wave+fm_midi -> SPDIF/OUT */
 200 #define CM_INVIDWEN             0x00100000      /* internal vendor ID write enable, model 039? */
 201 #define CM_SETRETRY             0x00100000      /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
 202 #define CM_C_EEACCESS           0x00080000      /* direct programming eeprom regs */
 203 #define CM_C_EECS               0x00040000
 204 #define CM_C_EEDI46             0x00020000
 205 #define CM_C_EECK46             0x00010000
 206 #define CM_CHB3D6C              0x00008000      /* 5.1 channels support */
 207 #define CM_CENTR2LIN            0x00004000      /* line-in as center out */
 208 #define CM_BASE2LIN             0x00002000      /* line-in as bass out */
 209 #define CM_EXBASEN              0x00001000      /* external bass input enable */
 210
 211 #define CM_REG_MISC_CTRL        0x18
 212 #define CM_PWD                  0x80000000      /* power down */
 213 #define CM_RESET                0x40000000
 214 #define CM_SFIL_MASK            0x30000000      /* filter control at front end DAC, model 037? */
 215 #define CM_VMGAIN               0x10000000      /* analog master amp +6dB, model 039? */
 216 #define CM_TXVX                 0x08000000      /* model 037? */
 217 #define CM_N4SPK3D              0x04000000      /* copy front to rear */
 218 #define CM_SPDO5V               0x02000000      /* 5V spdif output (1 = 0.5v (coax)) */
 219 #define CM_SPDIF48K             0x01000000      /* write */
 220 #define CM_SPATUS48K            0x01000000      /* read */
 221 #define CM_ENDBDAC              0x00800000      /* enable double dac */
 222 #define CM_XCHGDAC              0x00400000      /* 0: front=ch0, 1: front=ch1 */
 223 #define CM_SPD32SEL             0x00200000      /* 0: 16bit SPDIF, 1: 32bit */
 224 #define CM_SPDFLOOPI            0x00100000      /* int. SPDIF-OUT -> int. IN */
 225 #define CM_FM_EN                0x00080000      /* enable legacy FM */
 226 #define CM_AC3EN2               0x00040000      /* enable AC3: model 039 */
 227 #define CM_ENWRASID             0x00010000      /* choose writable internal SUBID (audio) */
 228 #define CM_VIDWPDSB             0x00010000      /* model 037? */
 229 #define CM_SPDF_AC97            0x00008000      /* 0: SPDIF/OUT 44.1K, 1: 48K */
 230 #define CM_MASK_EN              0x00004000      /* activate channel mask on legacy DMA */
 231 #define CM_ENWRMSID             0x00002000      /* choose writable internal SUBID (modem) */
 232 #define CM_VIDWPPRT             0x00002000      /* model 037? */
 233 #define CM_SFILENB              0x00001000      /* filter stepping at front end DAC, model 037? */
 234 #define CM_MMODE_MASK           0x00000E00      /* model DAA interface mode */
 235 #define CM_SPDIF_SELECT2        0x00000100      /* for model > 039 ? */
 236 #define CM_ENCENTER             0x00000080
 237 #define CM_FLINKON              0x00000040      /* force modem link detection on, model 037 */
 238 #define CM_MUTECH1              0x00000040      /* mute PCI ch1 to DAC */
 239 #define CM_FLINKOFF             0x00000020      /* force modem link detection off, model 037 */
 240 #define CM_MIDSMP               0x00000010      /* 1/2 interpolation at front end DAC */
 241 #define CM_UPDDMA_MASK          0x0000000C      /* TDMA position update notification */
 242 #define CM_UPDDMA_2048          0x00000000
 243 #define CM_UPDDMA_1024          0x00000004
 244 #define CM_UPDDMA_512           0x00000008
 245 #define CM_UPDDMA_256           0x0000000C
 246 #define CM_TWAIT_MASK           0x00000003      /* model 037 */
 247 #define CM_TWAIT1               0x00000002      /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
 248 #define CM_TWAIT0               0x00000001      /* i/o cycle, 0: 4, 1: 6 PCICLKs */
 249
 250 #define CM_REG_TDMA_POSITION    0x1C
 251 #define CM_TDMA_CNT_MASK        0xFFFF0000      /* current byte/word count */
 252 #define CM_TDMA_ADR_MASK        0x0000FFFF      /* current address */
 253
 254         /* byte */
 255 #define CM_REG_MIXER0           0x20
 256 #define CM_REG_SBVR             0x20            /* write: sb16 version */
 257 #define CM_REG_DEV              0x20            /* read: hardware device version */
 258
 259 #define CM_REG_MIXER21          0x21
 260 #define CM_UNKNOWN_21_MASK      0x78            /* ? */
 261 #define CM_X_ADPCM              0x04            /* SB16 ADPCM enable */
 262 #define CM_PROINV               0x02            /* SBPro left/right channel switching */
 263 #define CM_X_SB16               0x01            /* SB16 compatible */
 264
 265 #define CM_REG_SB16_DATA        0x22
 266 #define CM_REG_SB16_ADDR        0x23
 267
 268 #define CM_REFFREQ_XIN          (315*1000*1000)/22      /* 14.31818 Mhz reference clock frequency pin XIN */
 269 #define CM_ADCMULT_XIN          512                     /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
 270 #define CM_TOLERANCE_RATE       0.001                   /* Tolerance sample rate pitch (1000ppm) */
 271 #define CM_MAXIMUM_RATE         80000000                /* Note more than 80MHz */
 272
 273 #define CM_REG_MIXER1           0x24
 274 #define CM_FMMUTE               0x80    /* mute FM */
 275 #define CM_FMMUTE_SHIFT         7
 276 #define CM_WSMUTE               0x40    /* mute PCM */
 277 #define CM_WSMUTE_SHIFT         6
 278 #define CM_REAR2LIN             0x20    /* lin-in -> rear line out */
 279 #define CM_REAR2LIN_SHIFT       5
 280 #define CM_REAR2FRONT           0x10    /* exchange rear/front */
 281 #define CM_REAR2FRONT_SHIFT     4
 282 #define CM_WAVEINL              0x08    /* digital wave rec. left chan */
 283 #define CM_WAVEINL_SHIFT        3
 284 #define CM_WAVEINR              0x04    /* digical wave rec. right */
 285 #define CM_WAVEINR_SHIFT        2
 286 #define CM_X3DEN                0x02    /* 3D surround enable */
 287 #define CM_X3DEN_SHIFT          1
 288 #define CM_CDPLAY               0x01    /* enable SPDIF/IN PCM -> DAC */
 289 #define CM_CDPLAY_SHIFT         0
 290
 291 #define CM_REG_MIXER2           0x25
 292 #define CM_RAUXREN              0x80    /* AUX right capture */
 293 #define CM_RAUXREN_SHIFT        7
 294 #define CM_RAUXLEN              0x40    /* AUX left capture */
 295 #define CM_RAUXLEN_SHIFT        6
 296 #define CM_VAUXRM               0x20    /* AUX right mute */
 297 #define CM_VAUXRM_SHIFT         5
 298 #define CM_VAUXLM               0x10    /* AUX left mute */
 299 #define CM_VAUXLM_SHIFT         4
 300 #define CM_VADMIC_MASK          0x0e    /* mic gain level (0-3) << 1 */
 301 #define CM_VADMIC_SHIFT         1
 302 #define CM_MICGAINZ             0x01    /* mic boost */
 303 #define CM_MICGAINZ_SHIFT       0
 304
 305 #define CM_REG_AUX_VOL          0x26
 306 #define CM_VAUXL_MASK           0xf0
 307 #define CM_VAUXR_MASK           0x0f
 308
 309 #define CM_REG_MISC             0x27
 310 #define CM_UNKNOWN_27_MASK      0xd8    /* ? */
 311 #define CM_XGPO1                0x20
 312 // #define CM_XGPBIO            0x04
 313 #define CM_MIC_CENTER_LFE       0x04    /* mic as center/lfe out? (model 039 or later?) */
 314 #define CM_SPDIF_INVERSE        0x04    /* spdif input phase inverse (model 037) */
 315 #define CM_SPDVALID             0x02    /* spdif input valid check */
 316 #define CM_DMAUTO               0x01    /* SB16 DMA auto detect */
 317
 318 #define CM_REG_AC97             0x28    /* hmmm.. do we have ac97 link? */
 319 /*
 320  * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
 321  * or identical with AC97 codec?
 322  */
 323 #define CM_REG_EXTERN_CODEC     CM_REG_AC97
 324
 325 /*
 326  * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
 327  */
 328 #define CM_REG_MPU_PCI          0x40
 329
 330 /*
 331  * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
 332  */
 333 #define CM_REG_FM_PCI           0x50
 334
 335 /*
 336  * access from SB-mixer port
 337  */
 338 #define CM_REG_EXTENT_IND       0xf0
 339 #define CM_VPHONE_MASK          0xe0    /* Phone volume control (0-3) << 5 */
 340 #define CM_VPHONE_SHIFT         5
 341 #define CM_VPHOM                0x10    /* Phone mute control */
 342 #define CM_VSPKM                0x08    /* Speaker mute control, default high */
 343 #define CM_RLOOPREN             0x04    /* Rec. R-channel enable */
 344 #define CM_RLOOPLEN             0x02    /* Rec. L-channel enable */
 345 #define CM_VADMIC3              0x01    /* Mic record boost */
 346
 347 /*
 348  * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
 349  * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
 350  * unit (readonly?).
 351  */
 352 #define CM_REG_PLL              0xf8
 353
 354 /*
 355  * extended registers
 356  */
 357 #define CM_REG_CH0_FRAME1       0x80    /* write: base address */
 358 #define CM_REG_CH0_FRAME2       0x84    /* read: current address */
 359 #define CM_REG_CH1_FRAME1       0x88    /* 0-15: count of samples at bus master; buffer size */
 360 #define CM_REG_CH1_FRAME2       0x8C    /* 16-31: count of samples at codec; fragment size */
 361
 362 #define CM_REG_EXT_MISC         0x90
 363 #define CM_ADC48K44K            0x10000000      /* ADC parameters group, 0: 44k, 1: 48k */
 364 #define CM_CHB3D8C              0x00200000      /* 7.1 channels support */
 365 #define CM_SPD32FMT             0x00100000      /* SPDIF/IN 32k sample rate */
 366 #define CM_ADC2SPDIF            0x00080000      /* ADC output to SPDIF/OUT */
 367 #define CM_SHAREADC             0x00040000      /* DAC in ADC as Center/LFE */
 368 #define CM_REALTCMP             0x00020000      /* monitor the CMPL/CMPR of ADC */
 369 #define CM_INVLRCK              0x00010000      /* invert ZVPORT's LRCK */
 370 #define CM_UNKNOWN_90_MASK      0x0000FFFF      /* ? */
 371
 372 /*
 373  * size of i/o region
 374  */
 375 #define CM_EXTENT_CODEC   0x100
 376 #define CM_EXTENT_MIDI    0x2
 377 #define CM_EXTENT_SYNTH   0x4
 378
 379
 380 /*
 381  * channels for playback / capture
 382  */
 383 #define CM_CH_PLAY      0
 384 #define CM_CH_CAPT      1
 385
 386 /*
 387  * flags to check device open/close
 388  */
 389 #define CM_OPEN_NONE    0
 390 #define CM_OPEN_CH_MASK 0x01
 391 #define CM_OPEN_DAC     0x10
 392 #define CM_OPEN_ADC     0x20
 393 #define CM_OPEN_SPDIF   0x40
 394 #define CM_OPEN_MCHAN   0x80
 395 #define CM_OPEN_PLAYBACK        (CM_CH_PLAY | CM_OPEN_DAC)
 396 #define CM_OPEN_PLAYBACK2       (CM_CH_CAPT | CM_OPEN_DAC)
 397 #define CM_OPEN_PLAYBACK_MULTI  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
 398 #define CM_OPEN_CAPTURE         (CM_CH_CAPT | CM_OPEN_ADC)
 399 #define CM_OPEN_SPDIF_PLAYBACK  (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
 400 #define CM_OPEN_SPDIF_CAPTURE   (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
 401
 402
 403 #if CM_CH_PLAY == 1
 404 #define CM_PLAYBACK_SRATE_176K  CM_CH1_SRATE_176K
 405 #define CM_PLAYBACK_SPDF        CM_SPDF_1
 406 #define CM_CAPTURE_SPDF         CM_SPDF_0
 407 #else
 408 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
 409 #define CM_PLAYBACK_SPDF        CM_SPDF_0
 410 #define CM_CAPTURE_SPDF         CM_SPDF_1
 411 #endif
 412
 413
 414 /*
 415  * driver data
 416  */
 417
 418 struct cmipci_pcm {
 419         struct snd_pcm_substream *substream;
 420         u8 running;             /* dac/adc running? */
 421         u8 fmt;                 /* format bits */
 422         u8 is_dac;
 423         u8 needs_silencing;
 424         unsigned int dma_size;  /* in frames */
 425         unsigned int shift;
 426         unsigned int ch;        /* channel (0/1) */
 427         unsigned int offset;    /* physical address of the buffer */
 428 };
 429
 430 /* mixer elements toggled/resumed during ac3 playback */
 431 struct cmipci_mixer_auto_switches {
 432         const char *name;       /* switch to toggle */
 433         int toggle_on;          /* value to change when ac3 mode */
 434 };
 435 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
 436         {"PCM Playback Switch", 0},
 437         {"IEC958 Output Switch", 1},
 438         {"IEC958 Mix Analog", 0},
 439         // {"IEC958 Out To DAC", 1}, // no longer used
 440         {"IEC958 Loop", 0},
 441 };
 442 #define CM_SAVED_MIXERS         ARRAY_SIZE(cm_saved_mixer)
 443
 444 struct cmipci {
 445         struct snd_card *card;
 446
 447         struct pci_dev *pci;
 448         unsigned int device;    /* device ID */
 449         int irq;
 450
 451         unsigned long iobase;
 452         unsigned int ctrl;      /* FUNCTRL0 current value */
 453
 454         struct snd_pcm *pcm;            /* DAC/ADC PCM */
 455         struct snd_pcm *pcm2;   /* 2nd DAC */
 456         struct snd_pcm *pcm_spdif;      /* SPDIF */
 457
 458         int chip_version;
 459         int max_channels;
 460         unsigned int can_ac3_sw: 1;
 461         unsigned int can_ac3_hw: 1;
 462         unsigned int can_multi_ch: 1;
 463         unsigned int can_96k: 1;        /* samplerate above 48k */
 464         unsigned int do_soft_ac3: 1;
 465
 466         unsigned int spdif_playback_avail: 1;   /* spdif ready? */
 467         unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
 468         int spdif_counter;      /* for software AC3 */
 469
 470         unsigned int dig_status;
 471         unsigned int dig_pcm_status;
 472
 473         struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
 474
 475         int opened[2];  /* open mode */
 476         struct mutex open_mutex;
 477
 478         unsigned int mixer_insensitive: 1;
 479         struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
 480         int mixer_res_status[CM_SAVED_MIXERS];
 481
 482         struct cmipci_pcm channel[2];   /* ch0 - DAC, ch1 - ADC or 2nd DAC */
 483
 484         /* external MIDI */
 485         struct snd_rawmidi *rmidi;
 486
 487 #ifdef SUPPORT_JOYSTICK
 488         struct gameport *gameport;
 489 #endif
 490
 491         spinlock_t reg_lock;
 492
 493 #ifdef CONFIG_PM_SLEEP
 494         unsigned int saved_regs[0x20];
 495         unsigned char saved_mixers[0x20];
 496 #endif
 497 };
 498
 499
 500 /* read/write operations for dword register */
 501 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
 502 {
 503         outl(data, cm->iobase + cmd);
 504 }
 505
 506 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
 507 {
 508         return inl(cm->iobase + cmd);
 509 }
 510
 511 /* read/write operations for word register */
 512 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
 513 {
 514         outw(data, cm->iobase + cmd);
 515 }
 516
 517 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
 518 {
 519         return inw(cm->iobase + cmd);
 520 }
 521
 522 /* read/write operations for byte register */
 523 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
 524 {
 525         outb(data, cm->iobase + cmd);
 526 }
 527
 528 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
 529 {
 530         return inb(cm->iobase + cmd);
 531 }
 532
 533 /* bit operations for dword register */
 534 static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
 535 {
 536         unsigned int val, oval;
 537         val = oval = inl(cm->iobase + cmd);
 538         val |= flag;
 539         if (val == oval)
 540                 return 0;
 541         outl(val, cm->iobase + cmd);
 542         return 1;
 543 }
 544
 545 static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
 546 {
 547         unsigned int val, oval;
 548         val = oval = inl(cm->iobase + cmd);
 549         val &= ~flag;
 550         if (val == oval)
 551                 return 0;
 552         outl(val, cm->iobase + cmd);
 553         return 1;
 554 }
 555
 556 /* bit operations for byte register */
 557 static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
 558 {
 559         unsigned char val, oval;
 560         val = oval = inb(cm->iobase + cmd);
 561         val |= flag;
 562         if (val == oval)
 563                 return 0;
 564         outb(val, cm->iobase + cmd);
 565         return 1;
 566 }
 567
 568 static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
 569 {
 570         unsigned char val, oval;
 571         val = oval = inb(cm->iobase + cmd);
 572         val &= ~flag;
 573         if (val == oval)
 574                 return 0;
 575         outb(val, cm->iobase + cmd);
 576         return 1;
 577 }
 578
 579
 580 /*
 581  * PCM interface
 582  */
 583
 584 /*
 585  * calculate frequency
 586  */
 587
 588 static const unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
 589
 590 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
 591 {
 592         unsigned int i;
 593
 594         for (i = 0; i < ARRAY_SIZE(rates); i++) {
 595                 if (rates[i] == rate)
 596                         return i;
 597         }
 598         snd_BUG();
 599         return 0;
 600 }
 601
 602 #ifdef USE_VAR48KRATE
 603 /*
 604  * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
 605  * does it this way .. maybe not.  Never get any information from C-Media about
 606  * that <werner@suse.de>.
 607  */
 608 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
 609 {
 610         unsigned int delta, tolerance;
 611         int xm, xn, xr;
 612
 613         for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
 614                 rate <<= 1;
 615         *n = -1;
 616         if (*r > 0xff)
 617                 goto out;
 618         tolerance = rate*CM_TOLERANCE_RATE;
 619
 620         for (xn = (1+2); xn < (0x1f+2); xn++) {
 621                 for (xm = (1+2); xm < (0xff+2); xm++) {
 622                         xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
 623
 624                         if (xr < rate)
 625                                 delta = rate - xr;
 626                         else
 627                                 delta = xr - rate;
 628
 629                         /*
 630                          * If we found one, remember this,
 631                          * and try to find a closer one
 632                          */
 633                         if (delta < tolerance) {
 634                                 tolerance = delta;
 635                                 *m = xm - 2;
 636                                 *n = xn - 2;
 637                         }
 638                 }
 639         }
 640 out:
 641         return (*n > -1);
 642 }
 643
 644 /*
 645  * Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff
 646  * are mapped onto the 8 ADC/DAC sampling frequency which can be chosen
 647  * at the register CM_REG_FUNCTRL1 (0x04).
 648  * Problem: other ways are also possible (any information about that?)
 649  */
 650 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
 651 {
 652         unsigned int reg = CM_REG_PLL + slot;
 653         /*
 654          * Guess that this programs at reg. 0x04 the pos 15:13/12:10
 655          * for DSFC/ASFC (000 up to 111).
 656          */
 657
 658         /* FIXME: Init (Do we've to set an other register first before programming?) */
 659
 660         /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
 661         snd_cmipci_write_b(cm, reg, rate>>8);
 662         snd_cmipci_write_b(cm, reg, rate&0xff);
 663
 664         /* FIXME: Setup (Do we've to set an other register first to enable this?) */
 665 }
 666 #endif /* USE_VAR48KRATE */
 667
 668 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
 669                                           struct snd_pcm_hw_params *hw_params)
 670 {
 671         struct cmipci *cm = snd_pcm_substream_chip(substream);
 672         if (params_channels(hw_params) > 2) {
 673                 mutex_lock(&cm->open_mutex);
 674                 if (cm->opened[CM_CH_PLAY]) {
 675                         mutex_unlock(&cm->open_mutex);
 676                         return -EBUSY;
 677                 }
 678                 /* reserve the channel A */
 679                 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
 680                 mutex_unlock(&cm->open_mutex);
 681         }
 682         return 0;
 683 }
 684
 685 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
 686 {
 687         int reset = CM_RST_CH0 << (cm->channel[ch].ch);
 688         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
 689         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
 690         udelay(10);
 691 }
 692
 693
 694 /*
 695  */
 696
 697 static const unsigned int hw_channels[] = {1, 2, 4, 6, 8};
 698 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
 699         .count = 3,
 700         .list = hw_channels,
 701         .mask = 0,
 702 };
 703 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
 704         .count = 4,
 705         .list = hw_channels,
 706         .mask = 0,
 707 };
 708 static const struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
 709         .count = 5,
 710         .list = hw_channels,
 711         .mask = 0,
 712 };
 713
 714 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
 715 {
 716         if (channels > 2) {
 717                 if (!cm->can_multi_ch || !rec->ch)
 718                         return -EINVAL;
 719                 if (rec->fmt != 0x03) /* stereo 16bit only */
 720                         return -EINVAL;
 721         }
 722
 723         if (cm->can_multi_ch) {
 724                 spin_lock_irq(&cm->reg_lock);
 725                 if (channels > 2) {
 726                         snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
 727                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
 728                 } else {
 729                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
 730                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
 731                 }
 732                 if (channels == 8)
 733                         snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
 734                 else
 735                         snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
 736                 if (channels == 6) {
 737                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 738                         snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 739                 } else {
 740                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
 741                         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
 742                 }
 743                 if (channels == 4)
 744                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 745                 else
 746                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
 747                 spin_unlock_irq(&cm->reg_lock);
 748         }
 749         return 0;
 750 }
 751
 752
 753 /*
 754  * prepare playback/capture channel
 755  * channel to be used must have been set in rec->ch.
 756  */
 757 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
 758                                  struct snd_pcm_substream *substream)
 759 {
 760         unsigned int reg, freq, freq_ext, val;
 761         unsigned int period_size;
 762         struct snd_pcm_runtime *runtime = substream->runtime;
 763
 764         rec->fmt = 0;
 765         rec->shift = 0;
 766         if (snd_pcm_format_width(runtime->format) >= 16) {
 767                 rec->fmt |= 0x02;
 768                 if (snd_pcm_format_width(runtime->format) > 16)
 769                         rec->shift++; /* 24/32bit */
 770         }
 771         if (runtime->channels > 1)
 772                 rec->fmt |= 0x01;
 773         if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
 774                 dev_dbg(cm->card->dev, "cannot set dac channels\n");
 775                 return -EINVAL;
 776         }
 777
 778         rec->offset = runtime->dma_addr;
 779         /* buffer and period sizes in frame */
 780         rec->dma_size = runtime->buffer_size << rec->shift;
 781         period_size = runtime->period_size << rec->shift;
 782         if (runtime->channels > 2) {
 783                 /* multi-channels */
 784                 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
 785                 period_size = (period_size * runtime->channels) / 2;
 786         }
 787
 788         spin_lock_irq(&cm->reg_lock);
 789
 790         /* set buffer address */
 791         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
 792         snd_cmipci_write(cm, reg, rec->offset);
 793         /* program sample counts */
 794         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
 795         snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
 796         snd_cmipci_write_w(cm, reg + 2, period_size - 1);
 797
 798         /* set adc/dac flag */
 799         val = rec->ch ? CM_CHADC1 : CM_CHADC0;
 800         if (rec->is_dac)
 801                 cm->ctrl &= ~val;
 802         else
 803                 cm->ctrl |= val;
 804         snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 805         /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
 806
 807         /* set sample rate */
 808         freq = 0;
 809         freq_ext = 0;
 810         if (runtime->rate > 48000)
 811                 switch (runtime->rate) {
 812                 case 88200:  freq_ext = CM_CH0_SRATE_88K; break;
 813                 case 96000:  freq_ext = CM_CH0_SRATE_96K; break;
 814                 case 128000: freq_ext = CM_CH0_SRATE_128K; break;
 815                 default:     snd_BUG(); break;
 816                 }
 817         else
 818                 freq = snd_cmipci_rate_freq(runtime->rate);
 819         val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
 820         if (rec->ch) {
 821                 val &= ~CM_DSFC_MASK;
 822                 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
 823         } else {
 824                 val &= ~CM_ASFC_MASK;
 825                 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
 826         }
 827         snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
 828         dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
 829
 830         /* set format */
 831         val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
 832         if (rec->ch) {
 833                 val &= ~CM_CH1FMT_MASK;
 834                 val |= rec->fmt << CM_CH1FMT_SHIFT;
 835         } else {
 836                 val &= ~CM_CH0FMT_MASK;
 837                 val |= rec->fmt << CM_CH0FMT_SHIFT;
 838         }
 839         if (cm->can_96k) {
 840                 val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
 841                 val |= freq_ext << (rec->ch * 2);
 842         }
 843         snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
 844         dev_dbg(cm->card->dev, "chformat = %08x\n", val);
 845
 846         if (!rec->is_dac && cm->chip_version) {
 847                 if (runtime->rate > 44100)
 848                         snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
 849                 else
 850                         snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
 851         }
 852
 853         rec->running = 0;
 854         spin_unlock_irq(&cm->reg_lock);
 855
 856         return 0;
 857 }
 858
 859 /*
 860  * PCM trigger/stop
 861  */
 862 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
 863                                   int cmd)
 864 {
 865         unsigned int inthld, chen, reset, pause;
 866         int result = 0;
 867
 868         inthld = CM_CH0_INT_EN << rec->ch;
 869         chen = CM_CHEN0 << rec->ch;
 870         reset = CM_RST_CH0 << rec->ch;
 871         pause = CM_PAUSE0 << rec->ch;
 872
 873         spin_lock(&cm->reg_lock);
 874         switch (cmd) {
 875         case SNDRV_PCM_TRIGGER_START:
 876                 rec->running = 1;
 877                 /* set interrupt */
 878                 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
 879                 cm->ctrl |= chen;
 880                 /* enable channel */
 881                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 882                 dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
 883                 break;
 884         case SNDRV_PCM_TRIGGER_STOP:
 885                 rec->running = 0;
 886                 /* disable interrupt */
 887                 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
 888                 /* reset */
 889                 cm->ctrl &= ~chen;
 890                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
 891                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
 892                 rec->needs_silencing = rec->is_dac;
 893                 break;
 894         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 895         case SNDRV_PCM_TRIGGER_SUSPEND:
 896                 cm->ctrl |= pause;
 897                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 898                 break;
 899         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 900         case SNDRV_PCM_TRIGGER_RESUME:
 901                 cm->ctrl &= ~pause;
 902                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
 903                 break;
 904         default:
 905                 result = -EINVAL;
 906                 break;
 907         }
 908         spin_unlock(&cm->reg_lock);
 909         return result;
 910 }
 911
 912 /*
 913  * return the current pointer
 914  */
 915 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
 916                                                 struct snd_pcm_substream *substream)
 917 {
 918         size_t ptr;
 919         unsigned int reg, rem, tries;
 920
 921         if (!rec->running)
 922                 return 0;
 923 #if 1 // this seems better..
 924         reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
 925         for (tries = 0; tries < 3; tries++) {
 926                 rem = snd_cmipci_read_w(cm, reg);
 927                 if (rem < rec->dma_size)
 928                         goto ok;
 929         }
 930         dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
 931         return SNDRV_PCM_POS_XRUN;
 932 ok:
 933         ptr = (rec->dma_size - (rem + 1)) >> rec->shift;
 934 #else
 935         reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
 936         ptr = snd_cmipci_read(cm, reg) - rec->offset;
 937         ptr = bytes_to_frames(substream->runtime, ptr);
 938 #endif
 939         if (substream->runtime->channels > 2)
 940                 ptr = (ptr * 2) / substream->runtime->channels;
 941         return ptr;
 942 }
 943
 944 /*
 945  * playback
 946  */
 947
 948 static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
 949                                        int cmd)
 950 {
 951         struct cmipci *cm = snd_pcm_substream_chip(substream);
 952         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
 953 }
 954
 955 static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
 956 {
 957         struct cmipci *cm = snd_pcm_substream_chip(substream);
 958         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
 959 }
 960
 961
 962
 963 /*
 964  * capture
 965  */
 966
 967 static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
 968                                      int cmd)
 969 {
 970         struct cmipci *cm = snd_pcm_substream_chip(substream);
 971         return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
 972 }
 973
 974 static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
 975 {
 976         struct cmipci *cm = snd_pcm_substream_chip(substream);
 977         return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
 978 }
 979
 980
 981 /*
 982  * hw preparation for spdif
 983  */
 984
 985 static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
 986                                          struct snd_ctl_elem_info *uinfo)
 987 {
 988         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
 989         uinfo->count = 1;
 990         return 0;
 991 }
 992
 993 static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
 994                                         struct snd_ctl_elem_value *ucontrol)
 995 {
 996         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
 997         int i;
 998
 999         spin_lock_irq(&chip->reg_lock);
1000         for (i = 0; i < 4; i++)
1001                 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
1002         spin_unlock_irq(&chip->reg_lock);
1003         return 0;
1004 }
1005
1006 static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1007                                          struct snd_ctl_elem_value *ucontrol)
1008 {
1009         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1010         int i, change;
1011         unsigned int val;
1012
1013         val = 0;
1014         spin_lock_irq(&chip->reg_lock);
1015         for (i = 0; i < 4; i++)
1016                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1017         change = val != chip->dig_status;
1018         chip->dig_status = val;
1019         spin_unlock_irq(&chip->reg_lock);
1020         return change;
1021 }
1022
1023 static const struct snd_kcontrol_new snd_cmipci_spdif_default =
1024 {
1025         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1026         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1027         .info =         snd_cmipci_spdif_default_info,
1028         .get =          snd_cmipci_spdif_default_get,
1029         .put =          snd_cmipci_spdif_default_put
1030 };
1031
1032 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1033                                       struct snd_ctl_elem_info *uinfo)
1034 {
1035         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1036         uinfo->count = 1;
1037         return 0;
1038 }
1039
1040 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1041                                      struct snd_ctl_elem_value *ucontrol)
1042 {
1043         ucontrol->value.iec958.status[0] = 0xff;
1044         ucontrol->value.iec958.status[1] = 0xff;
1045         ucontrol->value.iec958.status[2] = 0xff;
1046         ucontrol->value.iec958.status[3] = 0xff;
1047         return 0;
1048 }
1049
1050 static const struct snd_kcontrol_new snd_cmipci_spdif_mask =
1051 {
1052         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1053         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1054         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1055         .info =         snd_cmipci_spdif_mask_info,
1056         .get =          snd_cmipci_spdif_mask_get,
1057 };
1058
1059 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1060                                         struct snd_ctl_elem_info *uinfo)
1061 {
1062         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1063         uinfo->count = 1;
1064         return 0;
1065 }
1066
1067 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1068                                        struct snd_ctl_elem_value *ucontrol)
1069 {
1070         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1071         int i;
1072
1073         spin_lock_irq(&chip->reg_lock);
1074         for (i = 0; i < 4; i++)
1075                 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1076         spin_unlock_irq(&chip->reg_lock);
1077         return 0;
1078 }
1079
1080 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1081                                        struct snd_ctl_elem_value *ucontrol)
1082 {
1083         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1084         int i, change;
1085         unsigned int val;
1086
1087         val = 0;
1088         spin_lock_irq(&chip->reg_lock);
1089         for (i = 0; i < 4; i++)
1090                 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1091         change = val != chip->dig_pcm_status;
1092         chip->dig_pcm_status = val;
1093         spin_unlock_irq(&chip->reg_lock);
1094         return change;
1095 }
1096
1097 static const struct snd_kcontrol_new snd_cmipci_spdif_stream =
1098 {
1099         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1100         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1101         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1102         .info =         snd_cmipci_spdif_stream_info,
1103         .get =          snd_cmipci_spdif_stream_get,
1104         .put =          snd_cmipci_spdif_stream_put
1105 };
1106
1107 /*
1108  */
1109
1110 /* save mixer setting and mute for AC3 playback */
1111 static int save_mixer_state(struct cmipci *cm)
1112 {
1113         if (! cm->mixer_insensitive) {
1114                 struct snd_ctl_elem_value *val;
1115                 unsigned int i;
1116
1117                 val = kmalloc(sizeof(*val), GFP_KERNEL);
1118                 if (!val)
1119                         return -ENOMEM;
1120                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1121                         struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1122                         if (ctl) {
1123                                 int event;
1124                                 memset(val, 0, sizeof(*val));
1125                                 ctl->get(ctl, val);
1126                                 cm->mixer_res_status[i] = val->value.integer.value[0];
1127                                 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1128                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1129                                 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1130                                         ctl->put(ctl, val); /* toggle */
1131                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1132                                 }
1133                                 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1134                                 snd_ctl_notify(cm->card, event, &ctl->id);
1135                         }
1136                 }
1137                 kfree(val);
1138                 cm->mixer_insensitive = 1;
1139         }
1140         return 0;
1141 }
1142
1143
1144 /* restore the previously saved mixer status */
1145 static void restore_mixer_state(struct cmipci *cm)
1146 {
1147         if (cm->mixer_insensitive) {
1148                 struct snd_ctl_elem_value *val;
1149                 unsigned int i;
1150
1151                 val = kmalloc(sizeof(*val), GFP_KERNEL);
1152                 if (!val)
1153                         return;
1154                 cm->mixer_insensitive = 0; /* at first clear this;
1155                                               otherwise the changes will be ignored */
1156                 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1157                         struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1158                         if (ctl) {
1159                                 int event;
1160
1161                                 memset(val, 0, sizeof(*val));
1162                                 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1163                                 ctl->get(ctl, val);
1164                                 event = SNDRV_CTL_EVENT_MASK_INFO;
1165                                 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1166                                         val->value.integer.value[0] = cm->mixer_res_status[i];
1167                                         ctl->put(ctl, val);
1168                                         event |= SNDRV_CTL_EVENT_MASK_VALUE;
1169                                 }
1170                                 snd_ctl_notify(cm->card, event, &ctl->id);
1171                         }
1172                 }
1173                 kfree(val);
1174         }
1175 }
1176
1177 /* spinlock held! */
1178 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1179 {
1180         if (do_ac3) {
1181                 /* AC3EN for 037 */
1182                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1183                 /* AC3EN for 039 */
1184                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1185
1186                 if (cm->can_ac3_hw) {
1187                         /* SPD24SEL for 037, 0x02 */
1188                         /* SPD24SEL for 039, 0x20, but cannot be set */
1189                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1190                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1191                 } else { /* can_ac3_sw */
1192                         /* SPD32SEL for 037 & 039, 0x20 */
1193                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1194                         /* set 176K sample rate to fix 033 HW bug */
1195                         if (cm->chip_version == 33) {
1196                                 if (rate >= 48000) {
1197                                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1198                                 } else {
1199                                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1200                                 }
1201                         }
1202                 }
1203
1204         } else {
1205                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1206                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1207
1208                 if (cm->can_ac3_hw) {
1209                         /* chip model >= 37 */
1210                         if (snd_pcm_format_width(subs->runtime->format) > 16) {
1211                                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1212                                 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1213                         } else {
1214                                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1215                                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1216                         }
1217                 } else {
1218                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1219                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1220                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1221                 }
1222         }
1223 }
1224
1225 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1226 {
1227         int rate, err;
1228
1229         rate = subs->runtime->rate;
1230
1231         if (up && do_ac3)
1232                 if ((err = save_mixer_state(cm)) < 0)
1233                         return err;
1234
1235         spin_lock_irq(&cm->reg_lock);
1236         cm->spdif_playback_avail = up;
1237         if (up) {
1238                 /* they are controlled via "IEC958 Output Switch" */
1239                 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1240                 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1241                 if (cm->spdif_playback_enabled)
1242                         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1243                 setup_ac3(cm, subs, do_ac3, rate);
1244
1245                 if (rate == 48000 || rate == 96000)
1246                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1247                 else
1248                         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1249                 if (rate > 48000)
1250                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1251                 else
1252                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1253         } else {
1254                 /* they are controlled via "IEC958 Output Switch" */
1255                 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1256                 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1257                 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1258                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1259                 setup_ac3(cm, subs, 0, 0);
1260         }
1261         spin_unlock_irq(&cm->reg_lock);
1262         return 0;
1263 }
1264
1265
1266 /*
1267  * preparation
1268  */
1269
1270 /* playback - enable spdif only on the certain condition */
1271 static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1272 {
1273         struct cmipci *cm = snd_pcm_substream_chip(substream);
1274         int rate = substream->runtime->rate;
1275         int err, do_spdif, do_ac3 = 0;
1276
1277         do_spdif = (rate >= 44100 && rate <= 96000 &&
1278                     substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1279                     substream->runtime->channels == 2);
1280         if (do_spdif && cm->can_ac3_hw)
1281                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1282         if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1283                 return err;
1284         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1285 }
1286
1287 /* playback  (via device #2) - enable spdif always */
1288 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1289 {
1290         struct cmipci *cm = snd_pcm_substream_chip(substream);
1291         int err, do_ac3;
1292
1293         if (cm->can_ac3_hw)
1294                 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1295         else
1296                 do_ac3 = 1; /* doesn't matter */
1297         if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1298                 return err;
1299         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1300 }
1301
1302 /*
1303  * Apparently, the samples last played on channel A stay in some buffer, even
1304  * after the channel is reset, and get added to the data for the rear DACs when
1305  * playing a multichannel stream on channel B.  This is likely to generate
1306  * wraparounds and thus distortions.
1307  * To avoid this, we play at least one zero sample after the actual stream has
1308  * stopped.
1309  */
1310 static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1311 {
1312         struct snd_pcm_runtime *runtime = rec->substream->runtime;
1313         unsigned int reg, val;
1314
1315         if (rec->needs_silencing && runtime && runtime->dma_area) {
1316                 /* set up a small silence buffer */
1317                 memset(runtime->dma_area, 0, PAGE_SIZE);
1318                 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1319                 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1320                 snd_cmipci_write(cm, reg, val);
1321
1322                 /* configure for 16 bits, 2 channels, 8 kHz */
1323                 if (runtime->channels > 2)
1324                         set_dac_channels(cm, rec, 2);
1325                 spin_lock_irq(&cm->reg_lock);
1326                 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1327                 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1328                 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1329                 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1330                 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1331                 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1332                 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1333                 if (cm->can_96k)
1334                         val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1335                 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1336
1337                 /* start stream (we don't need interrupts) */
1338                 cm->ctrl |= CM_CHEN0 << rec->ch;
1339                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1340                 spin_unlock_irq(&cm->reg_lock);
1341
1342                 msleep(1);
1343
1344                 /* stop and reset stream */
1345                 spin_lock_irq(&cm->reg_lock);
1346                 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1347                 val = CM_RST_CH0 << rec->ch;
1348                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1349                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1350                 spin_unlock_irq(&cm->reg_lock);
1351
1352                 rec->needs_silencing = 0;
1353         }
1354 }
1355
1356 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1357 {
1358         struct cmipci *cm = snd_pcm_substream_chip(substream);
1359         setup_spdif_playback(cm, substream, 0, 0);
1360         restore_mixer_state(cm);
1361         snd_cmipci_silence_hack(cm, &cm->channel[0]);
1362         return 0;
1363 }
1364
1365 static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1366 {
1367         struct cmipci *cm = snd_pcm_substream_chip(substream);
1368         snd_cmipci_silence_hack(cm, &cm->channel[1]);
1369         return 0;
1370 }
1371
1372 /* capture */
1373 static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1374 {
1375         struct cmipci *cm = snd_pcm_substream_chip(substream);
1376         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1377 }
1378
1379 /* capture with spdif (via device #2) */
1380 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1381 {
1382         struct cmipci *cm = snd_pcm_substream_chip(substream);
1383
1384         spin_lock_irq(&cm->reg_lock);
1385         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1386         if (cm->can_96k) {
1387                 if (substream->runtime->rate > 48000)
1388                         snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1389                 else
1390                         snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1391         }
1392         if (snd_pcm_format_width(substream->runtime->format) > 16)
1393                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1394         else
1395                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1396
1397         spin_unlock_irq(&cm->reg_lock);
1398
1399         return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1400 }
1401
1402 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1403 {
1404         struct cmipci *cm = snd_pcm_substream_chip(subs);
1405
1406         spin_lock_irq(&cm->reg_lock);
1407         snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1408         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1409         spin_unlock_irq(&cm->reg_lock);
1410
1411         return 0;
1412 }
1413
1414
1415 /*
1416  * interrupt handler
1417  */
1418 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1419 {
1420         struct cmipci *cm = dev_id;
1421         unsigned int status, mask = 0;
1422
1423         /* fastpath out, to ease interrupt sharing */
1424         status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1425         if (!(status & CM_INTR))
1426                 return IRQ_NONE;
1427
1428         /* acknowledge interrupt */
1429         spin_lock(&cm->reg_lock);
1430         if (status & CM_CHINT0)
1431                 mask |= CM_CH0_INT_EN;
1432         if (status & CM_CHINT1)
1433                 mask |= CM_CH1_INT_EN;
1434         snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1435         snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1436         spin_unlock(&cm->reg_lock);
1437
1438         if (cm->rmidi && (status & CM_UARTINT))
1439                 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1440
1441         if (cm->pcm) {
1442                 if ((status & CM_CHINT0) && cm->channel[0].running)
1443                         snd_pcm_period_elapsed(cm->channel[0].substream);
1444                 if ((status & CM_CHINT1) && cm->channel[1].running)
1445                         snd_pcm_period_elapsed(cm->channel[1].substream);
1446         }
1447         return IRQ_HANDLED;
1448 }
1449
1450 /*
1451  * h/w infos
1452  */
1453
1454 /* playback on channel A */
1455 static const struct snd_pcm_hardware snd_cmipci_playback =
1456 {
1457         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1458                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1459                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1460         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1461         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1462         .rate_min =             5512,
1463         .rate_max =             48000,
1464         .channels_min =         1,
1465         .channels_max =         2,
1466         .buffer_bytes_max =     (128*1024),
1467         .period_bytes_min =     64,
1468         .period_bytes_max =     (128*1024),
1469         .periods_min =          2,
1470         .periods_max =          1024,
1471         .fifo_size =            0,
1472 };
1473
1474 /* capture on channel B */
1475 static const struct snd_pcm_hardware snd_cmipci_capture =
1476 {
1477         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1478                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1479                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1480         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1481         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1482         .rate_min =             5512,
1483         .rate_max =             48000,
1484         .channels_min =         1,
1485         .channels_max =         2,
1486         .buffer_bytes_max =     (128*1024),
1487         .period_bytes_min =     64,
1488         .period_bytes_max =     (128*1024),
1489         .periods_min =          2,
1490         .periods_max =          1024,
1491         .fifo_size =            0,
1492 };
1493
1494 /* playback on channel B - stereo 16bit only? */
1495 static const struct snd_pcm_hardware snd_cmipci_playback2 =
1496 {
1497         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1498                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1499                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1500         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1501         .rates =                SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1502         .rate_min =             5512,
1503         .rate_max =             48000,
1504         .channels_min =         2,
1505         .channels_max =         2,
1506         .buffer_bytes_max =     (128*1024),
1507         .period_bytes_min =     64,
1508         .period_bytes_max =     (128*1024),
1509         .periods_min =          2,
1510         .periods_max =          1024,
1511         .fifo_size =            0,
1512 };
1513
1514 /* spdif playback on channel A */
1515 static const struct snd_pcm_hardware snd_cmipci_playback_spdif =
1516 {
1517         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1518                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1519                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1520         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1521         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1522         .rate_min =             44100,
1523         .rate_max =             48000,
1524         .channels_min =         2,
1525         .channels_max =         2,
1526         .buffer_bytes_max =     (128*1024),
1527         .period_bytes_min =     64,
1528         .period_bytes_max =     (128*1024),
1529         .periods_min =          2,
1530         .periods_max =          1024,
1531         .fifo_size =            0,
1532 };
1533
1534 /* spdif playback on channel A (32bit, IEC958 subframes) */
1535 static const struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1536 {
1537         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1538                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1539                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1540         .formats =              SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1541         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1542         .rate_min =             44100,
1543         .rate_max =             48000,
1544         .channels_min =         2,
1545         .channels_max =         2,
1546         .buffer_bytes_max =     (128*1024),
1547         .period_bytes_min =     64,
1548         .period_bytes_max =     (128*1024),
1549         .periods_min =          2,
1550         .periods_max =          1024,
1551         .fifo_size =            0,
1552 };
1553
1554 /* spdif capture on channel B */
1555 static const struct snd_pcm_hardware snd_cmipci_capture_spdif =
1556 {
1557         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1558                                  SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1559                                  SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1560         .formats =              SNDRV_PCM_FMTBIT_S16_LE |
1561                                 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1562         .rates =                SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1563         .rate_min =             44100,
1564         .rate_max =             48000,
1565         .channels_min =         2,
1566         .channels_max =         2,
1567         .buffer_bytes_max =     (128*1024),
1568         .period_bytes_min =     64,
1569         .period_bytes_max =     (128*1024),
1570         .periods_min =          2,
1571         .periods_max =          1024,
1572         .fifo_size =            0,
1573 };
1574
1575 static const unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
1576                         32000, 44100, 48000, 88200, 96000, 128000 };
1577 static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
1578                 .count = ARRAY_SIZE(rate_constraints),
1579                 .list = rate_constraints,
1580                 .mask = 0,
1581 };
1582
1583 /*
1584  * check device open/close
1585  */
1586 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1587 {
1588         int ch = mode & CM_OPEN_CH_MASK;
1589
1590         /* FIXME: a file should wait until the device becomes free
1591          * when it's opened on blocking mode.  however, since the current
1592          * pcm framework doesn't pass file pointer before actually opened,
1593          * we can't know whether blocking mode or not in open callback..
1594          */
1595         mutex_lock(&cm->open_mutex);
1596         if (cm->opened[ch]) {
1597                 mutex_unlock(&cm->open_mutex);
1598                 return -EBUSY;
1599         }
1600         cm->opened[ch] = mode;
1601         cm->channel[ch].substream = subs;
1602         if (! (mode & CM_OPEN_DAC)) {
1603                 /* disable dual DAC mode */
1604                 cm->channel[ch].is_dac = 0;
1605                 spin_lock_irq(&cm->reg_lock);
1606                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1607                 spin_unlock_irq(&cm->reg_lock);
1608         }
1609         mutex_unlock(&cm->open_mutex);
1610         return 0;
1611 }
1612
1613 static void close_device_check(struct cmipci *cm, int mode)
1614 {
1615         int ch = mode & CM_OPEN_CH_MASK;
1616
1617         mutex_lock(&cm->open_mutex);
1618         if (cm->opened[ch] == mode) {
1619                 if (cm->channel[ch].substream) {
1620                         snd_cmipci_ch_reset(cm, ch);
1621                         cm->channel[ch].running = 0;
1622                         cm->channel[ch].substream = NULL;
1623                 }
1624                 cm->opened[ch] = 0;
1625                 if (! cm->channel[ch].is_dac) {
1626                         /* enable dual DAC mode again */
1627                         cm->channel[ch].is_dac = 1;
1628                         spin_lock_irq(&cm->reg_lock);
1629                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1630                         spin_unlock_irq(&cm->reg_lock);
1631                 }
1632         }
1633         mutex_unlock(&cm->open_mutex);
1634 }
1635
1636 /*
1637  */
1638
1639 static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1640 {
1641         struct cmipci *cm = snd_pcm_substream_chip(substream);
1642         struct snd_pcm_runtime *runtime = substream->runtime;
1643         int err;
1644
1645         if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1646                 return err;
1647         runtime->hw = snd_cmipci_playback;
1648         if (cm->chip_version == 68) {
1649                 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1650                                      SNDRV_PCM_RATE_96000;
1651                 runtime->hw.rate_max = 96000;
1652         } else if (cm->chip_version == 55) {
1653                 err = snd_pcm_hw_constraint_list(runtime, 0,
1654                         SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1655                 if (err < 0)
1656                         return err;
1657                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1658                 runtime->hw.rate_max = 128000;
1659         }
1660         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1661         cm->dig_pcm_status = cm->dig_status;
1662         return 0;
1663 }
1664
1665 static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1666 {
1667         struct cmipci *cm = snd_pcm_substream_chip(substream);
1668         struct snd_pcm_runtime *runtime = substream->runtime;
1669         int err;
1670
1671         if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1672                 return err;
1673         runtime->hw = snd_cmipci_capture;
1674         if (cm->chip_version == 68) {   // 8768 only supports 44k/48k recording
1675                 runtime->hw.rate_min = 41000;
1676                 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1677         } else if (cm->chip_version == 55) {
1678                 err = snd_pcm_hw_constraint_list(runtime, 0,
1679                         SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1680                 if (err < 0)
1681                         return err;
1682                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1683                 runtime->hw.rate_max = 128000;
1684         }
1685         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1686         return 0;
1687 }
1688
1689 static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1690 {
1691         struct cmipci *cm = snd_pcm_substream_chip(substream);
1692         struct snd_pcm_runtime *runtime = substream->runtime;
1693         int err;
1694
1695         if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1696                 return err;
1697         runtime->hw = snd_cmipci_playback2;
1698         mutex_lock(&cm->open_mutex);
1699         if (! cm->opened[CM_CH_PLAY]) {
1700                 if (cm->can_multi_ch) {
1701                         runtime->hw.channels_max = cm->max_channels;
1702                         if (cm->max_channels == 4)
1703                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1704                         else if (cm->max_channels == 6)
1705                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1706                         else if (cm->max_channels == 8)
1707                                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1708                 }
1709         }
1710         mutex_unlock(&cm->open_mutex);
1711         if (cm->chip_version == 68) {
1712                 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1713                                      SNDRV_PCM_RATE_96000;
1714                 runtime->hw.rate_max = 96000;
1715         } else if (cm->chip_version == 55) {
1716                 err = snd_pcm_hw_constraint_list(runtime, 0,
1717                         SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
1718                 if (err < 0)
1719                         return err;
1720                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
1721                 runtime->hw.rate_max = 128000;
1722         }
1723         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1724         return 0;
1725 }
1726
1727 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1728 {
1729         struct cmipci *cm = snd_pcm_substream_chip(substream);
1730         struct snd_pcm_runtime *runtime = substream->runtime;
1731         int err;
1732
1733         if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1734                 return err;
1735         if (cm->can_ac3_hw) {
1736                 runtime->hw = snd_cmipci_playback_spdif;
1737                 if (cm->chip_version >= 37) {
1738                         runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1739                         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1740                 }
1741                 if (cm->can_96k) {
1742                         runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1743                                              SNDRV_PCM_RATE_96000;
1744                         runtime->hw.rate_max = 96000;
1745                 }
1746         } else {
1747                 runtime->hw = snd_cmipci_playback_iec958_subframe;
1748         }
1749         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1750         cm->dig_pcm_status = cm->dig_status;
1751         return 0;
1752 }
1753
1754 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1755 {
1756         struct cmipci *cm = snd_pcm_substream_chip(substream);
1757         struct snd_pcm_runtime *runtime = substream->runtime;
1758         int err;
1759
1760         if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1761                 return err;
1762         runtime->hw = snd_cmipci_capture_spdif;
1763         if (cm->can_96k && !(cm->chip_version == 68)) {
1764                 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1765                                      SNDRV_PCM_RATE_96000;
1766                 runtime->hw.rate_max = 96000;
1767         }
1768         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1769         return 0;
1770 }
1771
1772
1773 /*
1774  */
1775
1776 static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1777 {
1778         struct cmipci *cm = snd_pcm_substream_chip(substream);
1779         close_device_check(cm, CM_OPEN_PLAYBACK);
1780         return 0;
1781 }
1782
1783 static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1784 {
1785         struct cmipci *cm = snd_pcm_substream_chip(substream);
1786         close_device_check(cm, CM_OPEN_CAPTURE);
1787         return 0;
1788 }
1789
1790 static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1791 {
1792         struct cmipci *cm = snd_pcm_substream_chip(substream);
1793         close_device_check(cm, CM_OPEN_PLAYBACK2);
1794         close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1795         return 0;
1796 }
1797
1798 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1799 {
1800         struct cmipci *cm = snd_pcm_substream_chip(substream);
1801         close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1802         return 0;
1803 }
1804
1805 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1806 {
1807         struct cmipci *cm = snd_pcm_substream_chip(substream);
1808         close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1809         return 0;
1810 }
1811
1812
1813 /*
1814  */
1815
1816 static const struct snd_pcm_ops snd_cmipci_playback_ops = {
1817         .open =         snd_cmipci_playback_open,
1818         .close =        snd_cmipci_playback_close,
1819         .hw_free =      snd_cmipci_playback_hw_free,
1820         .prepare =      snd_cmipci_playback_prepare,
1821         .trigger =      snd_cmipci_playback_trigger,
1822         .pointer =      snd_cmipci_playback_pointer,
1823 };
1824
1825 static const struct snd_pcm_ops snd_cmipci_capture_ops = {
1826         .open =         snd_cmipci_capture_open,
1827         .close =        snd_cmipci_capture_close,
1828         .prepare =      snd_cmipci_capture_prepare,
1829         .trigger =      snd_cmipci_capture_trigger,
1830         .pointer =      snd_cmipci_capture_pointer,
1831 };
1832
1833 static const struct snd_pcm_ops snd_cmipci_playback2_ops = {
1834         .open =         snd_cmipci_playback2_open,
1835         .close =        snd_cmipci_playback2_close,
1836         .hw_params =    snd_cmipci_playback2_hw_params,
1837         .hw_free =      snd_cmipci_playback2_hw_free,
1838         .prepare =      snd_cmipci_capture_prepare,     /* channel B */
1839         .trigger =      snd_cmipci_capture_trigger,     /* channel B */
1840         .pointer =      snd_cmipci_capture_pointer,     /* channel B */
1841 };
1842
1843 static const struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1844         .open =         snd_cmipci_playback_spdif_open,
1845         .close =        snd_cmipci_playback_spdif_close,
1846         .hw_free =      snd_cmipci_playback_hw_free,
1847         .prepare =      snd_cmipci_playback_spdif_prepare,      /* set up rate */
1848         .trigger =      snd_cmipci_playback_trigger,
1849         .pointer =      snd_cmipci_playback_pointer,
1850 };
1851
1852 static const struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1853         .open =         snd_cmipci_capture_spdif_open,
1854         .close =        snd_cmipci_capture_spdif_close,
1855         .hw_free =      snd_cmipci_capture_spdif_hw_free,
1856         .prepare =      snd_cmipci_capture_spdif_prepare,
1857         .trigger =      snd_cmipci_capture_trigger,
1858         .pointer =      snd_cmipci_capture_pointer,
1859 };
1860
1861
1862 /*
1863  */
1864
1865 static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
1866 {
1867         struct snd_pcm *pcm;
1868         int err;
1869
1870         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1871         if (err < 0)
1872                 return err;
1873
1874         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1875         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1876
1877         pcm->private_data = cm;
1878         pcm->info_flags = 0;
1879         strcpy(pcm->name, "C-Media PCI DAC/ADC");
1880         cm->pcm = pcm;
1881
1882         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1883                                        &cm->pci->dev, 64*1024, 128*1024);
1884
1885         return 0;
1886 }
1887
1888 static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1889 {
1890         struct snd_pcm *pcm;
1891         int err;
1892
1893         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1894         if (err < 0)
1895                 return err;
1896
1897         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1898
1899         pcm->private_data = cm;
1900         pcm->info_flags = 0;
1901         strcpy(pcm->name, "C-Media PCI 2nd DAC");
1902         cm->pcm2 = pcm;
1903
1904         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1905                                        &cm->pci->dev, 64*1024, 128*1024);
1906
1907         return 0;
1908 }
1909
1910 static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1911 {
1912         struct snd_pcm *pcm;
1913         int err;
1914
1915         err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1916         if (err < 0)
1917                 return err;
1918
1919         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1920         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1921
1922         pcm->private_data = cm;
1923         pcm->info_flags = 0;
1924         strcpy(pcm->name, "C-Media PCI IEC958");
1925         cm->pcm_spdif = pcm;
1926
1927         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1928                                        &cm->pci->dev, 64*1024, 128*1024);
1929
1930         err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1931                                      snd_pcm_alt_chmaps, cm->max_channels, 0,
1932                                      NULL);
1933         if (err < 0)
1934                 return err;
1935
1936         return 0;
1937 }
1938
1939 /*
1940  * mixer interface:
1941  * - CM8338/8738 has a compatible mixer interface with SB16, but
1942  *   lack of some elements like tone control, i/o gain and AGC.
1943  * - Access to native registers:
1944  *   - A 3D switch
1945  *   - Output mute switches
1946  */
1947
1948 static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1949 {
1950         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1951         outb(data, s->iobase + CM_REG_SB16_DATA);
1952 }
1953
1954 static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1955 {
1956         unsigned char v;
1957
1958         outb(idx, s->iobase + CM_REG_SB16_ADDR);
1959         v = inb(s->iobase + CM_REG_SB16_DATA);
1960         return v;
1961 }
1962
1963 /*
1964  * general mixer element
1965  */
1966 struct cmipci_sb_reg {
1967         unsigned int left_reg, right_reg;
1968         unsigned int left_shift, right_shift;
1969         unsigned int mask;
1970         unsigned int invert: 1;
1971         unsigned int stereo: 1;
1972 };
1973
1974 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1975  ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1976
1977 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1978 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1979   .info = snd_cmipci_info_volume, \
1980   .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1981   .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1982 }
1983
1984 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1985 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1986 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1987 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1988
1989 static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
1990 {
1991         r->left_reg = val & 0xff;
1992         r->right_reg = (val >> 8) & 0xff;
1993         r->left_shift = (val >> 16) & 0x07;
1994         r->right_shift = (val >> 19) & 0x07;
1995         r->invert = (val >> 22) & 1;
1996         r->stereo = (val >> 23) & 1;
1997         r->mask = (val >> 24) & 0xff;
1998 }
1999
2000 static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
2001                                   struct snd_ctl_elem_info *uinfo)
2002 {
2003         struct cmipci_sb_reg reg;
2004
2005         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2006         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2007         uinfo->count = reg.stereo + 1;
2008         uinfo->value.integer.min = 0;
2009         uinfo->value.integer.max = reg.mask;
2010         return 0;
2011 }
2012
2013 static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
2014                                  struct snd_ctl_elem_value *ucontrol)
2015 {
2016         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2017         struct cmipci_sb_reg reg;
2018         int val;
2019
2020         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2021         spin_lock_irq(&cm->reg_lock);
2022         val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
2023         if (reg.invert)
2024                 val = reg.mask - val;
2025         ucontrol->value.integer.value[0] = val;
2026         if (reg.stereo) {
2027                 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
2028                 if (reg.invert)
2029                         val = reg.mask - val;
2030                 ucontrol->value.integer.value[1] = val;
2031         }
2032         spin_unlock_irq(&cm->reg_lock);
2033         return 0;
2034 }
2035
2036 static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2037                                  struct snd_ctl_elem_value *ucontrol)
2038 {
2039         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2040         struct cmipci_sb_reg reg;
2041         int change;
2042         int left, right, oleft, oright;
2043
2044         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2045         left = ucontrol->value.integer.value[0] & reg.mask;
2046         if (reg.invert)
2047                 left = reg.mask - left;
2048         left <<= reg.left_shift;
2049         if (reg.stereo) {
2050                 right = ucontrol->value.integer.value[1] & reg.mask;
2051                 if (reg.invert)
2052                         right = reg.mask - right;
2053                 right <<= reg.right_shift;
2054         } else
2055                 right = 0;
2056         spin_lock_irq(&cm->reg_lock);
2057         oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2058         left |= oleft & ~(reg.mask << reg.left_shift);
2059         change = left != oleft;
2060         if (reg.stereo) {
2061                 if (reg.left_reg != reg.right_reg) {
2062                         snd_cmipci_mixer_write(cm, reg.left_reg, left);
2063                         oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2064                 } else
2065                         oright = left;
2066                 right |= oright & ~(reg.mask << reg.right_shift);
2067                 change |= right != oright;
2068                 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2069         } else
2070                 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2071         spin_unlock_irq(&cm->reg_lock);
2072         return change;
2073 }
2074
2075 /*
2076  * input route (left,right) -> (left,right)
2077  */
2078 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2079 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2080   .info = snd_cmipci_info_input_sw, \
2081   .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2082   .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2083 }
2084
2085 static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2086                                     struct snd_ctl_elem_info *uinfo)
2087 {
2088         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2089         uinfo->count = 4;
2090         uinfo->value.integer.min = 0;
2091         uinfo->value.integer.max = 1;
2092         return 0;
2093 }
2094
2095 static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2096                                    struct snd_ctl_elem_value *ucontrol)
2097 {
2098         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2099         struct cmipci_sb_reg reg;
2100         int val1, val2;
2101
2102         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2103         spin_lock_irq(&cm->reg_lock);
2104         val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2105         val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2106         spin_unlock_irq(&cm->reg_lock);
2107         ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2108         ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2109         ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2110         ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2111         return 0;
2112 }
2113
2114 static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2115                                    struct snd_ctl_elem_value *ucontrol)
2116 {
2117         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2118         struct cmipci_sb_reg reg;
2119         int change;
2120         int val1, val2, oval1, oval2;
2121
2122         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2123         spin_lock_irq(&cm->reg_lock);
2124         oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2125         oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2126         val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2127         val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2128         val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2129         val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2130         val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2131         val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2132         change = val1 != oval1 || val2 != oval2;
2133         snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2134         snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2135         spin_unlock_irq(&cm->reg_lock);
2136         return change;
2137 }
2138
2139 /*
2140  * native mixer switches/volumes
2141  */
2142
2143 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2144 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2145   .info = snd_cmipci_info_native_mixer, \
2146   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2147   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2148 }
2149
2150 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2151 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2152   .info = snd_cmipci_info_native_mixer, \
2153   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2154   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2155 }
2156
2157 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2158 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2159   .info = snd_cmipci_info_native_mixer, \
2160   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2161   .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2162 }
2163
2164 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2165 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2166   .info = snd_cmipci_info_native_mixer, \
2167   .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2168   .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2169 }
2170
2171 static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2172                                         struct snd_ctl_elem_info *uinfo)
2173 {
2174         struct cmipci_sb_reg reg;
2175
2176         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2177         uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2178         uinfo->count = reg.stereo + 1;
2179         uinfo->value.integer.min = 0;
2180         uinfo->value.integer.max = reg.mask;
2181         return 0;
2182
2183 }
2184
2185 static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2186                                        struct snd_ctl_elem_value *ucontrol)
2187 {
2188         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2189         struct cmipci_sb_reg reg;
2190         unsigned char oreg, val;
2191
2192         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2193         spin_lock_irq(&cm->reg_lock);
2194         oreg = inb(cm->iobase + reg.left_reg);
2195         val = (oreg >> reg.left_shift) & reg.mask;
2196         if (reg.invert)
2197                 val = reg.mask - val;
2198         ucontrol->value.integer.value[0] = val;
2199         if (reg.stereo) {
2200                 val = (oreg >> reg.right_shift) & reg.mask;
2201                 if (reg.invert)
2202                         val = reg.mask - val;
2203                 ucontrol->value.integer.value[1] = val;
2204         }
2205         spin_unlock_irq(&cm->reg_lock);
2206         return 0;
2207 }
2208
2209 static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2210                                        struct snd_ctl_elem_value *ucontrol)
2211 {
2212         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2213         struct cmipci_sb_reg reg;
2214         unsigned char oreg, nreg, val;
2215
2216         cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2217         spin_lock_irq(&cm->reg_lock);
2218         oreg = inb(cm->iobase + reg.left_reg);
2219         val = ucontrol->value.integer.value[0] & reg.mask;
2220         if (reg.invert)
2221                 val = reg.mask - val;
2222         nreg = oreg & ~(reg.mask << reg.left_shift);
2223         nreg |= (val << reg.left_shift);
2224         if (reg.stereo) {
2225                 val = ucontrol->value.integer.value[1] & reg.mask;
2226                 if (reg.invert)
2227                         val = reg.mask - val;
2228                 nreg &= ~(reg.mask << reg.right_shift);
2229                 nreg |= (val << reg.right_shift);
2230         }
2231         outb(nreg, cm->iobase + reg.left_reg);
2232         spin_unlock_irq(&cm->reg_lock);
2233         return (nreg != oreg);
2234 }
2235
2236 /*
2237  * special case - check mixer sensitivity
2238  */
2239 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2240                                                  struct snd_ctl_elem_value *ucontrol)
2241 {
2242         //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2243         return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2244 }
2245
2246 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2247                                                  struct snd_ctl_elem_value *ucontrol)
2248 {
2249         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2250         if (cm->mixer_insensitive) {
2251                 /* ignored */
2252                 return 0;
2253         }
2254         return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2255 }
2256
2257
2258 static const struct snd_kcontrol_new snd_cmipci_mixers[] = {
2259         CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2260         CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2261         CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2262         //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2263         { /* switch with sensitivity */
2264                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2265                 .name = "PCM Playback Switch",
2266                 .info = snd_cmipci_info_native_mixer,
2267                 .get = snd_cmipci_get_native_mixer_sensitive,
2268                 .put = snd_cmipci_put_native_mixer_sensitive,
2269                 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2270         },
2271         CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2272         CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2273         CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2274         CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2275         CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2276         CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2277         CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2278         CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2279         CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2280         CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2281         CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2282         CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2283         CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2284         CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2285         CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2286         CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2287         CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2288         CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2289         CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2290         CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2291         CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2292         CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2293         CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2294 };
2295
2296 /*
2297  * other switches
2298  */
2299
2300 struct cmipci_switch_args {
2301         int reg;                /* register index */
2302         unsigned int mask;      /* mask bits */
2303         unsigned int mask_on;   /* mask bits to turn on */
2304         unsigned int is_byte: 1;                /* byte access? */
2305         unsigned int ac3_sensitive: 1;  /* access forbidden during
2306                                          * non-audio operation?
2307                                          */
2308 };
2309
2310 #define snd_cmipci_uswitch_info         snd_ctl_boolean_mono_info
2311
2312 static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2313                                    struct snd_ctl_elem_value *ucontrol,
2314                                    struct cmipci_switch_args *args)
2315 {
2316         unsigned int val;
2317         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2318
2319         spin_lock_irq(&cm->reg_lock);
2320         if (args->ac3_sensitive && cm->mixer_insensitive) {
2321                 ucontrol->value.integer.value[0] = 0;
2322                 spin_unlock_irq(&cm->reg_lock);
2323                 return 0;
2324         }
2325         if (args->is_byte)
2326                 val = inb(cm->iobase + args->reg);
2327         else
2328                 val = snd_cmipci_read(cm, args->reg);
2329         ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2330         spin_unlock_irq(&cm->reg_lock);
2331         return 0;
2332 }
2333
2334 static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2335                                   struct snd_ctl_elem_value *ucontrol)
2336 {
2337         struct cmipci_switch_args *args;
2338         args = (struct cmipci_switch_args *)kcontrol->private_value;
2339         if (snd_BUG_ON(!args))
2340                 return -EINVAL;
2341         return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2342 }
2343
2344 static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2345                                    struct snd_ctl_elem_value *ucontrol,
2346                                    struct cmipci_switch_args *args)
2347 {
2348         unsigned int val;
2349         int change;
2350         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2351
2352         spin_lock_irq(&cm->reg_lock);
2353         if (args->ac3_sensitive && cm->mixer_insensitive) {
2354                 /* ignored */
2355                 spin_unlock_irq(&cm->reg_lock);
2356                 return 0;
2357         }
2358         if (args->is_byte)
2359                 val = inb(cm->iobase + args->reg);
2360         else
2361                 val = snd_cmipci_read(cm, args->reg);
2362         change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2363                         args->mask_on : (args->mask & ~args->mask_on));
2364         if (change) {
2365                 val &= ~args->mask;
2366                 if (ucontrol->value.integer.value[0])
2367                         val |= args->mask_on;
2368                 else
2369                         val |= (args->mask & ~args->mask_on);
2370                 if (args->is_byte)
2371                         outb((unsigned char)val, cm->iobase + args->reg);
2372                 else
2373                         snd_cmipci_write(cm, args->reg, val);
2374         }
2375         spin_unlock_irq(&cm->reg_lock);
2376         return change;
2377 }
2378
2379 static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2380                                   struct snd_ctl_elem_value *ucontrol)
2381 {
2382         struct cmipci_switch_args *args;
2383         args = (struct cmipci_switch_args *)kcontrol->private_value;
2384         if (snd_BUG_ON(!args))
2385                 return -EINVAL;
2386         return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2387 }
2388
2389 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2390 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2391   .reg = xreg, \
2392   .mask = xmask, \
2393   .mask_on = xmask_on, \
2394   .is_byte = xis_byte, \
2395   .ac3_sensitive = xac3, \
2396 }
2397
2398 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2399         DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2400
2401 #if 0 /* these will be controlled in pcm device */
2402 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2403 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2404 #endif
2405 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2406 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2407 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2408 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2409 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2410 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2411 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2412 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2413 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2414 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2415 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2416 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2417 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2418 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2419 #if CM_CH_PLAY == 1
2420 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2421 #else
2422 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2423 #endif
2424 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2425 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2426 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2427 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2428 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2429
2430 #define DEFINE_SWITCH(sname, stype, sarg) \
2431 { .name = sname, \
2432   .iface = stype, \
2433   .info = snd_cmipci_uswitch_info, \
2434   .get = snd_cmipci_uswitch_get, \
2435   .put = snd_cmipci_uswitch_put, \
2436   .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2437 }
2438
2439 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2440 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2441
2442
2443 /*
2444  * callbacks for spdif output switch
2445  * needs toggle two registers..
2446  */
2447 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2448                                         struct snd_ctl_elem_value *ucontrol)
2449 {
2450         int changed;
2451         changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2452         changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2453         return changed;
2454 }
2455
2456 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2457                                         struct snd_ctl_elem_value *ucontrol)
2458 {
2459         struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2460         int changed;
2461         changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2462         changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2463         if (changed) {
2464                 if (ucontrol->value.integer.value[0]) {
2465                         if (chip->spdif_playback_avail)
2466                                 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2467                 } else {
2468                         if (chip->spdif_playback_avail)
2469                                 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2470                 }
2471         }
2472         chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2473         return changed;
2474 }
2475
2476
2477 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2478                                         struct snd_ctl_elem_info *uinfo)
2479 {
2480         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2481         static const char *const texts[3] = {
2482                 "Line-In", "Rear Output", "Bass Output"
2483         };
2484
2485         return snd_ctl_enum_info(uinfo, 1,
2486                                  cm->chip_version >= 39 ? 3 : 2, texts);
2487 }
2488
2489 static inline unsigned int get_line_in_mode(struct cmipci *cm)
2490 {
2491         unsigned int val;
2492         if (cm->chip_version >= 39) {
2493                 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2494                 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2495                         return 2;
2496         }
2497         val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2498         if (val & CM_REAR2LIN)
2499                 return 1;
2500         return 0;
2501 }
2502
2503 static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2504                                        struct snd_ctl_elem_value *ucontrol)
2505 {
2506         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2507
2508         spin_lock_irq(&cm->reg_lock);
2509         ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2510         spin_unlock_irq(&cm->reg_lock);
2511         return 0;
2512 }
2513
2514 static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2515                                        struct snd_ctl_elem_value *ucontrol)
2516 {
2517         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2518         int change;
2519
2520         spin_lock_irq(&cm->reg_lock);
2521         if (ucontrol->value.enumerated.item[0] == 2)
2522                 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2523         else
2524                 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2525         if (ucontrol->value.enumerated.item[0] == 1)
2526                 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2527         else
2528                 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2529         spin_unlock_irq(&cm->reg_lock);
2530         return change;
2531 }
2532
2533 static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2534                                        struct snd_ctl_elem_info *uinfo)
2535 {
2536         static const char *const texts[2] = { "Mic-In", "Center/LFE Output" };
2537
2538         return snd_ctl_enum_info(uinfo, 1, 2, texts);
2539 }
2540
2541 static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2542                                       struct snd_ctl_elem_value *ucontrol)
2543 {
2544         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2545         /* same bit as spdi_phase */
2546         spin_lock_irq(&cm->reg_lock);
2547         ucontrol->value.enumerated.item[0] =
2548                 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2549         spin_unlock_irq(&cm->reg_lock);
2550         return 0;
2551 }
2552
2553 static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2554                                       struct snd_ctl_elem_value *ucontrol)
2555 {
2556         struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2557         int change;
2558
2559         spin_lock_irq(&cm->reg_lock);
2560         if (ucontrol->value.enumerated.item[0])
2561                 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2562         else
2563                 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2564         spin_unlock_irq(&cm->reg_lock);
2565         return change;
2566 }
2567
2568 /* both for CM8338/8738 */
2569 static const struct snd_kcontrol_new snd_cmipci_mixer_switches[] = {
2570         DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2571         {
2572                 .name = "Line-In Mode",
2573                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2574                 .info = snd_cmipci_line_in_mode_info,
2575                 .get = snd_cmipci_line_in_mode_get,
2576                 .put = snd_cmipci_line_in_mode_put,
2577         },
2578 };
2579
2580 /* for non-multichannel chips */
2581 static const struct snd_kcontrol_new snd_cmipci_nomulti_switch =
2582 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2583
2584 /* only for CM8738 */
2585 static const struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = {
2586 #if 0 /* controlled in pcm device */
2587         DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2588         DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2589         DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2590 #endif
2591         // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2592         { .name = "IEC958 Output Switch",
2593           .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2594           .info = snd_cmipci_uswitch_info,
2595           .get = snd_cmipci_spdout_enable_get,
2596           .put = snd_cmipci_spdout_enable_put,
2597         },
2598         DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2599         DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2600         DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2601 //      DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2602         DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2603         DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2604 };
2605
2606 /* only for model 033/037 */
2607 static const struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = {
2608         DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2609         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2610         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2611 };
2612
2613 /* only for model 039 or later */
2614 static const struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = {
2615         DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2616         DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2617         {
2618                 .name = "Mic-In Mode",
2619                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2620                 .info = snd_cmipci_mic_in_mode_info,
2621                 .get = snd_cmipci_mic_in_mode_get,
2622                 .put = snd_cmipci_mic_in_mode_put,
2623         }
2624 };
2625
2626 /* card control switches */
2627 static const struct snd_kcontrol_new snd_cmipci_modem_switch =
2628 DEFINE_CARD_SWITCH("Modem", modem);
2629
2630
2631 static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2632 {
2633         struct snd_card *card;
2634         const struct snd_kcontrol_new *sw;
2635         struct snd_kcontrol *kctl;
2636         unsigned int idx;
2637         int err;
2638
2639         if (snd_BUG_ON(!cm || !cm->card))
2640                 return -EINVAL;
2641
2642         card = cm->card;
2643
2644         strcpy(card->mixername, "CMedia PCI");
2645
2646         spin_lock_irq(&cm->reg_lock);
2647         snd_cmipci_mixer_write(cm, 0x00, 0x00);         /* mixer reset */
2648         spin_unlock_irq(&cm->reg_lock);
2649
2650         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2651                 if (cm->chip_version == 68) {   // 8768 has no PCM volume
2652                         if (!strcmp(snd_cmipci_mixers[idx].name,
2653                                 "PCM Playback Volume"))
2654                                 continue;
2655                 }
2656                 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2657                         return err;
2658         }
2659
2660         /* mixer switches */
2661         sw = snd_cmipci_mixer_switches;
2662         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2663                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2664                 if (err < 0)
2665                         return err;
2666         }
2667         if (! cm->can_multi_ch) {
2668                 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2669                 if (err < 0)
2670                         return err;
2671         }
2672         if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2673             cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2674                 sw = snd_cmipci_8738_mixer_switches;
2675                 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2676                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2677                         if (err < 0)
2678                                 return err;
2679                 }
2680                 if (cm->can_ac3_hw) {
2681                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2682                                 return err;
2683                         kctl->id.device = pcm_spdif_device;
2684                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2685                                 return err;
2686                         kctl->id.device = pcm_spdif_device;
2687                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2688                                 return err;
2689                         kctl->id.device = pcm_spdif_device;
2690                 }
2691                 if (cm->chip_version <= 37) {
2692                         sw = snd_cmipci_old_mixer_switches;
2693                         for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2694                                 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2695                                 if (err < 0)
2696                                         return err;
2697                         }
2698                 }
2699         }
2700         if (cm->chip_version >= 39) {
2701                 sw = snd_cmipci_extra_mixer_switches;
2702                 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2703                         err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2704                         if (err < 0)
2705                                 return err;
2706                 }
2707         }
2708
2709         /* card switches */
2710         /*
2711          * newer chips don't have the register bits to force modem link
2712          * detection; the bit that was FLINKON now mutes CH1
2713          */
2714         if (cm->chip_version < 39) {
2715                 err = snd_ctl_add(cm->card,
2716                                   snd_ctl_new1(&snd_cmipci_modem_switch, cm));
2717                 if (err < 0)
2718                         return err;
2719         }
2720
2721         for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2722                 struct snd_ctl_elem_id elem_id;
2723                 struct snd_kcontrol *ctl;
2724                 memset(&elem_id, 0, sizeof(elem_id));
2725                 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2726                 strcpy(elem_id.name, cm_saved_mixer[idx].name);
2727                 ctl = snd_ctl_find_id(cm->card, &elem_id);
2728                 if (ctl)
2729                         cm->mixer_res_ctl[idx] = ctl;
2730         }
2731
2732         return 0;
2733 }
2734
2735
2736 /*
2737  * proc interface
2738  */
2739
2740 static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2741                                  struct snd_info_buffer *buffer)
2742 {
2743         struct cmipci *cm = entry->private_data;
2744         int i, v;
2745
2746         snd_iprintf(buffer, "%s\n", cm->card->longname);
2747         for (i = 0; i < 0x94; i++) {
2748                 if (i == 0x28)
2749                         i = 0x90;
2750                 v = inb(cm->iobase + i);
2751                 if (i % 4 == 0)
2752                         snd_iprintf(buffer, "\n%02x:", i);
2753                 snd_iprintf(buffer, " %02x", v);
2754         }
2755         snd_iprintf(buffer, "\n");
2756 }
2757
2758 static void snd_cmipci_proc_init(struct cmipci *cm)
2759 {
2760         snd_card_ro_proc_new(cm->card, "cmipci", cm, snd_cmipci_proc_read);
2761 }
2762
2763 static const struct pci_device_id snd_cmipci_ids[] = {
2764         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0},
2765         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0},
2766         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2767         {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0},
2768         {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2769         {0,},
2770 };
2771
2772
2773 /*
2774  * check chip version and capabilities
2775  * driver name is modified according to the chip model
2776  */
2777 static void query_chip(struct cmipci *cm)
2778 {
2779         unsigned int detect;
2780
2781         /* check reg 0Ch, bit 24-31 */
2782         detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2783         if (! detect) {
2784                 /* check reg 08h, bit 24-28 */
2785                 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2786                 switch (detect) {
2787                 case 0:
2788                         cm->chip_version = 33;
2789                         if (cm->do_soft_ac3)
2790                                 cm->can_ac3_sw = 1;
2791                         else
2792                                 cm->can_ac3_hw = 1;
2793                         break;
2794                 case CM_CHIP_037:
2795                         cm->chip_version = 37;
2796                         cm->can_ac3_hw = 1;
2797                         break;
2798                 default:
2799                         cm->chip_version = 39;
2800                         cm->can_ac3_hw = 1;
2801                         break;
2802                 }
2803                 cm->max_channels = 2;
2804         } else {
2805                 if (detect & CM_CHIP_039) {
2806                         cm->chip_version = 39;
2807                         if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2808                                 cm->max_channels = 6;
2809                         else
2810                                 cm->max_channels = 4;
2811                 } else if (detect & CM_CHIP_8768) {
2812                         cm->chip_version = 68;
2813                         cm->max_channels = 8;
2814                         cm->can_96k = 1;
2815                 } else {
2816                         cm->chip_version = 55;
2817                         cm->max_channels = 6;
2818                         cm->can_96k = 1;
2819                 }
2820                 cm->can_ac3_hw = 1;
2821                 cm->can_multi_ch = 1;
2822         }
2823 }
2824
2825 #ifdef SUPPORT_JOYSTICK
2826 static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2827 {
2828         static const int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2829         struct gameport *gp;
2830         struct resource *r = NULL;
2831         int i, io_port = 0;
2832
2833         if (joystick_port[dev] == 0)
2834                 return -ENODEV;
2835
2836         if (joystick_port[dev] == 1) { /* auto-detect */
2837                 for (i = 0; ports[i]; i++) {
2838                         io_port = ports[i];
2839                         r = request_region(io_port, 1, "CMIPCI gameport");
2840                         if (r)
2841                                 break;
2842                 }
2843         } else {
2844                 io_port = joystick_port[dev];
2845                 r = request_region(io_port, 1, "CMIPCI gameport");
2846         }
2847
2848         if (!r) {
2849                 dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
2850                 return -EBUSY;
2851         }
2852
2853         cm->gameport = gp = gameport_allocate_port();
2854         if (!gp) {
2855                 dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
2856                 release_and_free_resource(r);
2857                 return -ENOMEM;
2858         }
2859         gameport_set_name(gp, "C-Media Gameport");
2860         gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2861         gameport_set_dev_parent(gp, &cm->pci->dev);
2862         gp->io = io_port;
2863         gameport_set_port_data(gp, r);
2864
2865         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2866
2867         gameport_register_port(cm->gameport);
2868
2869         return 0;
2870 }
2871
2872 static void snd_cmipci_free_gameport(struct cmipci *cm)
2873 {
2874         if (cm->gameport) {
2875                 struct resource *r = gameport_get_port_data(cm->gameport);
2876
2877                 gameport_unregister_port(cm->gameport);
2878                 cm->gameport = NULL;
2879
2880                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2881                 release_and_free_resource(r);
2882         }
2883 }
2884 #else
2885 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2886 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2887 #endif
2888
2889 static int snd_cmipci_free(struct cmipci *cm)
2890 {
2891         if (cm->irq >= 0) {
2892                 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2893                 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2894                 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);  /* disable ints */
2895                 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2896                 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2897                 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2898                 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2899
2900                 /* reset mixer */
2901                 snd_cmipci_mixer_write(cm, 0, 0);
2902
2903                 free_irq(cm->irq, cm);
2904         }
2905
2906         snd_cmipci_free_gameport(cm);
2907         pci_release_regions(cm->pci);
2908         pci_disable_device(cm->pci);
2909         kfree(cm);
2910         return 0;
2911 }
2912
2913 static int snd_cmipci_dev_free(struct snd_device *device)
2914 {
2915         struct cmipci *cm = device->device_data;
2916         return snd_cmipci_free(cm);
2917 }
2918
2919 static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2920 {
2921         long iosynth;
2922         unsigned int val;
2923         struct snd_opl3 *opl3;
2924         int err;
2925
2926         if (!fm_port)
2927                 goto disable_fm;
2928
2929         if (cm->chip_version >= 39) {
2930                 /* first try FM regs in PCI port range */
2931                 iosynth = cm->iobase + CM_REG_FM_PCI;
2932                 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2933                                       OPL3_HW_OPL3, 1, &opl3);
2934         } else {
2935                 err = -EIO;
2936         }
2937         if (err < 0) {
2938                 /* then try legacy ports */
2939                 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2940                 iosynth = fm_port;
2941                 switch (iosynth) {
2942                 case 0x3E8: val |= CM_FMSEL_3E8; break;
2943                 case 0x3E0: val |= CM_FMSEL_3E0; break;
2944                 case 0x3C8: val |= CM_FMSEL_3C8; break;
2945                 case 0x388: val |= CM_FMSEL_388; break;
2946                 default:
2947                         goto disable_fm;
2948                 }
2949                 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2950                 /* enable FM */
2951                 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2952
2953                 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2954                                     OPL3_HW_OPL3, 0, &opl3) < 0) {
2955                         dev_err(cm->card->dev,
2956                                 "no OPL device at %#lx, skipping...\n",
2957                                 iosynth);
2958                         goto disable_fm;
2959                 }
2960         }
2961         if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
2962                 dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
2963                 return err;
2964         }
2965         return 0;
2966
2967  disable_fm:
2968         snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2969         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2970         return 0;
2971 }
2972
2973 static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2974                              int dev, struct cmipci **rcmipci)
2975 {
2976         struct cmipci *cm;
2977         int err;
2978         static const struct snd_device_ops ops = {
2979                 .dev_free =     snd_cmipci_dev_free,
2980         };
2981         unsigned int val;
2982         long iomidi = 0;
2983         int integrated_midi = 0;
2984         char modelstr[16];
2985         int pcm_index, pcm_spdif_index;
2986         static const struct pci_device_id intel_82437vx[] = {
2987                 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2988                 { },
2989         };
2990
2991         *rcmipci = NULL;
2992
2993         if ((err = pci_enable_device(pci)) < 0)
2994                 return err;
2995
2996         cm = kzalloc(sizeof(*cm), GFP_KERNEL);
2997         if (cm == NULL) {
2998                 pci_disable_device(pci);
2999                 return -ENOMEM;
3000         }
3001
3002         spin_lock_init(&cm->reg_lock);
3003         mutex_init(&cm->open_mutex);
3004         cm->device = pci->device;
3005         cm->card = card;
3006         cm->pci = pci;
3007         cm->irq = -1;
3008         cm->channel[0].ch = 0;
3009         cm->channel[1].ch = 1;
3010         cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
3011
3012         if ((err = pci_request_regions(pci, card->driver)) < 0) {
3013                 kfree(cm);
3014                 pci_disable_device(pci);
3015                 return err;
3016         }
3017         cm->iobase = pci_resource_start(pci, 0);
3018
3019         if (request_irq(pci->irq, snd_cmipci_interrupt,
3020                         IRQF_SHARED, KBUILD_MODNAME, cm)) {
3021                 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
3022                 snd_cmipci_free(cm);
3023                 return -EBUSY;
3024         }
3025         cm->irq = pci->irq;
3026         card->sync_irq = cm->irq;
3027
3028         pci_set_master(cm->pci);
3029
3030         /*
3031          * check chip version, max channels and capabilities
3032          */
3033
3034         cm->chip_version = 0;
3035         cm->max_channels = 2;
3036         cm->do_soft_ac3 = soft_ac3[dev];
3037
3038         if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3039             pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3040                 query_chip(cm);
3041         /* added -MCx suffix for chip supporting multi-channels */
3042         if (cm->can_multi_ch)
3043                 sprintf(cm->card->driver + strlen(cm->card->driver),
3044                         "-MC%d", cm->max_channels);
3045         else if (cm->can_ac3_sw)
3046                 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3047
3048         cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3049         cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3050
3051 #if CM_CH_PLAY == 1
3052         cm->ctrl = CM_CHADC0;   /* default FUNCNTRL0 */
3053 #else
3054         cm->ctrl = CM_CHADC1;   /* default FUNCNTRL0 */
3055 #endif
3056
3057         /* initialize codec registers */
3058         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3059         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3060         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);     /* disable ints */
3061         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3062         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3063         snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0);       /* disable channels */
3064         snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3065
3066         snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3067         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3068 #if CM_CH_PLAY == 1
3069         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3070 #else
3071         snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3072 #endif
3073         if (cm->chip_version) {
3074                 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3075                 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3076         }
3077         /* Set Bus Master Request */
3078         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3079
3080         /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3081         switch (pci->device) {
3082         case PCI_DEVICE_ID_CMEDIA_CM8738:
3083         case PCI_DEVICE_ID_CMEDIA_CM8738B:
3084                 if (!pci_dev_present(intel_82437vx))
3085                         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3086                 break;
3087         default:
3088                 break;
3089         }
3090
3091         if (cm->chip_version < 68) {
3092                 val = pci->device < 0x110 ? 8338 : 8738;
3093         } else {
3094                 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3095                 case 0:
3096                         val = 8769;
3097                         break;
3098                 case 2:
3099                         val = 8762;
3100                         break;
3101                 default:
3102                         switch ((pci->subsystem_vendor << 16) |
3103                                 pci->subsystem_device) {
3104                         case 0x13f69761:
3105                         case 0x584d3741:
3106                         case 0x584d3751:
3107                         case 0x584d3761:
3108                         case 0x584d3771:
3109                         case 0x72848384:
3110                                 val = 8770;
3111                                 break;
3112                         default:
3113                                 val = 8768;
3114                                 break;
3115                         }
3116                 }
3117         }
3118         sprintf(card->shortname, "C-Media CMI%d", val);
3119         if (cm->chip_version < 68)
3120                 sprintf(modelstr, " (model %d)", cm->chip_version);
3121         else
3122                 modelstr[0] = '\0';
3123         sprintf(card->longname, "%s%s at %#lx, irq %i",
3124                 card->shortname, modelstr, cm->iobase, cm->irq);
3125
3126         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
3127                 snd_cmipci_free(cm);
3128                 return err;
3129         }
3130
3131         if (cm->chip_version >= 39) {
3132                 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3133                 if (val != 0x00 && val != 0xff) {
3134                         if (mpu_port[dev])
3135                                 iomidi = cm->iobase + CM_REG_MPU_PCI;
3136                         integrated_midi = 1;
3137                 }
3138         }
3139         if (!integrated_midi) {
3140                 val = 0;
3141                 iomidi = mpu_port[dev];
3142                 switch (iomidi) {
3143                 case 0x320: val = CM_VMPU_320; break;
3144                 case 0x310: val = CM_VMPU_310; break;
3145                 case 0x300: val = CM_VMPU_300; break;
3146                 case 0x330: val = CM_VMPU_330; break;
3147                 default:
3148                             iomidi = 0; break;
3149                 }
3150                 if (iomidi > 0) {
3151                         snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3152                         /* enable UART */
3153                         snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3154                         if (inb(iomidi + 1) == 0xff) {
3155                                 dev_err(cm->card->dev,
3156                                         "cannot enable MPU-401 port at %#lx\n",
3157                                         iomidi);
3158                                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3159                                                      CM_UART_EN);
3160                                 iomidi = 0;
3161                         }
3162                 }
3163         }
3164
3165         if (cm->chip_version < 68) {
3166                 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3167                 if (err < 0)
3168                         return err;
3169         }
3170
3171         /* reset mixer */
3172         snd_cmipci_mixer_write(cm, 0, 0);
3173
3174         snd_cmipci_proc_init(cm);
3175
3176         /* create pcm devices */
3177         pcm_index = pcm_spdif_index = 0;
3178         if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3179                 return err;
3180         pcm_index++;
3181         if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3182                 return err;
3183         pcm_index++;
3184         if (cm->can_ac3_hw || cm->can_ac3_sw) {
3185                 pcm_spdif_index = pcm_index;
3186                 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3187                         return err;
3188         }
3189
3190         /* create mixer interface & switches */
3191         if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3192                 return err;
3193
3194         if (iomidi > 0) {
3195                 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3196                                                iomidi,
3197                                                (integrated_midi ?
3198                                                 MPU401_INFO_INTEGRATED : 0) |
3199                                                MPU401_INFO_IRQ_HOOK,
3200                                                -1, &cm->rmidi)) < 0) {
3201                         dev_err(cm->card->dev,
3202                                 "no UART401 device at 0x%lx\n", iomidi);
3203                 }
3204         }
3205
3206 #ifdef USE_VAR48KRATE
3207         for (val = 0; val < ARRAY_SIZE(rates); val++)
3208                 snd_cmipci_set_pll(cm, rates[val], val);
3209
3210         /*
3211          * (Re-)Enable external switch spdo_48k
3212          */
3213         snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3214 #endif /* USE_VAR48KRATE */
3215
3216         if (snd_cmipci_create_gameport(cm, dev) < 0)
3217                 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3218
3219         *rcmipci = cm;
3220         return 0;
3221 }
3222
3223 /*
3224  */
3225
3226 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3227
3228 static int snd_cmipci_probe(struct pci_dev *pci,
3229                             const struct pci_device_id *pci_id)
3230 {
3231         static int dev;
3232         struct snd_card *card;
3233         struct cmipci *cm;
3234         int err;
3235
3236         if (dev >= SNDRV_CARDS)
3237                 return -ENODEV;
3238         if (! enable[dev]) {
3239                 dev++;
3240                 return -ENOENT;
3241         }
3242
3243         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
3244                            0, &card);
3245         if (err < 0)
3246                 return err;
3247
3248         switch (pci->device) {
3249         case PCI_DEVICE_ID_CMEDIA_CM8738:
3250         case PCI_DEVICE_ID_CMEDIA_CM8738B:
3251                 strcpy(card->driver, "CMI8738");
3252                 break;
3253         case PCI_DEVICE_ID_CMEDIA_CM8338A:
3254         case PCI_DEVICE_ID_CMEDIA_CM8338B:
3255                 strcpy(card->driver, "CMI8338");
3256                 break;
3257         default:
3258                 strcpy(card->driver, "CMIPCI");
3259                 break;
3260         }
3261
3262         err = snd_cmipci_create(card, pci, dev, &cm);
3263         if (err < 0)
3264                 goto free_card;
3265
3266         card->private_data = cm;
3267
3268         err = snd_card_register(card);
3269         if (err < 0)
3270                 goto free_card;
3271
3272         pci_set_drvdata(pci, card);
3273         dev++;
3274         return 0;
3275
3276 free_card:
3277         snd_card_free(card);
3278         return err;
3279 }
3280
3281 static void snd_cmipci_remove(struct pci_dev *pci)
3282 {
3283         snd_card_free(pci_get_drvdata(pci));
3284 }
3285
3286
3287 #ifdef CONFIG_PM_SLEEP
3288 /*
3289  * power management
3290  */
3291 static const unsigned char saved_regs[] = {
3292         CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3293         CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_AUX_VOL, CM_REG_PLL,
3294         CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3295         CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3296         CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3297 };
3298
3299 static const unsigned char saved_mixers[] = {
3300         SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3301         SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3302         SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3303         SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3304         SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3305         SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3306         CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3307         SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3308 };
3309
3310 static int snd_cmipci_suspend(struct device *dev)
3311 {
3312         struct snd_card *card = dev_get_drvdata(dev);
3313         struct cmipci *cm = card->private_data;
3314         int i;
3315
3316         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3317
3318         /* save registers */
3319         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3320                 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3321         for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3322                 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3323
3324         /* disable ints */
3325         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3326         return 0;
3327 }
3328
3329 static int snd_cmipci_resume(struct device *dev)
3330 {
3331         struct snd_card *card = dev_get_drvdata(dev);
3332         struct cmipci *cm = card->private_data;
3333         int i;
3334
3335         /* reset / initialize to a sane state */
3336         snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3337         snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3338         snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3339         snd_cmipci_mixer_write(cm, 0, 0);
3340
3341         /* restore registers */
3342         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3343                 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3344         for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3345                 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3346
3347         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3348         return 0;
3349 }
3350
3351 static SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume);
3352 #define SND_CMIPCI_PM_OPS       &snd_cmipci_pm
3353 #else
3354 #define SND_CMIPCI_PM_OPS       NULL
3355 #endif /* CONFIG_PM_SLEEP */
3356
3357 static struct pci_driver cmipci_driver = {
3358         .name = KBUILD_MODNAME,
3359         .id_table = snd_cmipci_ids,
3360         .probe = snd_cmipci_probe,
3361         .remove = snd_cmipci_remove,
3362         .driver = {
3363                 .pm = SND_CMIPCI_PM_OPS,
3364         },
3365 };
3366
3367 module_pci_driver(cmipci_driver);