sound/hda/hdac_stream.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * HD-audio stream operations
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/delay.h>
   8 #include <linux/export.h>
   9 #include <linux/clocksource.h>
  10 #include <sound/core.h>
  11 #include <sound/pcm.h>
  12 #include <sound/hdaudio.h>
  13 #include <sound/hda_register.h>
  14 #include "trace.h"
  15
  16 /**
  17  * snd_hdac_get_stream_stripe_ctl - get stripe control value
  18  * @bus: HD-audio core bus
  19  * @substream: PCM substream
  20  */
  21 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
  22                                    struct snd_pcm_substream *substream)
  23 {
  24         struct snd_pcm_runtime *runtime = substream->runtime;
  25         unsigned int channels = runtime->channels,
  26                      rate = runtime->rate,
  27                      bits_per_sample = runtime->sample_bits,
  28                      max_sdo_lines, value, sdo_line;
  29
  30         /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
  31         max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
  32
  33         /* following is from HD audio spec */
  34         for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
  35                 if (rate > 48000)
  36                         value = (channels * bits_per_sample *
  37                                         (rate / 48000)) / sdo_line;
  38                 else
  39                         value = (channels * bits_per_sample) / sdo_line;
  40
  41                 if (value >= bus->sdo_limit)
  42                         break;
  43         }
  44
  45         /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
  46         return sdo_line >> 1;
  47 }
  48 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
  49
  50 /**
  51  * snd_hdac_stream_init - initialize each stream (aka device)
  52  * @bus: HD-audio core bus
  53  * @azx_dev: HD-audio core stream object to initialize
  54  * @idx: stream index number
  55  * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
  56  * @tag: the tag id to assign
  57  *
  58  * Assign the starting bdl address to each stream (device) and initialize.
  59  */
  60 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
  61                           int idx, int direction, int tag)
  62 {
  63         azx_dev->bus = bus;
  64         /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
  65         azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
  66         /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
  67         azx_dev->sd_int_sta_mask = 1 << idx;
  68         azx_dev->index = idx;
  69         azx_dev->direction = direction;
  70         azx_dev->stream_tag = tag;
  71         snd_hdac_dsp_lock_init(azx_dev);
  72         list_add_tail(&azx_dev->list, &bus->stream_list);
  73 }
  74 EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
  75
  76 /**
  77  * snd_hdac_stream_start - start a stream
  78  * @azx_dev: HD-audio core stream to start
  79  * @fresh_start: false = wallclock timestamp relative to period wallclock
  80  *
  81  * Start a stream, set start_wallclk and set the running flag.
  82  */
  83 void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
  84 {
  85         struct hdac_bus *bus = azx_dev->bus;
  86         int stripe_ctl;
  87
  88         trace_snd_hdac_stream_start(bus, azx_dev);
  89
  90         azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
  91         if (!fresh_start)
  92                 azx_dev->start_wallclk -= azx_dev->period_wallclk;
  93
  94         /* enable SIE */
  95         snd_hdac_chip_updatel(bus, INTCTL,
  96                               1 << azx_dev->index,
  97                               1 << azx_dev->index);
  98         /* set stripe control */
  99         if (azx_dev->stripe) {
 100                 if (azx_dev->substream)
 101                         stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
 102                 else
 103                         stripe_ctl = 0;
 104                 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
 105                                         stripe_ctl);
 106         }
 107         /* set DMA start and interrupt mask */
 108         snd_hdac_stream_updateb(azx_dev, SD_CTL,
 109                                 0, SD_CTL_DMA_START | SD_INT_MASK);
 110         azx_dev->running = true;
 111 }
 112 EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
 113
 114 /**
 115  * snd_hdac_stream_clear - stop a stream DMA
 116  * @azx_dev: HD-audio core stream to stop
 117  */
 118 void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
 119 {
 120         snd_hdac_stream_updateb(azx_dev, SD_CTL,
 121                                 SD_CTL_DMA_START | SD_INT_MASK, 0);
 122         snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 123         if (azx_dev->stripe)
 124                 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
 125         azx_dev->running = false;
 126 }
 127 EXPORT_SYMBOL_GPL(snd_hdac_stream_clear);
 128
 129 /**
 130  * snd_hdac_stream_stop - stop a stream
 131  * @azx_dev: HD-audio core stream to stop
 132  *
 133  * Stop a stream DMA and disable stream interrupt
 134  */
 135 void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
 136 {
 137         trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
 138
 139         snd_hdac_stream_clear(azx_dev);
 140         /* disable SIE */
 141         snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
 142 }
 143 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
 144
 145 /**
 146  * snd_hdac_stop_streams - stop all streams
 147  * @bus: HD-audio core bus
 148  */
 149 void snd_hdac_stop_streams(struct hdac_bus *bus)
 150 {
 151         struct hdac_stream *stream;
 152
 153         list_for_each_entry(stream, &bus->stream_list, list)
 154                 snd_hdac_stream_stop(stream);
 155 }
 156 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams);
 157
 158 /**
 159  * snd_hdac_stop_streams_and_chip - stop all streams and chip if running
 160  * @bus: HD-audio core bus
 161  */
 162 void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus)
 163 {
 164
 165         if (bus->chip_init) {
 166                 snd_hdac_stop_streams(bus);
 167                 snd_hdac_bus_stop_chip(bus);
 168         }
 169 }
 170 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_chip);
 171
 172 /**
 173  * snd_hdac_stream_reset - reset a stream
 174  * @azx_dev: HD-audio core stream to reset
 175  */
 176 void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
 177 {
 178         unsigned char val;
 179         int timeout;
 180         int dma_run_state;
 181
 182         snd_hdac_stream_clear(azx_dev);
 183
 184         dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START;
 185
 186         snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
 187         udelay(3);
 188         timeout = 300;
 189         do {
 190                 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
 191                         SD_CTL_STREAM_RESET;
 192                 if (val)
 193                         break;
 194         } while (--timeout);
 195
 196         if (azx_dev->bus->dma_stop_delay && dma_run_state)
 197                 udelay(azx_dev->bus->dma_stop_delay);
 198
 199         val &= ~SD_CTL_STREAM_RESET;
 200         snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
 201         udelay(3);
 202
 203         timeout = 300;
 204         /* waiting for hardware to report that the stream is out of reset */
 205         do {
 206                 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
 207                         SD_CTL_STREAM_RESET;
 208                 if (!val)
 209                         break;
 210         } while (--timeout);
 211
 212         /* reset first position - may not be synced with hw at this time */
 213         if (azx_dev->posbuf)
 214                 *azx_dev->posbuf = 0;
 215 }
 216 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
 217
 218 /**
 219  * snd_hdac_stream_setup -  set up the SD for streaming
 220  * @azx_dev: HD-audio core stream to set up
 221  */
 222 int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
 223 {
 224         struct hdac_bus *bus = azx_dev->bus;
 225         struct snd_pcm_runtime *runtime;
 226         unsigned int val;
 227
 228         if (azx_dev->substream)
 229                 runtime = azx_dev->substream->runtime;
 230         else
 231                 runtime = NULL;
 232         /* make sure the run bit is zero for SD */
 233         snd_hdac_stream_clear(azx_dev);
 234         /* program the stream_tag */
 235         val = snd_hdac_stream_readl(azx_dev, SD_CTL);
 236         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
 237                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
 238         if (!bus->snoop)
 239                 val |= SD_CTL_TRAFFIC_PRIO;
 240         snd_hdac_stream_writel(azx_dev, SD_CTL, val);
 241
 242         /* program the length of samples in cyclic buffer */
 243         snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
 244
 245         /* program the stream format */
 246         /* this value needs to be the same as the one programmed */
 247         snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
 248
 249         /* program the stream LVI (last valid index) of the BDL */
 250         snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
 251
 252         /* program the BDL address */
 253         /* lower BDL address */
 254         snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
 255         /* upper BDL address */
 256         snd_hdac_stream_writel(azx_dev, SD_BDLPU,
 257                                upper_32_bits(azx_dev->bdl.addr));
 258
 259         /* enable the position buffer */
 260         if (bus->use_posbuf && bus->posbuf.addr) {
 261                 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
 262                         snd_hdac_chip_writel(bus, DPLBASE,
 263                                 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
 264         }
 265
 266         /* set the interrupt enable bits in the descriptor control register */
 267         snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
 268
 269         azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
 270
 271         /* when LPIB delay correction gives a small negative value,
 272          * we ignore it; currently set the threshold statically to
 273          * 64 frames
 274          */
 275         if (runtime && runtime->period_size > 64)
 276                 azx_dev->delay_negative_threshold =
 277                         -frames_to_bytes(runtime, 64);
 278         else
 279                 azx_dev->delay_negative_threshold = 0;
 280
 281         /* wallclk has 24Mhz clock source */
 282         if (runtime)
 283                 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
 284                                     runtime->rate) * 1000);
 285
 286         return 0;
 287 }
 288 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
 289
 290 /**
 291  * snd_hdac_stream_cleanup - cleanup a stream
 292  * @azx_dev: HD-audio core stream to clean up
 293  */
 294 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
 295 {
 296         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 297         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 298         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
 299         azx_dev->bufsize = 0;
 300         azx_dev->period_bytes = 0;
 301         azx_dev->format_val = 0;
 302 }
 303 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
 304
 305 /**
 306  * snd_hdac_stream_assign - assign a stream for the PCM
 307  * @bus: HD-audio core bus
 308  * @substream: PCM substream to assign
 309  *
 310  * Look for an unused stream for the given PCM substream, assign it
 311  * and return the stream object.  If no stream is free, returns NULL.
 312  * The function tries to keep using the same stream object when it's used
 313  * beforehand.  Also, when bus->reverse_assign flag is set, the last free
 314  * or matching entry is returned.  This is needed for some strange codecs.
 315  */
 316 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
 317                                            struct snd_pcm_substream *substream)
 318 {
 319         struct hdac_stream *azx_dev;
 320         struct hdac_stream *res = NULL;
 321
 322         /* make a non-zero unique key for the substream */
 323         int key = (substream->number << 2) | (substream->stream + 1);
 324
 325         if (substream->pcm)
 326                 key |= (substream->pcm->device << 16);
 327
 328         spin_lock_irq(&bus->reg_lock);
 329         list_for_each_entry(azx_dev, &bus->stream_list, list) {
 330                 if (azx_dev->direction != substream->stream)
 331                         continue;
 332                 if (azx_dev->opened)
 333                         continue;
 334                 if (azx_dev->assigned_key == key) {
 335                         res = azx_dev;
 336                         break;
 337                 }
 338                 if (!res || bus->reverse_assign)
 339                         res = azx_dev;
 340         }
 341         if (res) {
 342                 res->opened = 1;
 343                 res->running = 0;
 344                 res->assigned_key = key;
 345                 res->substream = substream;
 346         }
 347         spin_unlock_irq(&bus->reg_lock);
 348         return res;
 349 }
 350 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
 351
 352 /**
 353  * snd_hdac_stream_release - release the assigned stream
 354  * @azx_dev: HD-audio core stream to release
 355  *
 356  * Release the stream that has been assigned by snd_hdac_stream_assign().
 357  */
 358 void snd_hdac_stream_release(struct hdac_stream *azx_dev)
 359 {
 360         struct hdac_bus *bus = azx_dev->bus;
 361
 362         spin_lock_irq(&bus->reg_lock);
 363         azx_dev->opened = 0;
 364         azx_dev->running = 0;
 365         azx_dev->substream = NULL;
 366         spin_unlock_irq(&bus->reg_lock);
 367 }
 368 EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
 369
 370 /**
 371  * snd_hdac_get_stream - return hdac_stream based on stream_tag and
 372  * direction
 373  *
 374  * @bus: HD-audio core bus
 375  * @dir: direction for the stream to be found
 376  * @stream_tag: stream tag for stream to be found
 377  */
 378 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
 379                                         int dir, int stream_tag)
 380 {
 381         struct hdac_stream *s;
 382
 383         list_for_each_entry(s, &bus->stream_list, list) {
 384                 if (s->direction == dir && s->stream_tag == stream_tag)
 385                         return s;
 386         }
 387
 388         return NULL;
 389 }
 390 EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
 391
 392 /*
 393  * set up a BDL entry
 394  */
 395 static int setup_bdle(struct hdac_bus *bus,
 396                       struct snd_dma_buffer *dmab,
 397                       struct hdac_stream *azx_dev, __le32 **bdlp,
 398                       int ofs, int size, int with_ioc)
 399 {
 400         __le32 *bdl = *bdlp;
 401
 402         while (size > 0) {
 403                 dma_addr_t addr;
 404                 int chunk;
 405
 406                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
 407                         return -EINVAL;
 408
 409                 addr = snd_sgbuf_get_addr(dmab, ofs);
 410                 /* program the address field of the BDL entry */
 411                 bdl[0] = cpu_to_le32((u32)addr);
 412                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
 413                 /* program the size field of the BDL entry */
 414                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
 415                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
 416                 if (bus->align_bdle_4k) {
 417                         u32 remain = 0x1000 - (ofs & 0xfff);
 418
 419                         if (chunk > remain)
 420                                 chunk = remain;
 421                 }
 422                 bdl[2] = cpu_to_le32(chunk);
 423                 /* program the IOC to enable interrupt
 424                  * only when the whole fragment is processed
 425                  */
 426                 size -= chunk;
 427                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
 428                 bdl += 4;
 429                 azx_dev->frags++;
 430                 ofs += chunk;
 431         }
 432         *bdlp = bdl;
 433         return ofs;
 434 }
 435
 436 /**
 437  * snd_hdac_stream_setup_periods - set up BDL entries
 438  * @azx_dev: HD-audio core stream to set up
 439  *
 440  * Set up the buffer descriptor table of the given stream based on the
 441  * period and buffer sizes of the assigned PCM substream.
 442  */
 443 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
 444 {
 445         struct hdac_bus *bus = azx_dev->bus;
 446         struct snd_pcm_substream *substream = azx_dev->substream;
 447         struct snd_pcm_runtime *runtime = substream->runtime;
 448         __le32 *bdl;
 449         int i, ofs, periods, period_bytes;
 450         int pos_adj, pos_align;
 451
 452         /* reset BDL address */
 453         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 454         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 455
 456         period_bytes = azx_dev->period_bytes;
 457         periods = azx_dev->bufsize / period_bytes;
 458
 459         /* program the initial BDL entries */
 460         bdl = (__le32 *)azx_dev->bdl.area;
 461         ofs = 0;
 462         azx_dev->frags = 0;
 463
 464         pos_adj = bus->bdl_pos_adj;
 465         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
 466                 pos_align = pos_adj;
 467                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
 468                 if (!pos_adj)
 469                         pos_adj = pos_align;
 470                 else
 471                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
 472                                 pos_align;
 473                 pos_adj = frames_to_bytes(runtime, pos_adj);
 474                 if (pos_adj >= period_bytes) {
 475                         dev_warn(bus->dev, "Too big adjustment %d\n",
 476                                  pos_adj);
 477                         pos_adj = 0;
 478                 } else {
 479                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
 480                                          azx_dev,
 481                                          &bdl, ofs, pos_adj, true);
 482                         if (ofs < 0)
 483                                 goto error;
 484                 }
 485         } else
 486                 pos_adj = 0;
 487
 488         for (i = 0; i < periods; i++) {
 489                 if (i == periods - 1 && pos_adj)
 490                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
 491                                          azx_dev, &bdl, ofs,
 492                                          period_bytes - pos_adj, 0);
 493                 else
 494                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
 495                                          azx_dev, &bdl, ofs,
 496                                          period_bytes,
 497                                          !azx_dev->no_period_wakeup);
 498                 if (ofs < 0)
 499                         goto error;
 500         }
 501         return 0;
 502
 503  error:
 504         dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
 505                 azx_dev->bufsize, period_bytes);
 506         return -EINVAL;
 507 }
 508 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
 509
 510 /**
 511  * snd_hdac_stream_set_params - set stream parameters
 512  * @azx_dev: HD-audio core stream for which parameters are to be set
 513  * @format_val: format value parameter
 514  *
 515  * Setup the HD-audio core stream parameters from substream of the stream
 516  * and passed format value
 517  */
 518 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
 519                                  unsigned int format_val)
 520 {
 521
 522         unsigned int bufsize, period_bytes;
 523         struct snd_pcm_substream *substream = azx_dev->substream;
 524         struct snd_pcm_runtime *runtime;
 525         int err;
 526
 527         if (!substream)
 528                 return -EINVAL;
 529         runtime = substream->runtime;
 530         bufsize = snd_pcm_lib_buffer_bytes(substream);
 531         period_bytes = snd_pcm_lib_period_bytes(substream);
 532
 533         if (bufsize != azx_dev->bufsize ||
 534             period_bytes != azx_dev->period_bytes ||
 535             format_val != azx_dev->format_val ||
 536             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
 537                 azx_dev->bufsize = bufsize;
 538                 azx_dev->period_bytes = period_bytes;
 539                 azx_dev->format_val = format_val;
 540                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
 541                 err = snd_hdac_stream_setup_periods(azx_dev);
 542                 if (err < 0)
 543                         return err;
 544         }
 545         return 0;
 546 }
 547 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
 548
 549 static u64 azx_cc_read(const struct cyclecounter *cc)
 550 {
 551         struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
 552
 553         return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
 554 }
 555
 556 static void azx_timecounter_init(struct hdac_stream *azx_dev,
 557                                  bool force, u64 last)
 558 {
 559         struct timecounter *tc = &azx_dev->tc;
 560         struct cyclecounter *cc = &azx_dev->cc;
 561         u64 nsec;
 562
 563         cc->read = azx_cc_read;
 564         cc->mask = CLOCKSOURCE_MASK(32);
 565
 566         /*
 567          * Converting from 24 MHz to ns means applying a 125/3 factor.
 568          * To avoid any saturation issues in intermediate operations,
 569          * the 125 factor is applied first. The division is applied
 570          * last after reading the timecounter value.
 571          * Applying the 1/3 factor as part of the multiplication
 572          * requires at least 20 bits for a decent precision, however
 573          * overflows occur after about 4 hours or less, not a option.
 574          */
 575
 576         cc->mult = 125; /* saturation after 195 years */
 577         cc->shift = 0;
 578
 579         nsec = 0; /* audio time is elapsed time since trigger */
 580         timecounter_init(tc, cc, nsec);
 581         if (force) {
 582                 /*
 583                  * force timecounter to use predefined value,
 584                  * used for synchronized starts
 585                  */
 586                 tc->cycle_last = last;
 587         }
 588 }
 589
 590 /**
 591  * snd_hdac_stream_timecounter_init - initialize time counter
 592  * @azx_dev: HD-audio core stream (master stream)
 593  * @streams: bit flags of streams to set up
 594  *
 595  * Initializes the time counter of streams marked by the bit flags (each
 596  * bit corresponds to the stream index).
 597  * The trigger timestamp of PCM substream assigned to the given stream is
 598  * updated accordingly, too.
 599  */
 600 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
 601                                       unsigned int streams)
 602 {
 603         struct hdac_bus *bus = azx_dev->bus;
 604         struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
 605         struct hdac_stream *s;
 606         bool inited = false;
 607         u64 cycle_last = 0;
 608
 609         list_for_each_entry(s, &bus->stream_list, list) {
 610                 if ((streams & (1 << s->index))) {
 611                         azx_timecounter_init(s, inited, cycle_last);
 612                         if (!inited) {
 613                                 inited = true;
 614                                 cycle_last = s->tc.cycle_last;
 615                         }
 616                 }
 617         }
 618
 619         snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
 620         runtime->trigger_tstamp_latched = true;
 621 }
 622 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
 623
 624 /**
 625  * snd_hdac_stream_sync_trigger - turn on/off stream sync register
 626  * @azx_dev: HD-audio core stream (master stream)
 627  * @set: true = set, false = clear
 628  * @streams: bit flags of streams to sync
 629  * @reg: the stream sync register address
 630  */
 631 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
 632                                   unsigned int streams, unsigned int reg)
 633 {
 634         struct hdac_bus *bus = azx_dev->bus;
 635         unsigned int val;
 636
 637         if (!reg)
 638                 reg = AZX_REG_SSYNC;
 639         val = _snd_hdac_chip_readl(bus, reg);
 640         if (set)
 641                 val |= streams;
 642         else
 643                 val &= ~streams;
 644         _snd_hdac_chip_writel(bus, reg, val);
 645 }
 646 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
 647
 648 /**
 649  * snd_hdac_stream_sync - sync with start/strop trigger operation
 650  * @azx_dev: HD-audio core stream (master stream)
 651  * @start: true = start, false = stop
 652  * @streams: bit flags of streams to sync
 653  *
 654  * For @start = true, wait until all FIFOs get ready.
 655  * For @start = false, wait until all RUN bits are cleared.
 656  */
 657 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
 658                           unsigned int streams)
 659 {
 660         struct hdac_bus *bus = azx_dev->bus;
 661         int nwait, timeout;
 662         struct hdac_stream *s;
 663
 664         for (timeout = 5000; timeout; timeout--) {
 665                 nwait = 0;
 666                 list_for_each_entry(s, &bus->stream_list, list) {
 667                         if (!(streams & (1 << s->index)))
 668                                 continue;
 669
 670                         if (start) {
 671                                 /* check FIFO gets ready */
 672                                 if (!(snd_hdac_stream_readb(s, SD_STS) &
 673                                       SD_STS_FIFO_READY))
 674                                         nwait++;
 675                         } else {
 676                                 /* check RUN bit is cleared */
 677                                 if (snd_hdac_stream_readb(s, SD_CTL) &
 678                                     SD_CTL_DMA_START) {
 679                                         nwait++;
 680                                         /*
 681                                          * Perform stream reset if DMA RUN
 682                                          * bit not cleared within given timeout
 683                                          */
 684                                         if (timeout == 1)
 685                                                 snd_hdac_stream_reset(s);
 686                                 }
 687                         }
 688                 }
 689                 if (!nwait)
 690                         break;
 691                 cpu_relax();
 692         }
 693 }
 694 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
 695
 696 #ifdef CONFIG_SND_HDA_DSP_LOADER
 697 /**
 698  * snd_hdac_dsp_prepare - prepare for DSP loading
 699  * @azx_dev: HD-audio core stream used for DSP loading
 700  * @format: HD-audio stream format
 701  * @byte_size: data chunk byte size
 702  * @bufp: allocated buffer
 703  *
 704  * Allocate the buffer for the given size and set up the given stream for
 705  * DSP loading.  Returns the stream tag (>= 0), or a negative error code.
 706  */
 707 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
 708                          unsigned int byte_size, struct snd_dma_buffer *bufp)
 709 {
 710         struct hdac_bus *bus = azx_dev->bus;
 711         __le32 *bdl;
 712         int err;
 713
 714         snd_hdac_dsp_lock(azx_dev);
 715         spin_lock_irq(&bus->reg_lock);
 716         if (azx_dev->running || azx_dev->locked) {
 717                 spin_unlock_irq(&bus->reg_lock);
 718                 err = -EBUSY;
 719                 goto unlock;
 720         }
 721         azx_dev->locked = true;
 722         spin_unlock_irq(&bus->reg_lock);
 723
 724         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
 725                                   byte_size, bufp);
 726         if (err < 0)
 727                 goto err_alloc;
 728
 729         azx_dev->substream = NULL;
 730         azx_dev->bufsize = byte_size;
 731         azx_dev->period_bytes = byte_size;
 732         azx_dev->format_val = format;
 733
 734         snd_hdac_stream_reset(azx_dev);
 735
 736         /* reset BDL address */
 737         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 738         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 739
 740         azx_dev->frags = 0;
 741         bdl = (__le32 *)azx_dev->bdl.area;
 742         err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
 743         if (err < 0)
 744                 goto error;
 745
 746         snd_hdac_stream_setup(azx_dev);
 747         snd_hdac_dsp_unlock(azx_dev);
 748         return azx_dev->stream_tag;
 749
 750  error:
 751         snd_dma_free_pages(bufp);
 752  err_alloc:
 753         spin_lock_irq(&bus->reg_lock);
 754         azx_dev->locked = false;
 755         spin_unlock_irq(&bus->reg_lock);
 756  unlock:
 757         snd_hdac_dsp_unlock(azx_dev);
 758         return err;
 759 }
 760 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
 761
 762 /**
 763  * snd_hdac_dsp_trigger - start / stop DSP loading
 764  * @azx_dev: HD-audio core stream used for DSP loading
 765  * @start: trigger start or stop
 766  */
 767 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
 768 {
 769         if (start)
 770                 snd_hdac_stream_start(azx_dev, true);
 771         else
 772                 snd_hdac_stream_stop(azx_dev);
 773 }
 774 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
 775
 776 /**
 777  * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
 778  * @azx_dev: HD-audio core stream used for DSP loading
 779  * @dmab: buffer used by DSP loading
 780  */
 781 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
 782                           struct snd_dma_buffer *dmab)
 783 {
 784         struct hdac_bus *bus = azx_dev->bus;
 785
 786         if (!dmab->area || !azx_dev->locked)
 787                 return;
 788
 789         snd_hdac_dsp_lock(azx_dev);
 790         /* reset BDL address */
 791         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 792         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 793         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
 794         azx_dev->bufsize = 0;
 795         azx_dev->period_bytes = 0;
 796         azx_dev->format_val = 0;
 797
 798         snd_dma_free_pages(dmab);
 799         dmab->area = NULL;
 800
 801         spin_lock_irq(&bus->reg_lock);
 802         azx_dev->locked = false;
 803         spin_unlock_irq(&bus->reg_lock);
 804         snd_hdac_dsp_unlock(azx_dev);
 805 }
 806 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
 807 #endif /* CONFIG_SND_HDA_DSP_LOADER */