1 // SPDX-License-Identifier: GPL-2.0-only
3 * HD-audio stream operations
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/export.h>
9 #include <linux/clocksource.h>
10 #include <sound/compress_driver.h>
11 #include <sound/core.h>
12 #include <sound/pcm.h>
13 #include <sound/hdaudio.h>
14 #include <sound/hda_register.h>
18 * the hdac_stream library is intended to be used with the following
19 * transitions. The states are not formally defined in the code but loosely
20 * inspired by boolean variables. Note that the 'prepared' field is not used
21 * in this library but by the callers during the hw_params/prepare transitions
30 * stream_assign() | | stream_release()
37 * stream_setup() | | stream_cleanup()
43 * stream_start() | | stream_stop()
51 * snd_hdac_get_stream_stripe_ctl - get stripe control value
52 * @bus: HD-audio core bus
53 * @substream: PCM substream
55 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
56 struct snd_pcm_substream *substream)
58 struct snd_pcm_runtime *runtime = substream->runtime;
59 unsigned int channels = runtime->channels,
61 bits_per_sample = runtime->sample_bits,
62 max_sdo_lines, value, sdo_line;
64 /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
65 max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
67 /* following is from HD audio spec */
68 for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
70 value = (channels * bits_per_sample *
71 (rate / 48000)) / sdo_line;
73 value = (channels * bits_per_sample) / sdo_line;
75 if (value >= bus->sdo_limit)
79 /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
82 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
85 * snd_hdac_stream_init - initialize each stream (aka device)
86 * @bus: HD-audio core bus
87 * @azx_dev: HD-audio core stream object to initialize
88 * @idx: stream index number
89 * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
90 * @tag: the tag id to assign
92 * Assign the starting bdl address to each stream (device) and initialize.
94 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
95 int idx, int direction, int tag)
98 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
99 azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
100 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
101 azx_dev->sd_int_sta_mask = 1 << idx;
102 azx_dev->index = idx;
103 azx_dev->direction = direction;
104 azx_dev->stream_tag = tag;
105 snd_hdac_dsp_lock_init(azx_dev);
106 list_add_tail(&azx_dev->list, &bus->stream_list);
109 azx_dev->spib_addr = bus->spbcap + AZX_SPB_BASE +
110 AZX_SPB_INTERVAL * idx +
113 azx_dev->fifo_addr = bus->spbcap + AZX_SPB_BASE +
114 AZX_SPB_INTERVAL * idx +
119 azx_dev->dpibr_addr = bus->drsmcap + AZX_DRSM_BASE +
120 AZX_DRSM_INTERVAL * idx;
122 EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
125 * snd_hdac_stream_start - start a stream
126 * @azx_dev: HD-audio core stream to start
128 * Start a stream, set start_wallclk and set the running flag.
130 void snd_hdac_stream_start(struct hdac_stream *azx_dev)
132 struct hdac_bus *bus = azx_dev->bus;
135 trace_snd_hdac_stream_start(bus, azx_dev);
137 azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
140 snd_hdac_chip_updatel(bus, INTCTL,
142 1 << azx_dev->index);
143 /* set stripe control */
144 if (azx_dev->stripe) {
145 if (azx_dev->substream)
146 stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
149 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
152 /* set DMA start and interrupt mask */
153 if (bus->access_sdnctl_in_dword)
154 snd_hdac_stream_updatel(azx_dev, SD_CTL,
155 0, SD_CTL_DMA_START | SD_INT_MASK);
157 snd_hdac_stream_updateb(azx_dev, SD_CTL,
158 0, SD_CTL_DMA_START | SD_INT_MASK);
159 azx_dev->running = true;
161 EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
164 * snd_hdac_stream_clear - helper to clear stream registers and stop DMA transfers
165 * @azx_dev: HD-audio core stream to stop
167 static void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
169 snd_hdac_stream_updateb(azx_dev, SD_CTL,
170 SD_CTL_DMA_START | SD_INT_MASK, 0);
171 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
173 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
174 azx_dev->running = false;
178 * snd_hdac_stream_stop - stop a stream
179 * @azx_dev: HD-audio core stream to stop
181 * Stop a stream DMA and disable stream interrupt
183 void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
185 trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
187 snd_hdac_stream_clear(azx_dev);
189 snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
191 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
194 * snd_hdac_stop_streams - stop all streams
195 * @bus: HD-audio core bus
197 void snd_hdac_stop_streams(struct hdac_bus *bus)
199 struct hdac_stream *stream;
201 list_for_each_entry(stream, &bus->stream_list, list)
202 snd_hdac_stream_stop(stream);
204 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams);
207 * snd_hdac_stop_streams_and_chip - stop all streams and chip if running
208 * @bus: HD-audio core bus
210 void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus)
213 if (bus->chip_init) {
214 snd_hdac_stop_streams(bus);
215 snd_hdac_bus_stop_chip(bus);
218 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_chip);
221 * snd_hdac_stream_reset - reset a stream
222 * @azx_dev: HD-audio core stream to reset
224 void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
229 snd_hdac_stream_clear(azx_dev);
231 dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START;
233 snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
235 /* wait for hardware to report that the stream entered reset */
236 snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, (val & SD_CTL_STREAM_RESET), 3, 300);
238 if (azx_dev->bus->dma_stop_delay && dma_run_state)
239 udelay(azx_dev->bus->dma_stop_delay);
241 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_CTL_STREAM_RESET, 0);
243 /* wait for hardware to report that the stream is out of reset */
244 snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, !(val & SD_CTL_STREAM_RESET), 3, 300);
246 /* reset first position - may not be synced with hw at this time */
248 *azx_dev->posbuf = 0;
250 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
253 * snd_hdac_stream_setup - set up the SD for streaming
254 * @azx_dev: HD-audio core stream to set up
255 * @code_loading: Whether the stream is for PCM or code-loading.
257 int snd_hdac_stream_setup(struct hdac_stream *azx_dev, bool code_loading)
259 struct hdac_bus *bus = azx_dev->bus;
260 struct snd_pcm_runtime *runtime;
265 if (azx_dev->substream)
266 runtime = azx_dev->substream->runtime;
269 /* make sure the run bit is zero for SD */
270 snd_hdac_stream_clear(azx_dev);
271 /* program the stream_tag */
272 val = snd_hdac_stream_readl(azx_dev, SD_CTL);
273 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
274 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
276 val |= SD_CTL_TRAFFIC_PRIO;
277 snd_hdac_stream_writel(azx_dev, SD_CTL, val);
279 /* program the length of samples in cyclic buffer */
280 snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
282 /* program the stream format */
283 /* this value needs to be the same as the one programmed */
284 snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
286 /* program the stream LVI (last valid index) of the BDL */
287 snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
289 /* program the BDL address */
290 /* lower BDL address */
291 snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
292 /* upper BDL address */
293 snd_hdac_stream_writel(azx_dev, SD_BDLPU,
294 upper_32_bits(azx_dev->bdl.addr));
296 /* enable the position buffer */
297 if (bus->use_posbuf && bus->posbuf.addr) {
298 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
299 snd_hdac_chip_writel(bus, DPLBASE,
300 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
303 /* set the interrupt enable bits in the descriptor control register */
304 snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
307 /* Once SDxFMT is set, the controller programs SDxFIFOS to non-zero value. */
308 ret = snd_hdac_stream_readw_poll(azx_dev, SD_FIFOSIZE, reg,
309 reg & AZX_SD_FIFOSIZE_MASK, 3, 300);
311 dev_dbg(bus->dev, "polling SD_FIFOSIZE 0x%04x failed: %d\n",
312 AZX_REG_SD_FIFOSIZE, ret);
313 azx_dev->fifo_size = reg;
316 /* when LPIB delay correction gives a small negative value,
317 * we ignore it; currently set the threshold statically to
320 if (runtime && runtime->period_size > 64)
321 azx_dev->delay_negative_threshold =
322 -frames_to_bytes(runtime, 64);
324 azx_dev->delay_negative_threshold = 0;
326 /* wallclk has 24Mhz clock source */
328 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
329 runtime->rate) * 1000);
333 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
336 * snd_hdac_stream_cleanup - cleanup a stream
337 * @azx_dev: HD-audio core stream to clean up
339 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
341 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
342 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
343 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
344 azx_dev->bufsize = 0;
345 azx_dev->period_bytes = 0;
346 azx_dev->format_val = 0;
348 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
351 * snd_hdac_stream_assign - assign a stream for the PCM
352 * @bus: HD-audio core bus
353 * @substream: PCM substream to assign
355 * Look for an unused stream for the given PCM substream, assign it
356 * and return the stream object. If no stream is free, returns NULL.
357 * The function tries to keep using the same stream object when it's used
358 * beforehand. Also, when bus->reverse_assign flag is set, the last free
359 * or matching entry is returned. This is needed for some strange codecs.
361 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
362 struct snd_pcm_substream *substream)
364 struct hdac_stream *azx_dev;
365 struct hdac_stream *res = NULL;
367 /* make a non-zero unique key for the substream */
368 int key = (substream->number << 2) | (substream->stream + 1);
371 key |= (substream->pcm->device << 16);
373 spin_lock_irq(&bus->reg_lock);
374 list_for_each_entry(azx_dev, &bus->stream_list, list) {
375 if (azx_dev->direction != substream->stream)
379 if (azx_dev->assigned_key == key) {
383 if (!res || bus->reverse_assign)
389 res->assigned_key = key;
390 res->substream = substream;
392 spin_unlock_irq(&bus->reg_lock);
395 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
398 * snd_hdac_stream_release_locked - release the assigned stream
399 * @azx_dev: HD-audio core stream to release
401 * Release the stream that has been assigned by snd_hdac_stream_assign().
402 * The bus->reg_lock needs to be taken at a higher level
404 void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev)
407 azx_dev->running = 0;
408 azx_dev->substream = NULL;
410 EXPORT_SYMBOL_GPL(snd_hdac_stream_release_locked);
413 * snd_hdac_stream_release - release the assigned stream
414 * @azx_dev: HD-audio core stream to release
416 * Release the stream that has been assigned by snd_hdac_stream_assign().
418 void snd_hdac_stream_release(struct hdac_stream *azx_dev)
420 struct hdac_bus *bus = azx_dev->bus;
422 spin_lock_irq(&bus->reg_lock);
423 snd_hdac_stream_release_locked(azx_dev);
424 spin_unlock_irq(&bus->reg_lock);
426 EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
429 * snd_hdac_get_stream - return hdac_stream based on stream_tag and
432 * @bus: HD-audio core bus
433 * @dir: direction for the stream to be found
434 * @stream_tag: stream tag for stream to be found
436 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
437 int dir, int stream_tag)
439 struct hdac_stream *s;
441 list_for_each_entry(s, &bus->stream_list, list) {
442 if (s->direction == dir && s->stream_tag == stream_tag)
448 EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
453 static int setup_bdle(struct hdac_bus *bus,
454 struct snd_dma_buffer *dmab,
455 struct hdac_stream *azx_dev, __le32 **bdlp,
456 int ofs, int size, int with_ioc)
464 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
467 addr = snd_sgbuf_get_addr(dmab, ofs);
468 /* program the address field of the BDL entry */
469 bdl[0] = cpu_to_le32((u32)addr);
470 bdl[1] = cpu_to_le32(upper_32_bits(addr));
471 /* program the size field of the BDL entry */
472 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
473 /* one BDLE cannot cross 4K boundary on CTHDA chips */
474 if (bus->align_bdle_4k) {
475 u32 remain = 0x1000 - (ofs & 0xfff);
480 bdl[2] = cpu_to_le32(chunk);
481 /* program the IOC to enable interrupt
482 * only when the whole fragment is processed
485 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
495 * snd_hdac_stream_setup_periods - set up BDL entries
496 * @azx_dev: HD-audio core stream to set up
498 * Set up the buffer descriptor table of the given stream based on the
499 * period and buffer sizes of the assigned PCM substream.
501 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
503 struct hdac_bus *bus = azx_dev->bus;
504 struct snd_pcm_substream *substream = azx_dev->substream;
505 struct snd_compr_stream *cstream = azx_dev->cstream;
506 struct snd_pcm_runtime *runtime = NULL;
507 struct snd_dma_buffer *dmab;
509 int i, ofs, periods, period_bytes;
510 int pos_adj, pos_align;
513 runtime = substream->runtime;
514 dmab = snd_pcm_get_dma_buf(substream);
515 } else if (cstream) {
516 dmab = snd_pcm_get_dma_buf(cstream);
518 WARN(1, "No substream or cstream assigned\n");
522 /* reset BDL address */
523 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
524 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
526 period_bytes = azx_dev->period_bytes;
527 periods = azx_dev->bufsize / period_bytes;
529 /* program the initial BDL entries */
530 bdl = (__le32 *)azx_dev->bdl.area;
534 pos_adj = bus->bdl_pos_adj;
535 if (runtime && !azx_dev->no_period_wakeup && pos_adj > 0) {
537 pos_adj = DIV_ROUND_UP(pos_adj * runtime->rate, 48000);
541 pos_adj = roundup(pos_adj, pos_align);
542 pos_adj = frames_to_bytes(runtime, pos_adj);
543 if (pos_adj >= period_bytes) {
544 dev_warn(bus->dev, "Too big adjustment %d\n",
548 ofs = setup_bdle(bus, dmab, azx_dev,
549 &bdl, ofs, pos_adj, true);
556 for (i = 0; i < periods; i++) {
557 if (i == periods - 1 && pos_adj)
558 ofs = setup_bdle(bus, dmab, azx_dev,
559 &bdl, ofs, period_bytes - pos_adj, 0);
561 ofs = setup_bdle(bus, dmab, azx_dev,
562 &bdl, ofs, period_bytes,
563 !azx_dev->no_period_wakeup);
570 dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
571 azx_dev->bufsize, period_bytes);
574 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
577 * snd_hdac_stream_set_params - set stream parameters
578 * @azx_dev: HD-audio core stream for which parameters are to be set
579 * @format_val: format value parameter
581 * Setup the HD-audio core stream parameters from substream of the stream
582 * and passed format value
584 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
585 unsigned int format_val)
587 struct snd_pcm_substream *substream = azx_dev->substream;
588 struct snd_compr_stream *cstream = azx_dev->cstream;
589 unsigned int bufsize, period_bytes;
590 unsigned int no_period_wakeup;
594 bufsize = snd_pcm_lib_buffer_bytes(substream);
595 period_bytes = snd_pcm_lib_period_bytes(substream);
596 no_period_wakeup = substream->runtime->no_period_wakeup;
597 } else if (cstream) {
598 bufsize = cstream->runtime->buffer_size;
599 period_bytes = cstream->runtime->fragment_size;
600 no_period_wakeup = 0;
605 if (bufsize != azx_dev->bufsize ||
606 period_bytes != azx_dev->period_bytes ||
607 format_val != azx_dev->format_val ||
608 no_period_wakeup != azx_dev->no_period_wakeup) {
609 azx_dev->bufsize = bufsize;
610 azx_dev->period_bytes = period_bytes;
611 azx_dev->format_val = format_val;
612 azx_dev->no_period_wakeup = no_period_wakeup;
613 err = snd_hdac_stream_setup_periods(azx_dev);
619 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
621 static u64 azx_cc_read(const struct cyclecounter *cc)
623 struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
625 return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
628 static void azx_timecounter_init(struct hdac_stream *azx_dev,
629 bool force, u64 last)
631 struct timecounter *tc = &azx_dev->tc;
632 struct cyclecounter *cc = &azx_dev->cc;
635 cc->read = azx_cc_read;
636 cc->mask = CLOCKSOURCE_MASK(32);
639 * Calculate the optimal mult/shift values. The counter wraps
640 * around after ~178.9 seconds.
642 clocks_calc_mult_shift(&cc->mult, &cc->shift, 24000000,
645 nsec = 0; /* audio time is elapsed time since trigger */
646 timecounter_init(tc, cc, nsec);
649 * force timecounter to use predefined value,
650 * used for synchronized starts
652 tc->cycle_last = last;
657 * snd_hdac_stream_timecounter_init - initialize time counter
658 * @azx_dev: HD-audio core stream (master stream)
659 * @streams: bit flags of streams to set up
661 * Initializes the time counter of streams marked by the bit flags (each
662 * bit corresponds to the stream index).
663 * The trigger timestamp of PCM substream assigned to the given stream is
664 * updated accordingly, too.
666 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
667 unsigned int streams)
669 struct hdac_bus *bus = azx_dev->bus;
670 struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
671 struct hdac_stream *s;
676 list_for_each_entry(s, &bus->stream_list, list) {
677 if (streams & (1 << i)) {
678 azx_timecounter_init(s, inited, cycle_last);
681 cycle_last = s->tc.cycle_last;
687 snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
688 runtime->trigger_tstamp_latched = true;
690 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
693 * snd_hdac_stream_sync_trigger - turn on/off stream sync register
694 * @azx_dev: HD-audio core stream (master stream)
695 * @set: true = set, false = clear
696 * @streams: bit flags of streams to sync
697 * @reg: the stream sync register address
699 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
700 unsigned int streams, unsigned int reg)
702 struct hdac_bus *bus = azx_dev->bus;
707 val = _snd_hdac_chip_readl(bus, reg);
712 _snd_hdac_chip_writel(bus, reg, val);
714 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
717 * snd_hdac_stream_sync - sync with start/stop trigger operation
718 * @azx_dev: HD-audio core stream (master stream)
719 * @start: true = start, false = stop
720 * @streams: bit flags of streams to sync
722 * For @start = true, wait until all FIFOs get ready.
723 * For @start = false, wait until all RUN bits are cleared.
725 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
726 unsigned int streams)
728 struct hdac_bus *bus = azx_dev->bus;
729 int i, nwait, timeout;
730 struct hdac_stream *s;
732 for (timeout = 5000; timeout; timeout--) {
735 list_for_each_entry(s, &bus->stream_list, list) {
736 if (!(streams & (1 << i++)))
740 /* check FIFO gets ready */
741 if (!(snd_hdac_stream_readb(s, SD_STS) &
745 /* check RUN bit is cleared */
746 if (snd_hdac_stream_readb(s, SD_CTL) &
750 * Perform stream reset if DMA RUN
751 * bit not cleared within given timeout
754 snd_hdac_stream_reset(s);
763 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
766 * snd_hdac_stream_spbcap_enable - enable SPIB for a stream
767 * @bus: HD-audio core bus
768 * @enable: flag to enable/disable SPIB
769 * @index: stream index for which SPIB need to be enabled
771 void snd_hdac_stream_spbcap_enable(struct hdac_bus *bus,
772 bool enable, int index)
777 dev_err(bus->dev, "Address of SPB capability is NULL\n");
781 mask |= (1 << index);
784 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, mask);
786 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, 0);
788 EXPORT_SYMBOL_GPL(snd_hdac_stream_spbcap_enable);
791 * snd_hdac_stream_set_spib - sets the spib value of a stream
792 * @bus: HD-audio core bus
793 * @azx_dev: hdac_stream
794 * @value: spib value to set
796 int snd_hdac_stream_set_spib(struct hdac_bus *bus,
797 struct hdac_stream *azx_dev, u32 value)
800 dev_err(bus->dev, "Address of SPB capability is NULL\n");
804 writel(value, azx_dev->spib_addr);
808 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_spib);
811 * snd_hdac_stream_get_spbmaxfifo - gets the spib value of a stream
812 * @bus: HD-audio core bus
813 * @azx_dev: hdac_stream
815 * Return maxfifo for the stream
817 int snd_hdac_stream_get_spbmaxfifo(struct hdac_bus *bus,
818 struct hdac_stream *azx_dev)
821 dev_err(bus->dev, "Address of SPB capability is NULL\n");
825 return readl(azx_dev->fifo_addr);
827 EXPORT_SYMBOL_GPL(snd_hdac_stream_get_spbmaxfifo);
830 * snd_hdac_stream_drsm_enable - enable DMA resume for a stream
831 * @bus: HD-audio core bus
832 * @enable: flag to enable/disable DRSM
833 * @index: stream index for which DRSM need to be enabled
835 void snd_hdac_stream_drsm_enable(struct hdac_bus *bus,
836 bool enable, int index)
841 dev_err(bus->dev, "Address of DRSM capability is NULL\n");
845 mask |= (1 << index);
848 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, mask);
850 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, 0);
852 EXPORT_SYMBOL_GPL(snd_hdac_stream_drsm_enable);
855 * snd_hdac_stream_wait_drsm - wait for HW to clear RSM for a stream
856 * @azx_dev: HD-audio core stream to await RSM for
858 * Returns 0 on success and -ETIMEDOUT upon a timeout.
860 int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev)
862 struct hdac_bus *bus = azx_dev->bus;
866 mask = 1 << azx_dev->index;
868 ret = read_poll_timeout(snd_hdac_reg_readl, reg, !(reg & mask), 250, 2000, false, bus,
869 bus->drsmcap + AZX_REG_DRSM_CTL);
871 dev_dbg(bus->dev, "polling RSM 0x%08x failed: %d\n", mask, ret);
874 EXPORT_SYMBOL_GPL(snd_hdac_stream_wait_drsm);
877 * snd_hdac_stream_set_dpibr - sets the dpibr value of a stream
878 * @bus: HD-audio core bus
879 * @azx_dev: hdac_stream
880 * @value: dpib value to set
882 int snd_hdac_stream_set_dpibr(struct hdac_bus *bus,
883 struct hdac_stream *azx_dev, u32 value)
886 dev_err(bus->dev, "Address of DRSM capability is NULL\n");
890 writel(value, azx_dev->dpibr_addr);
894 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_dpibr);
897 * snd_hdac_stream_set_lpib - sets the lpib value of a stream
898 * @azx_dev: hdac_stream
899 * @value: lpib value to set
901 int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value)
903 snd_hdac_stream_writel(azx_dev, SD_LPIB, value);
907 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_lpib);
909 #ifdef CONFIG_SND_HDA_DSP_LOADER
911 * snd_hdac_dsp_prepare - prepare for DSP loading
912 * @azx_dev: HD-audio core stream used for DSP loading
913 * @format: HD-audio stream format
914 * @byte_size: data chunk byte size
915 * @bufp: allocated buffer
917 * Allocate the buffer for the given size and set up the given stream for
918 * DSP loading. Returns the stream tag (>= 0), or a negative error code.
920 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
921 unsigned int byte_size, struct snd_dma_buffer *bufp)
923 struct hdac_bus *bus = azx_dev->bus;
927 snd_hdac_dsp_lock(azx_dev);
928 spin_lock_irq(&bus->reg_lock);
929 if (azx_dev->running || azx_dev->locked) {
930 spin_unlock_irq(&bus->reg_lock);
934 azx_dev->locked = true;
935 spin_unlock_irq(&bus->reg_lock);
937 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
942 azx_dev->substream = NULL;
943 azx_dev->bufsize = byte_size;
944 azx_dev->period_bytes = byte_size;
945 azx_dev->format_val = format;
947 snd_hdac_stream_reset(azx_dev);
949 /* reset BDL address */
950 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
951 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
954 bdl = (__le32 *)azx_dev->bdl.area;
955 err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
959 snd_hdac_stream_setup(azx_dev, true);
960 snd_hdac_dsp_unlock(azx_dev);
961 return azx_dev->stream_tag;
964 snd_dma_free_pages(bufp);
966 spin_lock_irq(&bus->reg_lock);
967 azx_dev->locked = false;
968 spin_unlock_irq(&bus->reg_lock);
970 snd_hdac_dsp_unlock(azx_dev);
973 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
976 * snd_hdac_dsp_trigger - start / stop DSP loading
977 * @azx_dev: HD-audio core stream used for DSP loading
978 * @start: trigger start or stop
980 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
983 snd_hdac_stream_start(azx_dev);
985 snd_hdac_stream_stop(azx_dev);
987 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
990 * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
991 * @azx_dev: HD-audio core stream used for DSP loading
992 * @dmab: buffer used by DSP loading
994 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
995 struct snd_dma_buffer *dmab)
997 struct hdac_bus *bus = azx_dev->bus;
999 if (!dmab->area || !azx_dev->locked)
1002 snd_hdac_dsp_lock(azx_dev);
1003 /* reset BDL address */
1004 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
1005 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
1006 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
1007 azx_dev->bufsize = 0;
1008 azx_dev->period_bytes = 0;
1009 azx_dev->format_val = 0;
1011 snd_dma_free_pages(dmab);
1014 spin_lock_irq(&bus->reg_lock);
1015 azx_dev->locked = false;
1016 spin_unlock_irq(&bus->reg_lock);
1017 snd_hdac_dsp_unlock(azx_dev);
1019 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
1020 #endif /* CONFIG_SND_HDA_DSP_LOADER */