sound/hda/hdac_stream.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * HD-audio stream operations
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/delay.h>
   8 #include <linux/export.h>
   9 #include <linux/clocksource.h>
  10 #include <sound/core.h>
  11 #include <sound/pcm.h>
  12 #include <sound/hdaudio.h>
  13 #include <sound/hda_register.h>
  14 #include "trace.h"
  15
  16 /**
  17  * snd_hdac_get_stream_stripe_ctl - get stripe control value
  18  * @bus: HD-audio core bus
  19  * @substream: PCM substream
  20  */
  21 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
  22                                    struct snd_pcm_substream *substream)
  23 {
  24         struct snd_pcm_runtime *runtime = substream->runtime;
  25         unsigned int channels = runtime->channels,
  26                      rate = runtime->rate,
  27                      bits_per_sample = runtime->sample_bits,
  28                      max_sdo_lines, value, sdo_line;
  29
  30         /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
  31         max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
  32
  33         /* following is from HD audio spec */
  34         for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
  35                 if (rate > 48000)
  36                         value = (channels * bits_per_sample *
  37                                         (rate / 48000)) / sdo_line;
  38                 else
  39                         value = (channels * bits_per_sample) / sdo_line;
  40
  41                 if (value >= 8)
  42                         break;
  43         }
  44
  45         /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
  46         return sdo_line >> 1;
  47 }
  48 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
  49
  50 /**
  51  * snd_hdac_stream_init - initialize each stream (aka device)
  52  * @bus: HD-audio core bus
  53  * @azx_dev: HD-audio core stream object to initialize
  54  * @idx: stream index number
  55  * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
  56  * @tag: the tag id to assign
  57  *
  58  * Assign the starting bdl address to each stream (device) and initialize.
  59  */
  60 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
  61                           int idx, int direction, int tag)
  62 {
  63         azx_dev->bus = bus;
  64         /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
  65         azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
  66         /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
  67         azx_dev->sd_int_sta_mask = 1 << idx;
  68         azx_dev->index = idx;
  69         azx_dev->direction = direction;
  70         azx_dev->stream_tag = tag;
  71         snd_hdac_dsp_lock_init(azx_dev);
  72         list_add_tail(&azx_dev->list, &bus->stream_list);
  73 }
  74 EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
  75
  76 /**
  77  * snd_hdac_stream_start - start a stream
  78  * @azx_dev: HD-audio core stream to start
  79  * @fresh_start: false = wallclock timestamp relative to period wallclock
  80  *
  81  * Start a stream, set start_wallclk and set the running flag.
  82  */
  83 void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
  84 {
  85         struct hdac_bus *bus = azx_dev->bus;
  86         int stripe_ctl;
  87
  88         trace_snd_hdac_stream_start(bus, azx_dev);
  89
  90         azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
  91         if (!fresh_start)
  92                 azx_dev->start_wallclk -= azx_dev->period_wallclk;
  93
  94         /* enable SIE */
  95         snd_hdac_chip_updatel(bus, INTCTL,
  96                               1 << azx_dev->index,
  97                               1 << azx_dev->index);
  98         /* set stripe control */
  99         if (azx_dev->stripe) {
 100                 if (azx_dev->substream)
 101                         stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
 102                 else
 103                         stripe_ctl = 0;
 104                 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
 105                                         stripe_ctl);
 106         }
 107         /* set DMA start and interrupt mask */
 108         snd_hdac_stream_updateb(azx_dev, SD_CTL,
 109                                 0, SD_CTL_DMA_START | SD_INT_MASK);
 110         azx_dev->running = true;
 111 }
 112 EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
 113
 114 /**
 115  * snd_hdac_stream_clear - stop a stream DMA
 116  * @azx_dev: HD-audio core stream to stop
 117  */
 118 void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
 119 {
 120         snd_hdac_stream_updateb(azx_dev, SD_CTL,
 121                                 SD_CTL_DMA_START | SD_INT_MASK, 0);
 122         snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 123         if (azx_dev->stripe)
 124                 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
 125         azx_dev->running = false;
 126 }
 127 EXPORT_SYMBOL_GPL(snd_hdac_stream_clear);
 128
 129 /**
 130  * snd_hdac_stream_stop - stop a stream
 131  * @azx_dev: HD-audio core stream to stop
 132  *
 133  * Stop a stream DMA and disable stream interrupt
 134  */
 135 void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
 136 {
 137         trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
 138
 139         snd_hdac_stream_clear(azx_dev);
 140         /* disable SIE */
 141         snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
 142 }
 143 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
 144
 145 /**
 146  * snd_hdac_stop_streams - stop all streams
 147  * @bus: HD-audio core bus
 148  */
 149 void snd_hdac_stop_streams(struct hdac_bus *bus)
 150 {
 151         struct hdac_stream *stream;
 152
 153         list_for_each_entry(stream, &bus->stream_list, list)
 154                 snd_hdac_stream_stop(stream);
 155 }
 156 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams);
 157
 158 /**
 159  * snd_hdac_stop_streams_and_chip - stop all streams and chip if running
 160  * @bus: HD-audio core bus
 161  */
 162 void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus)
 163 {
 164
 165         if (bus->chip_init) {
 166                 snd_hdac_stop_streams(bus);
 167                 snd_hdac_bus_stop_chip(bus);
 168         }
 169 }
 170 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_chip);
 171
 172 /**
 173  * snd_hdac_stream_reset - reset a stream
 174  * @azx_dev: HD-audio core stream to reset
 175  */
 176 void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
 177 {
 178         unsigned char val;
 179         int timeout;
 180
 181         snd_hdac_stream_clear(azx_dev);
 182
 183         snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
 184         udelay(3);
 185         timeout = 300;
 186         do {
 187                 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
 188                         SD_CTL_STREAM_RESET;
 189                 if (val)
 190                         break;
 191         } while (--timeout);
 192         val &= ~SD_CTL_STREAM_RESET;
 193         snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
 194         udelay(3);
 195
 196         timeout = 300;
 197         /* waiting for hardware to report that the stream is out of reset */
 198         do {
 199                 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
 200                         SD_CTL_STREAM_RESET;
 201                 if (!val)
 202                         break;
 203         } while (--timeout);
 204
 205         /* reset first position - may not be synced with hw at this time */
 206         if (azx_dev->posbuf)
 207                 *azx_dev->posbuf = 0;
 208 }
 209 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
 210
 211 /**
 212  * snd_hdac_stream_setup -  set up the SD for streaming
 213  * @azx_dev: HD-audio core stream to set up
 214  */
 215 int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
 216 {
 217         struct hdac_bus *bus = azx_dev->bus;
 218         struct snd_pcm_runtime *runtime;
 219         unsigned int val;
 220
 221         if (azx_dev->substream)
 222                 runtime = azx_dev->substream->runtime;
 223         else
 224                 runtime = NULL;
 225         /* make sure the run bit is zero for SD */
 226         snd_hdac_stream_clear(azx_dev);
 227         /* program the stream_tag */
 228         val = snd_hdac_stream_readl(azx_dev, SD_CTL);
 229         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
 230                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
 231         if (!bus->snoop)
 232                 val |= SD_CTL_TRAFFIC_PRIO;
 233         snd_hdac_stream_writel(azx_dev, SD_CTL, val);
 234
 235         /* program the length of samples in cyclic buffer */
 236         snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
 237
 238         /* program the stream format */
 239         /* this value needs to be the same as the one programmed */
 240         snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
 241
 242         /* program the stream LVI (last valid index) of the BDL */
 243         snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
 244
 245         /* program the BDL address */
 246         /* lower BDL address */
 247         snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
 248         /* upper BDL address */
 249         snd_hdac_stream_writel(azx_dev, SD_BDLPU,
 250                                upper_32_bits(azx_dev->bdl.addr));
 251
 252         /* enable the position buffer */
 253         if (bus->use_posbuf && bus->posbuf.addr) {
 254                 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
 255                         snd_hdac_chip_writel(bus, DPLBASE,
 256                                 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
 257         }
 258
 259         /* set the interrupt enable bits in the descriptor control register */
 260         snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
 261
 262         azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
 263
 264         /* when LPIB delay correction gives a small negative value,
 265          * we ignore it; currently set the threshold statically to
 266          * 64 frames
 267          */
 268         if (runtime && runtime->period_size > 64)
 269                 azx_dev->delay_negative_threshold =
 270                         -frames_to_bytes(runtime, 64);
 271         else
 272                 azx_dev->delay_negative_threshold = 0;
 273
 274         /* wallclk has 24Mhz clock source */
 275         if (runtime)
 276                 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
 277                                     runtime->rate) * 1000);
 278
 279         return 0;
 280 }
 281 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
 282
 283 /**
 284  * snd_hdac_stream_cleanup - cleanup a stream
 285  * @azx_dev: HD-audio core stream to clean up
 286  */
 287 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
 288 {
 289         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 290         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 291         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
 292         azx_dev->bufsize = 0;
 293         azx_dev->period_bytes = 0;
 294         azx_dev->format_val = 0;
 295 }
 296 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
 297
 298 /**
 299  * snd_hdac_stream_assign - assign a stream for the PCM
 300  * @bus: HD-audio core bus
 301  * @substream: PCM substream to assign
 302  *
 303  * Look for an unused stream for the given PCM substream, assign it
 304  * and return the stream object.  If no stream is free, returns NULL.
 305  * The function tries to keep using the same stream object when it's used
 306  * beforehand.  Also, when bus->reverse_assign flag is set, the last free
 307  * or matching entry is returned.  This is needed for some strange codecs.
 308  */
 309 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
 310                                            struct snd_pcm_substream *substream)
 311 {
 312         struct hdac_stream *azx_dev;
 313         struct hdac_stream *res = NULL;
 314
 315         /* make a non-zero unique key for the substream */
 316         int key = (substream->pcm->device << 16) | (substream->number << 2) |
 317                 (substream->stream + 1);
 318
 319         spin_lock_irq(&bus->reg_lock);
 320         list_for_each_entry(azx_dev, &bus->stream_list, list) {
 321                 if (azx_dev->direction != substream->stream)
 322                         continue;
 323                 if (azx_dev->opened)
 324                         continue;
 325                 if (azx_dev->assigned_key == key) {
 326                         res = azx_dev;
 327                         break;
 328                 }
 329                 if (!res || bus->reverse_assign)
 330                         res = azx_dev;
 331         }
 332         if (res) {
 333                 res->opened = 1;
 334                 res->running = 0;
 335                 res->assigned_key = key;
 336                 res->substream = substream;
 337         }
 338         spin_unlock_irq(&bus->reg_lock);
 339         return res;
 340 }
 341 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
 342
 343 /**
 344  * snd_hdac_stream_release - release the assigned stream
 345  * @azx_dev: HD-audio core stream to release
 346  *
 347  * Release the stream that has been assigned by snd_hdac_stream_assign().
 348  */
 349 void snd_hdac_stream_release(struct hdac_stream *azx_dev)
 350 {
 351         struct hdac_bus *bus = azx_dev->bus;
 352
 353         spin_lock_irq(&bus->reg_lock);
 354         azx_dev->opened = 0;
 355         azx_dev->running = 0;
 356         azx_dev->substream = NULL;
 357         spin_unlock_irq(&bus->reg_lock);
 358 }
 359 EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
 360
 361 /**
 362  * snd_hdac_get_stream - return hdac_stream based on stream_tag and
 363  * direction
 364  *
 365  * @bus: HD-audio core bus
 366  * @dir: direction for the stream to be found
 367  * @stream_tag: stream tag for stream to be found
 368  */
 369 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
 370                                         int dir, int stream_tag)
 371 {
 372         struct hdac_stream *s;
 373
 374         list_for_each_entry(s, &bus->stream_list, list) {
 375                 if (s->direction == dir && s->stream_tag == stream_tag)
 376                         return s;
 377         }
 378
 379         return NULL;
 380 }
 381 EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
 382
 383 /*
 384  * set up a BDL entry
 385  */
 386 static int setup_bdle(struct hdac_bus *bus,
 387                       struct snd_dma_buffer *dmab,
 388                       struct hdac_stream *azx_dev, __le32 **bdlp,
 389                       int ofs, int size, int with_ioc)
 390 {
 391         __le32 *bdl = *bdlp;
 392
 393         while (size > 0) {
 394                 dma_addr_t addr;
 395                 int chunk;
 396
 397                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
 398                         return -EINVAL;
 399
 400                 addr = snd_sgbuf_get_addr(dmab, ofs);
 401                 /* program the address field of the BDL entry */
 402                 bdl[0] = cpu_to_le32((u32)addr);
 403                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
 404                 /* program the size field of the BDL entry */
 405                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
 406                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
 407                 if (bus->align_bdle_4k) {
 408                         u32 remain = 0x1000 - (ofs & 0xfff);
 409
 410                         if (chunk > remain)
 411                                 chunk = remain;
 412                 }
 413                 bdl[2] = cpu_to_le32(chunk);
 414                 /* program the IOC to enable interrupt
 415                  * only when the whole fragment is processed
 416                  */
 417                 size -= chunk;
 418                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
 419                 bdl += 4;
 420                 azx_dev->frags++;
 421                 ofs += chunk;
 422         }
 423         *bdlp = bdl;
 424         return ofs;
 425 }
 426
 427 /**
 428  * snd_hdac_stream_setup_periods - set up BDL entries
 429  * @azx_dev: HD-audio core stream to set up
 430  *
 431  * Set up the buffer descriptor table of the given stream based on the
 432  * period and buffer sizes of the assigned PCM substream.
 433  */
 434 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
 435 {
 436         struct hdac_bus *bus = azx_dev->bus;
 437         struct snd_pcm_substream *substream = azx_dev->substream;
 438         struct snd_pcm_runtime *runtime = substream->runtime;
 439         __le32 *bdl;
 440         int i, ofs, periods, period_bytes;
 441         int pos_adj, pos_align;
 442
 443         /* reset BDL address */
 444         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 445         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 446
 447         period_bytes = azx_dev->period_bytes;
 448         periods = azx_dev->bufsize / period_bytes;
 449
 450         /* program the initial BDL entries */
 451         bdl = (__le32 *)azx_dev->bdl.area;
 452         ofs = 0;
 453         azx_dev->frags = 0;
 454
 455         pos_adj = bus->bdl_pos_adj;
 456         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
 457                 pos_align = pos_adj;
 458                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
 459                 if (!pos_adj)
 460                         pos_adj = pos_align;
 461                 else
 462                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
 463                                 pos_align;
 464                 pos_adj = frames_to_bytes(runtime, pos_adj);
 465                 if (pos_adj >= period_bytes) {
 466                         dev_warn(bus->dev, "Too big adjustment %d\n",
 467                                  pos_adj);
 468                         pos_adj = 0;
 469                 } else {
 470                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
 471                                          azx_dev,
 472                                          &bdl, ofs, pos_adj, true);
 473                         if (ofs < 0)
 474                                 goto error;
 475                 }
 476         } else
 477                 pos_adj = 0;
 478
 479         for (i = 0; i < periods; i++) {
 480                 if (i == periods - 1 && pos_adj)
 481                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
 482                                          azx_dev, &bdl, ofs,
 483                                          period_bytes - pos_adj, 0);
 484                 else
 485                         ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
 486                                          azx_dev, &bdl, ofs,
 487                                          period_bytes,
 488                                          !azx_dev->no_period_wakeup);
 489                 if (ofs < 0)
 490                         goto error;
 491         }
 492         return 0;
 493
 494  error:
 495         dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
 496                 azx_dev->bufsize, period_bytes);
 497         return -EINVAL;
 498 }
 499 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
 500
 501 /**
 502  * snd_hdac_stream_set_params - set stream parameters
 503  * @azx_dev: HD-audio core stream for which parameters are to be set
 504  * @format_val: format value parameter
 505  *
 506  * Setup the HD-audio core stream parameters from substream of the stream
 507  * and passed format value
 508  */
 509 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
 510                                  unsigned int format_val)
 511 {
 512
 513         unsigned int bufsize, period_bytes;
 514         struct snd_pcm_substream *substream = azx_dev->substream;
 515         struct snd_pcm_runtime *runtime;
 516         int err;
 517
 518         if (!substream)
 519                 return -EINVAL;
 520         runtime = substream->runtime;
 521         bufsize = snd_pcm_lib_buffer_bytes(substream);
 522         period_bytes = snd_pcm_lib_period_bytes(substream);
 523
 524         if (bufsize != azx_dev->bufsize ||
 525             period_bytes != azx_dev->period_bytes ||
 526             format_val != azx_dev->format_val ||
 527             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
 528                 azx_dev->bufsize = bufsize;
 529                 azx_dev->period_bytes = period_bytes;
 530                 azx_dev->format_val = format_val;
 531                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
 532                 err = snd_hdac_stream_setup_periods(azx_dev);
 533                 if (err < 0)
 534                         return err;
 535         }
 536         return 0;
 537 }
 538 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
 539
 540 static u64 azx_cc_read(const struct cyclecounter *cc)
 541 {
 542         struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
 543
 544         return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
 545 }
 546
 547 static void azx_timecounter_init(struct hdac_stream *azx_dev,
 548                                  bool force, u64 last)
 549 {
 550         struct timecounter *tc = &azx_dev->tc;
 551         struct cyclecounter *cc = &azx_dev->cc;
 552         u64 nsec;
 553
 554         cc->read = azx_cc_read;
 555         cc->mask = CLOCKSOURCE_MASK(32);
 556
 557         /*
 558          * Converting from 24 MHz to ns means applying a 125/3 factor.
 559          * To avoid any saturation issues in intermediate operations,
 560          * the 125 factor is applied first. The division is applied
 561          * last after reading the timecounter value.
 562          * Applying the 1/3 factor as part of the multiplication
 563          * requires at least 20 bits for a decent precision, however
 564          * overflows occur after about 4 hours or less, not a option.
 565          */
 566
 567         cc->mult = 125; /* saturation after 195 years */
 568         cc->shift = 0;
 569
 570         nsec = 0; /* audio time is elapsed time since trigger */
 571         timecounter_init(tc, cc, nsec);
 572         if (force) {
 573                 /*
 574                  * force timecounter to use predefined value,
 575                  * used for synchronized starts
 576                  */
 577                 tc->cycle_last = last;
 578         }
 579 }
 580
 581 /**
 582  * snd_hdac_stream_timecounter_init - initialize time counter
 583  * @azx_dev: HD-audio core stream (master stream)
 584  * @streams: bit flags of streams to set up
 585  *
 586  * Initializes the time counter of streams marked by the bit flags (each
 587  * bit corresponds to the stream index).
 588  * The trigger timestamp of PCM substream assigned to the given stream is
 589  * updated accordingly, too.
 590  */
 591 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
 592                                       unsigned int streams)
 593 {
 594         struct hdac_bus *bus = azx_dev->bus;
 595         struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
 596         struct hdac_stream *s;
 597         bool inited = false;
 598         u64 cycle_last = 0;
 599         int i = 0;
 600
 601         list_for_each_entry(s, &bus->stream_list, list) {
 602                 if (streams & (1 << i)) {
 603                         azx_timecounter_init(s, inited, cycle_last);
 604                         if (!inited) {
 605                                 inited = true;
 606                                 cycle_last = s->tc.cycle_last;
 607                         }
 608                 }
 609                 i++;
 610         }
 611
 612         snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
 613         runtime->trigger_tstamp_latched = true;
 614 }
 615 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
 616
 617 /**
 618  * snd_hdac_stream_sync_trigger - turn on/off stream sync register
 619  * @azx_dev: HD-audio core stream (master stream)
 620  * @streams: bit flags of streams to sync
 621  */
 622 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
 623                                   unsigned int streams, unsigned int reg)
 624 {
 625         struct hdac_bus *bus = azx_dev->bus;
 626         unsigned int val;
 627
 628         if (!reg)
 629                 reg = AZX_REG_SSYNC;
 630         val = _snd_hdac_chip_readl(bus, reg);
 631         if (set)
 632                 val |= streams;
 633         else
 634                 val &= ~streams;
 635         _snd_hdac_chip_writel(bus, reg, val);
 636 }
 637 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
 638
 639 /**
 640  * snd_hdac_stream_sync - sync with start/strop trigger operation
 641  * @azx_dev: HD-audio core stream (master stream)
 642  * @start: true = start, false = stop
 643  * @streams: bit flags of streams to sync
 644  *
 645  * For @start = true, wait until all FIFOs get ready.
 646  * For @start = false, wait until all RUN bits are cleared.
 647  */
 648 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
 649                           unsigned int streams)
 650 {
 651         struct hdac_bus *bus = azx_dev->bus;
 652         int i, nwait, timeout;
 653         struct hdac_stream *s;
 654
 655         for (timeout = 5000; timeout; timeout--) {
 656                 nwait = 0;
 657                 i = 0;
 658                 list_for_each_entry(s, &bus->stream_list, list) {
 659                         if (streams & (1 << i)) {
 660                                 if (start) {
 661                                         /* check FIFO gets ready */
 662                                         if (!(snd_hdac_stream_readb(s, SD_STS) &
 663                                               SD_STS_FIFO_READY))
 664                                                 nwait++;
 665                                 } else {
 666                                         /* check RUN bit is cleared */
 667                                         if (snd_hdac_stream_readb(s, SD_CTL) &
 668                                             SD_CTL_DMA_START)
 669                                                 nwait++;
 670                                 }
 671                         }
 672                         i++;
 673                 }
 674                 if (!nwait)
 675                         break;
 676                 cpu_relax();
 677         }
 678 }
 679 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
 680
 681 #ifdef CONFIG_SND_HDA_DSP_LOADER
 682 /**
 683  * snd_hdac_dsp_prepare - prepare for DSP loading
 684  * @azx_dev: HD-audio core stream used for DSP loading
 685  * @format: HD-audio stream format
 686  * @byte_size: data chunk byte size
 687  * @bufp: allocated buffer
 688  *
 689  * Allocate the buffer for the given size and set up the given stream for
 690  * DSP loading.  Returns the stream tag (>= 0), or a negative error code.
 691  */
 692 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
 693                          unsigned int byte_size, struct snd_dma_buffer *bufp)
 694 {
 695         struct hdac_bus *bus = azx_dev->bus;
 696         __le32 *bdl;
 697         int err;
 698
 699         snd_hdac_dsp_lock(azx_dev);
 700         spin_lock_irq(&bus->reg_lock);
 701         if (azx_dev->running || azx_dev->locked) {
 702                 spin_unlock_irq(&bus->reg_lock);
 703                 err = -EBUSY;
 704                 goto unlock;
 705         }
 706         azx_dev->locked = true;
 707         spin_unlock_irq(&bus->reg_lock);
 708
 709         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
 710                                   byte_size, bufp);
 711         if (err < 0)
 712                 goto err_alloc;
 713
 714         azx_dev->substream = NULL;
 715         azx_dev->bufsize = byte_size;
 716         azx_dev->period_bytes = byte_size;
 717         azx_dev->format_val = format;
 718
 719         snd_hdac_stream_reset(azx_dev);
 720
 721         /* reset BDL address */
 722         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 723         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 724
 725         azx_dev->frags = 0;
 726         bdl = (__le32 *)azx_dev->bdl.area;
 727         err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
 728         if (err < 0)
 729                 goto error;
 730
 731         snd_hdac_stream_setup(azx_dev);
 732         snd_hdac_dsp_unlock(azx_dev);
 733         return azx_dev->stream_tag;
 734
 735  error:
 736         snd_dma_free_pages(bufp);
 737  err_alloc:
 738         spin_lock_irq(&bus->reg_lock);
 739         azx_dev->locked = false;
 740         spin_unlock_irq(&bus->reg_lock);
 741  unlock:
 742         snd_hdac_dsp_unlock(azx_dev);
 743         return err;
 744 }
 745 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
 746
 747 /**
 748  * snd_hdac_dsp_trigger - start / stop DSP loading
 749  * @azx_dev: HD-audio core stream used for DSP loading
 750  * @start: trigger start or stop
 751  */
 752 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
 753 {
 754         if (start)
 755                 snd_hdac_stream_start(azx_dev, true);
 756         else
 757                 snd_hdac_stream_stop(azx_dev);
 758 }
 759 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
 760
 761 /**
 762  * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
 763  * @azx_dev: HD-audio core stream used for DSP loading
 764  * @dmab: buffer used by DSP loading
 765  */
 766 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
 767                           struct snd_dma_buffer *dmab)
 768 {
 769         struct hdac_bus *bus = azx_dev->bus;
 770
 771         if (!dmab->area || !azx_dev->locked)
 772                 return;
 773
 774         snd_hdac_dsp_lock(azx_dev);
 775         /* reset BDL address */
 776         snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
 777         snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
 778         snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
 779         azx_dev->bufsize = 0;
 780         azx_dev->period_bytes = 0;
 781         azx_dev->format_val = 0;
 782
 783         snd_dma_free_pages(dmab);
 784         dmab->area = NULL;
 785
 786         spin_lock_irq(&bus->reg_lock);
 787         azx_dev->locked = false;
 788         spin_unlock_irq(&bus->reg_lock);
 789         snd_hdac_dsp_unlock(azx_dev);
 790 }
 791 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
 792 #endif /* CONFIG_SND_HDA_DSP_LOADER */