sound/hda/hdac_controller.c

   1 /*
   2  * HD-audio controller helpers
   3  */
   4
   5 #include <linux/kernel.h>
   6 #include <linux/delay.h>
   7 #include <linux/export.h>
   8 #include <sound/core.h>
   9 #include <sound/hdaudio.h>
  10 #include <sound/hda_register.h>
  11
  12 /* clear CORB read pointer properly */
  13 static void azx_clear_corbrp(struct hdac_bus *bus)
  14 {
  15         int timeout;
  16
  17         for (timeout = 1000; timeout > 0; timeout--) {
  18                 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST)
  19                         break;
  20                 udelay(1);
  21         }
  22         if (timeout <= 0)
  23                 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n",
  24                         snd_hdac_chip_readw(bus, CORBRP));
  25
  26         snd_hdac_chip_writew(bus, CORBRP, 0);
  27         for (timeout = 1000; timeout > 0; timeout--) {
  28                 if (snd_hdac_chip_readw(bus, CORBRP) == 0)
  29                         break;
  30                 udelay(1);
  31         }
  32         if (timeout <= 0)
  33                 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n",
  34                         snd_hdac_chip_readw(bus, CORBRP));
  35 }
  36
  37 /**
  38  * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers
  39  * @bus: HD-audio core bus
  40  */
  41 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
  42 {
  43         WARN_ON_ONCE(!bus->rb.area);
  44
  45         spin_lock_irq(&bus->reg_lock);
  46         /* CORB set up */
  47         bus->corb.addr = bus->rb.addr;
  48         bus->corb.buf = (__le32 *)bus->rb.area;
  49         snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
  50         snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
  51
  52         /* set the corb size to 256 entries (ULI requires explicitly) */
  53         snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
  54         /* set the corb write pointer to 0 */
  55         snd_hdac_chip_writew(bus, CORBWP, 0);
  56
  57         /* reset the corb hw read pointer */
  58         snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST);
  59         if (!bus->corbrp_self_clear)
  60                 azx_clear_corbrp(bus);
  61
  62         /* enable corb dma */
  63         snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN);
  64
  65         /* RIRB set up */
  66         bus->rirb.addr = bus->rb.addr + 2048;
  67         bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
  68         bus->rirb.wp = bus->rirb.rp = 0;
  69         memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
  70         snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
  71         snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
  72
  73         /* set the rirb size to 256 entries (ULI requires explicitly) */
  74         snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
  75         /* reset the rirb hw write pointer */
  76         snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST);
  77         /* set N=1, get RIRB response interrupt for new entry */
  78         snd_hdac_chip_writew(bus, RINTCNT, 1);
  79         /* enable rirb dma and response irq */
  80         snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
  81         spin_unlock_irq(&bus->reg_lock);
  82 }
  83 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io);
  84
  85 /* wait for cmd dmas till they are stopped */
  86 static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus)
  87 {
  88         unsigned long timeout;
  89
  90         timeout = jiffies + msecs_to_jiffies(100);
  91         while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN)
  92                 && time_before(jiffies, timeout))
  93                 udelay(10);
  94
  95         timeout = jiffies + msecs_to_jiffies(100);
  96         while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN)
  97                 && time_before(jiffies, timeout))
  98                 udelay(10);
  99 }
 100
 101 /**
 102  * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers
 103  * @bus: HD-audio core bus
 104  */
 105 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus)
 106 {
 107         spin_lock_irq(&bus->reg_lock);
 108         /* disable ringbuffer DMAs */
 109         snd_hdac_chip_writeb(bus, RIRBCTL, 0);
 110         snd_hdac_chip_writeb(bus, CORBCTL, 0);
 111         spin_unlock_irq(&bus->reg_lock);
 112
 113         hdac_wait_for_cmd_dmas(bus);
 114
 115         spin_lock_irq(&bus->reg_lock);
 116         /* disable unsolicited responses */
 117         snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);
 118         spin_unlock_irq(&bus->reg_lock);
 119 }
 120 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io);
 121
 122 static unsigned int azx_command_addr(u32 cmd)
 123 {
 124         unsigned int addr = cmd >> 28;
 125
 126         if (snd_BUG_ON(addr >= HDA_MAX_CODECS))
 127                 addr = 0;
 128         return addr;
 129 }
 130
 131 /**
 132  * snd_hdac_bus_send_cmd - send a command verb via CORB
 133  * @bus: HD-audio core bus
 134  * @val: encoded verb value to send
 135  *
 136  * Returns zero for success or a negative error code.
 137  */
 138 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val)
 139 {
 140         unsigned int addr = azx_command_addr(val);
 141         unsigned int wp, rp;
 142
 143         spin_lock_irq(&bus->reg_lock);
 144
 145         bus->last_cmd[azx_command_addr(val)] = val;
 146
 147         /* add command to corb */
 148         wp = snd_hdac_chip_readw(bus, CORBWP);
 149         if (wp == 0xffff) {
 150                 /* something wrong, controller likely turned to D3 */
 151                 spin_unlock_irq(&bus->reg_lock);
 152                 return -EIO;
 153         }
 154         wp++;
 155         wp %= AZX_MAX_CORB_ENTRIES;
 156
 157         rp = snd_hdac_chip_readw(bus, CORBRP);
 158         if (wp == rp) {
 159                 /* oops, it's full */
 160                 spin_unlock_irq(&bus->reg_lock);
 161                 return -EAGAIN;
 162         }
 163
 164         bus->rirb.cmds[addr]++;
 165         bus->corb.buf[wp] = cpu_to_le32(val);
 166         snd_hdac_chip_writew(bus, CORBWP, wp);
 167
 168         spin_unlock_irq(&bus->reg_lock);
 169
 170         return 0;
 171 }
 172 EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd);
 173
 174 #define AZX_RIRB_EX_UNSOL_EV    (1<<4)
 175
 176 /**
 177  * snd_hdac_bus_update_rirb - retrieve RIRB entries
 178  * @bus: HD-audio core bus
 179  *
 180  * Usually called from interrupt handler.
 181  */
 182 void snd_hdac_bus_update_rirb(struct hdac_bus *bus)
 183 {
 184         unsigned int rp, wp;
 185         unsigned int addr;
 186         u32 res, res_ex;
 187
 188         wp = snd_hdac_chip_readw(bus, RIRBWP);
 189         if (wp == 0xffff) {
 190                 /* something wrong, controller likely turned to D3 */
 191                 return;
 192         }
 193
 194         if (wp == bus->rirb.wp)
 195                 return;
 196         bus->rirb.wp = wp;
 197
 198         while (bus->rirb.rp != wp) {
 199                 bus->rirb.rp++;
 200                 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
 201
 202                 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 203                 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]);
 204                 res = le32_to_cpu(bus->rirb.buf[rp]);
 205                 addr = res_ex & 0xf;
 206                 if (addr >= HDA_MAX_CODECS) {
 207                         dev_err(bus->dev,
 208                                 "spurious response %#x:%#x, rp = %d, wp = %d",
 209                                 res, res_ex, bus->rirb.rp, wp);
 210                         snd_BUG();
 211                 } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
 212                         snd_hdac_bus_queue_event(bus, res, res_ex);
 213                 else if (bus->rirb.cmds[addr]) {
 214                         bus->rirb.res[addr] = res;
 215                         bus->rirb.cmds[addr]--;
 216                 } else {
 217                         dev_err_ratelimited(bus->dev,
 218                                 "spurious response %#x:%#x, last cmd=%#08x\n",
 219                                 res, res_ex, bus->last_cmd[addr]);
 220                 }
 221         }
 222 }
 223 EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb);
 224
 225 /**
 226  * snd_hdac_bus_get_response - receive a response via RIRB
 227  * @bus: HD-audio core bus
 228  * @addr: codec address
 229  * @res: pointer to store the value, NULL when not needed
 230  *
 231  * Returns zero if a value is read, or a negative error code.
 232  */
 233 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
 234                               unsigned int *res)
 235 {
 236         unsigned long timeout;
 237         unsigned long loopcounter;
 238
 239         timeout = jiffies + msecs_to_jiffies(1000);
 240
 241         for (loopcounter = 0;; loopcounter++) {
 242                 spin_lock_irq(&bus->reg_lock);
 243                 if (!bus->rirb.cmds[addr]) {
 244                         if (res)
 245                                 *res = bus->rirb.res[addr]; /* the last value */
 246                         spin_unlock_irq(&bus->reg_lock);
 247                         return 0;
 248                 }
 249                 spin_unlock_irq(&bus->reg_lock);
 250                 if (time_after(jiffies, timeout))
 251                         break;
 252                 if (loopcounter > 3000)
 253                         msleep(2); /* temporary workaround */
 254                 else {
 255                         udelay(10);
 256                         cond_resched();
 257                 }
 258         }
 259
 260         return -EIO;
 261 }
 262 EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response);
 263
 264 #define HDAC_MAX_CAPS 10
 265 /**
 266  * snd_hdac_bus_parse_capabilities - parse capability structure
 267  * @bus: the pointer to bus object
 268  *
 269  * Returns 0 if successful, or a negative error code.
 270  */
 271 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus)
 272 {
 273         unsigned int cur_cap;
 274         unsigned int offset;
 275         unsigned int counter = 0;
 276
 277         offset = snd_hdac_chip_readl(bus, LLCH);
 278
 279         /* Lets walk the linked capabilities list */
 280         do {
 281                 cur_cap = _snd_hdac_chip_read(l, bus, offset);
 282
 283                 dev_dbg(bus->dev, "Capability version: 0x%x\n",
 284                         (cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF);
 285
 286                 dev_dbg(bus->dev, "HDA capability ID: 0x%x\n",
 287                         (cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF);
 288
 289                 if (cur_cap == -1) {
 290                         dev_dbg(bus->dev, "Invalid capability reg read\n");
 291                         break;
 292                 }
 293
 294                 switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) {
 295                 case AZX_ML_CAP_ID:
 296                         dev_dbg(bus->dev, "Found ML capability\n");
 297                         bus->mlcap = bus->remap_addr + offset;
 298                         break;
 299
 300                 case AZX_GTS_CAP_ID:
 301                         dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset);
 302                         bus->gtscap = bus->remap_addr + offset;
 303                         break;
 304
 305                 case AZX_PP_CAP_ID:
 306                         /* PP capability found, the Audio DSP is present */
 307                         dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset);
 308                         bus->ppcap = bus->remap_addr + offset;
 309                         break;
 310
 311                 case AZX_SPB_CAP_ID:
 312                         /* SPIB capability found, handler function */
 313                         dev_dbg(bus->dev, "Found SPB capability\n");
 314                         bus->spbcap = bus->remap_addr + offset;
 315                         break;
 316
 317                 case AZX_DRSM_CAP_ID:
 318                         /* DMA resume  capability found, handler function */
 319                         dev_dbg(bus->dev, "Found DRSM capability\n");
 320                         bus->drsmcap = bus->remap_addr + offset;
 321                         break;
 322
 323                 default:
 324                         dev_dbg(bus->dev, "Unknown capability %d\n", cur_cap);
 325                         break;
 326                 }
 327
 328                 counter++;
 329
 330                 if (counter > HDAC_MAX_CAPS) {
 331                         dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n");
 332                         break;
 333                 }
 334
 335                 /* read the offset of next capability */
 336                 offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK;
 337
 338         } while (offset);
 339
 340         return 0;
 341 }
 342 EXPORT_SYMBOL_GPL(snd_hdac_bus_parse_capabilities);
 343
 344 /*
 345  * Lowlevel interface
 346  */
 347
 348 /**
 349  * snd_hdac_bus_enter_link_reset - enter link reset
 350  * @bus: HD-audio core bus
 351  *
 352  * Enter to the link reset state.
 353  */
 354 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus)
 355 {
 356         unsigned long timeout;
 357
 358         /* reset controller */
 359         snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0);
 360
 361         timeout = jiffies + msecs_to_jiffies(100);
 362         while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) &&
 363                time_before(jiffies, timeout))
 364                 usleep_range(500, 1000);
 365 }
 366 EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset);
 367
 368 /**
 369  * snd_hdac_bus_exit_link_reset - exit link reset
 370  * @bus: HD-audio core bus
 371  *
 372  * Exit from the link reset state.
 373  */
 374 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus)
 375 {
 376         unsigned long timeout;
 377
 378         snd_hdac_chip_updateb(bus, GCTL, 0, AZX_GCTL_RESET);
 379
 380         timeout = jiffies + msecs_to_jiffies(100);
 381         while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout))
 382                 usleep_range(500, 1000);
 383 }
 384 EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset);
 385
 386 /* reset codec link */
 387 static int azx_reset(struct hdac_bus *bus, bool full_reset)
 388 {
 389         if (!full_reset)
 390                 goto skip_reset;
 391
 392         /* clear STATESTS if not in reset */
 393         if (snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET)
 394                 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
 395
 396         /* reset controller */
 397         snd_hdac_bus_enter_link_reset(bus);
 398
 399         /* delay for >= 100us for codec PLL to settle per spec
 400          * Rev 0.9 section 5.5.1
 401          */
 402         usleep_range(500, 1000);
 403
 404         /* Bring controller out of reset */
 405         snd_hdac_bus_exit_link_reset(bus);
 406
 407         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 408         usleep_range(1000, 1200);
 409
 410  skip_reset:
 411         /* check to see if controller is ready */
 412         if (!snd_hdac_chip_readb(bus, GCTL)) {
 413                 dev_dbg(bus->dev, "azx_reset: controller not ready!\n");
 414                 return -EBUSY;
 415         }
 416
 417         /* Accept unsolicited responses */
 418         snd_hdac_chip_updatel(bus, GCTL, 0, AZX_GCTL_UNSOL);
 419
 420         /* detect codecs */
 421         if (!bus->codec_mask) {
 422                 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
 423                 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
 424         }
 425
 426         return 0;
 427 }
 428
 429 /* enable interrupts */
 430 static void azx_int_enable(struct hdac_bus *bus)
 431 {
 432         /* enable controller CIE and GIE */
 433         snd_hdac_chip_updatel(bus, INTCTL, 0, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
 434 }
 435
 436 /* disable interrupts */
 437 static void azx_int_disable(struct hdac_bus *bus)
 438 {
 439         struct hdac_stream *azx_dev;
 440
 441         /* disable interrupts in stream descriptor */
 442         list_for_each_entry(azx_dev, &bus->stream_list, list)
 443                 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0);
 444
 445         /* disable SIE for all streams */
 446         snd_hdac_chip_writeb(bus, INTCTL, 0);
 447
 448         /* disable controller CIE and GIE */
 449         snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 0);
 450 }
 451
 452 /* clear interrupts */
 453 static void azx_int_clear(struct hdac_bus *bus)
 454 {
 455         struct hdac_stream *azx_dev;
 456
 457         /* clear stream status */
 458         list_for_each_entry(azx_dev, &bus->stream_list, list)
 459                 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
 460
 461         /* clear STATESTS */
 462         snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
 463
 464         /* clear rirb status */
 465         snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
 466
 467         /* clear int status */
 468         snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
 469 }
 470
 471 /**
 472  * snd_hdac_bus_init_chip - reset and start the controller registers
 473  * @bus: HD-audio core bus
 474  * @full_reset: Do full reset
 475  */
 476 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
 477 {
 478         if (bus->chip_init)
 479                 return false;
 480
 481         /* reset controller */
 482         azx_reset(bus, full_reset);
 483
 484         /* clear interrupts */
 485         azx_int_clear(bus);
 486
 487         /* initialize the codec command I/O */
 488         snd_hdac_bus_init_cmd_io(bus);
 489
 490         /* enable interrupts after CORB/RIRB buffers are initialized above */
 491         azx_int_enable(bus);
 492
 493         /* program the position buffer */
 494         if (bus->use_posbuf && bus->posbuf.addr) {
 495                 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
 496                 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
 497         }
 498
 499         bus->chip_init = true;
 500         return true;
 501 }
 502 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip);
 503
 504 /**
 505  * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os
 506  * @bus: HD-audio core bus
 507  */
 508 void snd_hdac_bus_stop_chip(struct hdac_bus *bus)
 509 {
 510         if (!bus->chip_init)
 511                 return;
 512
 513         /* disable interrupts */
 514         azx_int_disable(bus);
 515         azx_int_clear(bus);
 516
 517         /* disable CORB/RIRB */
 518         snd_hdac_bus_stop_cmd_io(bus);
 519
 520         /* disable position buffer */
 521         if (bus->posbuf.addr) {
 522                 snd_hdac_chip_writel(bus, DPLBASE, 0);
 523                 snd_hdac_chip_writel(bus, DPUBASE, 0);
 524         }
 525
 526         bus->chip_init = false;
 527 }
 528 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip);
 529
 530 /**
 531  * snd_hdac_bus_handle_stream_irq - interrupt handler for streams
 532  * @bus: HD-audio core bus
 533  * @status: INTSTS register value
 534  * @ask: callback to be called for woken streams
 535  *
 536  * Returns the bits of handled streams, or zero if no stream is handled.
 537  */
 538 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
 539                                     void (*ack)(struct hdac_bus *,
 540                                                 struct hdac_stream *))
 541 {
 542         struct hdac_stream *azx_dev;
 543         u8 sd_status;
 544         int handled = 0;
 545
 546         list_for_each_entry(azx_dev, &bus->stream_list, list) {
 547                 if (status & azx_dev->sd_int_sta_mask) {
 548                         sd_status = snd_hdac_stream_readb(azx_dev, SD_STS);
 549                         snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
 550                         handled |= 1 << azx_dev->index;
 551                         if (!azx_dev->substream || !azx_dev->running ||
 552                             !(sd_status & SD_INT_COMPLETE))
 553                                 continue;
 554                         if (ack)
 555                                 ack(bus, azx_dev);
 556                 }
 557         }
 558         return handled;
 559 }
 560 EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq);
 561
 562 /**
 563  * snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers
 564  * @bus: HD-audio core bus
 565  *
 566  * Call this after assigning the all streams.
 567  * Returns zero for success, or a negative error code.
 568  */
 569 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus)
 570 {
 571         struct hdac_stream *s;
 572         int num_streams = 0;
 573         int err;
 574
 575         list_for_each_entry(s, &bus->stream_list, list) {
 576                 /* allocate memory for the BDL for each stream */
 577                 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
 578                                                    BDL_SIZE, &s->bdl);
 579                 num_streams++;
 580                 if (err < 0)
 581                         return -ENOMEM;
 582         }
 583
 584         if (WARN_ON(!num_streams))
 585                 return -EINVAL;
 586         /* allocate memory for the position buffer */
 587         err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
 588                                            num_streams * 8, &bus->posbuf);
 589         if (err < 0)
 590                 return -ENOMEM;
 591         list_for_each_entry(s, &bus->stream_list, list)
 592                 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8);
 593
 594         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 595         return bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
 596                                             PAGE_SIZE, &bus->rb);
 597 }
 598 EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages);
 599
 600 /**
 601  * snd_hdac_bus_free_stream_pages - release BDL and other buffers
 602  * @bus: HD-audio core bus
 603  */
 604 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus)
 605 {
 606         struct hdac_stream *s;
 607
 608         list_for_each_entry(s, &bus->stream_list, list) {
 609                 if (s->bdl.area)
 610                         bus->io_ops->dma_free_pages(bus, &s->bdl);
 611         }
 612
 613         if (bus->rb.area)
 614                 bus->io_ops->dma_free_pages(bus, &bus->rb);
 615         if (bus->posbuf.area)
 616                 bus->io_ops->dma_free_pages(bus, &bus->posbuf);
 617 }
 618 EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages);