2 * HD-audio controller helpers
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/export.h>
8 #include <sound/core.h>
9 #include <sound/hdaudio.h>
10 #include <sound/hda_register.h>
12 /* clear CORB read pointer properly */
13 static void azx_clear_corbrp(struct hdac_bus *bus)
17 for (timeout = 1000; timeout > 0; timeout--) {
18 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST)
23 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n",
24 snd_hdac_chip_readw(bus, CORBRP));
26 snd_hdac_chip_writew(bus, CORBRP, 0);
27 for (timeout = 1000; timeout > 0; timeout--) {
28 if (snd_hdac_chip_readw(bus, CORBRP) == 0)
33 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n",
34 snd_hdac_chip_readw(bus, CORBRP));
38 * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers
39 * @bus: HD-audio core bus
41 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
43 WARN_ON_ONCE(!bus->rb.area);
45 spin_lock_irq(&bus->reg_lock);
47 bus->corb.addr = bus->rb.addr;
48 bus->corb.buf = (__le32 *)bus->rb.area;
49 snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
50 snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
52 /* set the corb size to 256 entries (ULI requires explicitly) */
53 snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
54 /* set the corb write pointer to 0 */
55 snd_hdac_chip_writew(bus, CORBWP, 0);
57 /* reset the corb hw read pointer */
58 snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST);
59 if (!bus->corbrp_self_clear)
60 azx_clear_corbrp(bus);
63 snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN);
66 bus->rirb.addr = bus->rb.addr + 2048;
67 bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
68 bus->rirb.wp = bus->rirb.rp = 0;
69 memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
70 snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
71 snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
73 /* set the rirb size to 256 entries (ULI requires explicitly) */
74 snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
75 /* reset the rirb hw write pointer */
76 snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST);
77 /* set N=1, get RIRB response interrupt for new entry */
78 snd_hdac_chip_writew(bus, RINTCNT, 1);
79 /* enable rirb dma and response irq */
80 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
81 spin_unlock_irq(&bus->reg_lock);
83 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io);
86 * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers
87 * @bus: HD-audio core bus
89 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus)
91 spin_lock_irq(&bus->reg_lock);
92 /* disable ringbuffer DMAs */
93 snd_hdac_chip_writeb(bus, RIRBCTL, 0);
94 snd_hdac_chip_writeb(bus, CORBCTL, 0);
95 /* disable unsolicited responses */
96 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);
97 spin_unlock_irq(&bus->reg_lock);
99 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io);
101 static unsigned int azx_command_addr(u32 cmd)
103 unsigned int addr = cmd >> 28;
105 if (snd_BUG_ON(addr >= HDA_MAX_CODECS))
111 * snd_hdac_bus_send_cmd - send a command verb via CORB
112 * @bus: HD-audio core bus
113 * @val: encoded verb value to send
115 * Returns zero for success or a negative error code.
117 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val)
119 unsigned int addr = azx_command_addr(val);
122 spin_lock_irq(&bus->reg_lock);
124 bus->last_cmd[azx_command_addr(val)] = val;
126 /* add command to corb */
127 wp = snd_hdac_chip_readw(bus, CORBWP);
129 /* something wrong, controller likely turned to D3 */
130 spin_unlock_irq(&bus->reg_lock);
134 wp %= AZX_MAX_CORB_ENTRIES;
136 rp = snd_hdac_chip_readw(bus, CORBRP);
138 /* oops, it's full */
139 spin_unlock_irq(&bus->reg_lock);
143 bus->rirb.cmds[addr]++;
144 bus->corb.buf[wp] = cpu_to_le32(val);
145 snd_hdac_chip_writew(bus, CORBWP, wp);
147 spin_unlock_irq(&bus->reg_lock);
151 EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd);
153 #define AZX_RIRB_EX_UNSOL_EV (1<<4)
156 * snd_hdac_bus_update_rirb - retrieve RIRB entries
157 * @bus: HD-audio core bus
159 * Usually called from interrupt handler.
161 void snd_hdac_bus_update_rirb(struct hdac_bus *bus)
167 wp = snd_hdac_chip_readw(bus, RIRBWP);
169 /* something wrong, controller likely turned to D3 */
173 if (wp == bus->rirb.wp)
177 while (bus->rirb.rp != wp) {
179 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
181 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */
182 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]);
183 res = le32_to_cpu(bus->rirb.buf[rp]);
185 if (addr >= HDA_MAX_CODECS) {
187 "spurious response %#x:%#x, rp = %d, wp = %d",
188 res, res_ex, bus->rirb.rp, wp);
190 } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
191 snd_hdac_bus_queue_event(bus, res, res_ex);
192 else if (bus->rirb.cmds[addr]) {
193 bus->rirb.res[addr] = res;
194 bus->rirb.cmds[addr]--;
196 dev_err_ratelimited(bus->dev,
197 "spurious response %#x:%#x, last cmd=%#08x\n",
198 res, res_ex, bus->last_cmd[addr]);
202 EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb);
205 * snd_hdac_bus_get_response - receive a response via RIRB
206 * @bus: HD-audio core bus
207 * @addr: codec address
208 * @res: pointer to store the value, NULL when not needed
210 * Returns zero if a value is read, or a negative error code.
212 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
215 unsigned long timeout;
216 unsigned long loopcounter;
218 timeout = jiffies + msecs_to_jiffies(1000);
220 for (loopcounter = 0;; loopcounter++) {
221 spin_lock_irq(&bus->reg_lock);
222 if (!bus->rirb.cmds[addr]) {
224 *res = bus->rirb.res[addr]; /* the last value */
225 spin_unlock_irq(&bus->reg_lock);
228 spin_unlock_irq(&bus->reg_lock);
229 if (time_after(jiffies, timeout))
231 if (loopcounter > 3000)
232 msleep(2); /* temporary workaround */
241 EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response);
248 * snd_hdac_bus_enter_link_reset - enter link reset
249 * @bus: HD-audio core bus
251 * Enter to the link reset state.
253 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus)
255 unsigned long timeout;
257 /* reset controller */
258 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0);
260 timeout = jiffies + msecs_to_jiffies(100);
261 while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) &&
262 time_before(jiffies, timeout))
263 usleep_range(500, 1000);
265 EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset);
268 * snd_hdac_bus_exit_link_reset - exit link reset
269 * @bus: HD-audio core bus
271 * Exit from the link reset state.
273 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus)
275 unsigned long timeout;
277 snd_hdac_chip_updateb(bus, GCTL, 0, AZX_GCTL_RESET);
279 timeout = jiffies + msecs_to_jiffies(100);
280 while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout))
281 usleep_range(500, 1000);
283 EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset);
285 /* reset codec link */
286 static int azx_reset(struct hdac_bus *bus, bool full_reset)
292 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
294 /* reset controller */
295 snd_hdac_bus_enter_link_reset(bus);
297 /* delay for >= 100us for codec PLL to settle per spec
298 * Rev 0.9 section 5.5.1
300 usleep_range(500, 1000);
302 /* Bring controller out of reset */
303 snd_hdac_bus_exit_link_reset(bus);
305 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
306 usleep_range(1000, 1200);
309 /* check to see if controller is ready */
310 if (!snd_hdac_chip_readb(bus, GCTL)) {
311 dev_dbg(bus->dev, "azx_reset: controller not ready!\n");
315 /* Accept unsolicited responses */
316 snd_hdac_chip_updatel(bus, GCTL, 0, AZX_GCTL_UNSOL);
319 if (!bus->codec_mask) {
320 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
321 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
327 /* enable interrupts */
328 static void azx_int_enable(struct hdac_bus *bus)
330 /* enable controller CIE and GIE */
331 snd_hdac_chip_updatel(bus, INTCTL, 0, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
334 /* disable interrupts */
335 static void azx_int_disable(struct hdac_bus *bus)
337 struct hdac_stream *azx_dev;
339 /* disable interrupts in stream descriptor */
340 list_for_each_entry(azx_dev, &bus->stream_list, list)
341 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0);
343 /* disable SIE for all streams */
344 snd_hdac_chip_writeb(bus, INTCTL, 0);
346 /* disable controller CIE and GIE */
347 snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 0);
350 /* clear interrupts */
351 static void azx_int_clear(struct hdac_bus *bus)
353 struct hdac_stream *azx_dev;
355 /* clear stream status */
356 list_for_each_entry(azx_dev, &bus->stream_list, list)
357 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
360 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
362 /* clear rirb status */
363 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
365 /* clear int status */
366 snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
370 * snd_hdac_bus_init_chip - reset and start the controller registers
371 * @bus: HD-audio core bus
372 * @full_reset: Do full reset
374 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
379 /* reset controller */
380 azx_reset(bus, full_reset);
382 /* clear interrupts */
385 /* initialize the codec command I/O */
386 snd_hdac_bus_init_cmd_io(bus);
388 /* enable interrupts after CORB/RIRB buffers are initialized above */
391 /* program the position buffer */
392 if (bus->use_posbuf && bus->posbuf.addr) {
393 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
394 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
397 bus->chip_init = true;
400 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip);
403 * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os
404 * @bus: HD-audio core bus
406 void snd_hdac_bus_stop_chip(struct hdac_bus *bus)
411 /* disable interrupts */
412 azx_int_disable(bus);
415 /* disable CORB/RIRB */
416 snd_hdac_bus_stop_cmd_io(bus);
418 /* disable position buffer */
419 if (bus->posbuf.addr) {
420 snd_hdac_chip_writel(bus, DPLBASE, 0);
421 snd_hdac_chip_writel(bus, DPUBASE, 0);
424 bus->chip_init = false;
426 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip);
429 * snd_hdac_bus_handle_stream_irq - interrupt handler for streams
430 * @bus: HD-audio core bus
431 * @status: INTSTS register value
432 * @ask: callback to be called for woken streams
434 void snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
435 void (*ack)(struct hdac_bus *,
436 struct hdac_stream *))
438 struct hdac_stream *azx_dev;
441 list_for_each_entry(azx_dev, &bus->stream_list, list) {
442 if (status & azx_dev->sd_int_sta_mask) {
443 sd_status = snd_hdac_stream_readb(azx_dev, SD_STS);
444 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
445 if (!azx_dev->substream || !azx_dev->running ||
446 !(sd_status & SD_INT_COMPLETE))
453 EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq);
456 * snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers
457 * @bus: HD-audio core bus
459 * Call this after assigning the all streams.
460 * Returns zero for success, or a negative error code.
462 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus)
464 struct hdac_stream *s;
468 list_for_each_entry(s, &bus->stream_list, list) {
469 /* allocate memory for the BDL for each stream */
470 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
477 if (WARN_ON(!num_streams))
479 /* allocate memory for the position buffer */
480 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
481 num_streams * 8, &bus->posbuf);
484 list_for_each_entry(s, &bus->stream_list, list)
485 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8);
487 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
488 return bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
489 PAGE_SIZE, &bus->rb);
491 EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages);
494 * snd_hdac_bus_free_stream_pages - release BDL and other buffers
495 * @bus: HD-audio core bus
497 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus)
499 struct hdac_stream *s;
501 list_for_each_entry(s, &bus->stream_list, list) {
503 bus->io_ops->dma_free_pages(bus, &s->bdl);
507 bus->io_ops->dma_free_pages(bus, &bus->rb);
508 if (bus->posbuf.area)
509 bus->io_ops->dma_free_pages(bus, &bus->posbuf);
511 EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages);