1 // SPDX-License-Identifier: GPL-2.0-only
3 * motu-protocol-v2.c - a part of driver for MOTU FireWire series
5 * Copyright (c) 2015-2017 Takashi Sakamoto <o-takashi@sakamocchi.jp>
10 #define V2_CLOCK_STATUS_OFFSET 0x0b14
11 #define V2_CLOCK_RATE_MASK 0x00000038
12 #define V2_CLOCK_RATE_SHIFT 3
13 #define V2_CLOCK_SRC_MASK 0x00000007
14 #define V2_CLOCK_SRC_SHIFT 0
15 #define V2_CLOCK_TRAVELER_FETCH_DISABLE 0x04000000
16 #define V2_CLOCK_TRAVELER_FETCH_ENABLE 0x03000000
17 #define V2_CLOCK_8PRE_FETCH_DISABLE 0x02000000
18 #define V2_CLOCK_8PRE_FETCH_ENABLE 0x00000000
20 #define V2_IN_OUT_CONF_OFFSET 0x0c04
21 #define V2_OPT_OUT_IFACE_MASK 0x00000c00
22 #define V2_OPT_OUT_IFACE_SHIFT 10
23 #define V2_OPT_IN_IFACE_MASK 0x00000300
24 #define V2_OPT_IN_IFACE_SHIFT 8
25 #define V2_OPT_IFACE_MODE_NONE 0
26 #define V2_OPT_IFACE_MODE_ADAT 1
27 #define V2_OPT_IFACE_MODE_SPDIF 2
29 static int v2_get_clock_rate(struct snd_motu *motu, unsigned int *rate)
35 err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
40 index = (be32_to_cpu(reg) & V2_CLOCK_RATE_MASK) >> V2_CLOCK_RATE_SHIFT;
41 if (index >= ARRAY_SIZE(snd_motu_clock_rates))
44 *rate = snd_motu_clock_rates[index];
49 static int v2_set_clock_rate(struct snd_motu *motu, unsigned int rate)
56 for (i = 0; i < ARRAY_SIZE(snd_motu_clock_rates); ++i) {
57 if (snd_motu_clock_rates[i] == rate)
60 if (i == ARRAY_SIZE(snd_motu_clock_rates))
63 err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
67 data = be32_to_cpu(reg);
69 data &= ~V2_CLOCK_RATE_MASK;
70 data |= i << V2_CLOCK_RATE_SHIFT;
72 if (motu->spec == &snd_motu_spec_traveler) {
73 data &= ~V2_CLOCK_TRAVELER_FETCH_ENABLE;
74 data |= V2_CLOCK_TRAVELER_FETCH_DISABLE;
77 reg = cpu_to_be32(data);
78 return snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET, ®,
82 static int v2_get_clock_source(struct snd_motu *motu,
83 enum snd_motu_clock_source *src)
89 err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET, ®,
94 index = be32_to_cpu(reg) & V2_CLOCK_SRC_MASK;
98 /* To check the configuration of optical interface. */
99 err = snd_motu_transaction_read(motu, V2_IN_OUT_CONF_OFFSET, ®,
106 *src = SND_MOTU_CLOCK_SOURCE_INTERNAL;
109 if (be32_to_cpu(reg) & 0x00000200)
110 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT;
112 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT;
115 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX;
118 *src = SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC;
121 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_DSUB;
130 static int v2_switch_fetching_mode(struct snd_motu *motu, bool enable)
136 if (motu->spec == &snd_motu_spec_traveler ||
137 motu->spec == &snd_motu_spec_8pre) {
138 err = snd_motu_transaction_read(motu, V2_CLOCK_STATUS_OFFSET,
142 data = be32_to_cpu(reg);
144 if (motu->spec == &snd_motu_spec_traveler) {
145 data &= ~(V2_CLOCK_TRAVELER_FETCH_DISABLE |
146 V2_CLOCK_TRAVELER_FETCH_ENABLE);
149 data |= V2_CLOCK_TRAVELER_FETCH_ENABLE;
151 data |= V2_CLOCK_TRAVELER_FETCH_DISABLE;
152 } else if (motu->spec == &snd_motu_spec_8pre) {
153 data &= ~(V2_CLOCK_8PRE_FETCH_DISABLE |
154 V2_CLOCK_8PRE_FETCH_ENABLE);
157 data |= V2_CLOCK_8PRE_FETCH_DISABLE;
159 data |= V2_CLOCK_8PRE_FETCH_ENABLE;
162 reg = cpu_to_be32(data);
163 err = snd_motu_transaction_write(motu, V2_CLOCK_STATUS_OFFSET,
170 static void calculate_fixed_part(struct snd_motu_packet_format *formats,
171 enum amdtp_stream_direction dir,
172 enum snd_motu_spec_flags flags,
173 unsigned char analog_ports)
175 unsigned char pcm_chunks[3] = {0, 0, 0};
177 formats->msg_chunks = 2;
179 pcm_chunks[0] = analog_ports;
180 pcm_chunks[1] = analog_ports;
181 if (flags & SND_MOTU_SPEC_SUPPORT_CLOCK_X4)
182 pcm_chunks[2] = analog_ports;
184 if (dir == AMDTP_IN_STREAM) {
185 if (flags & SND_MOTU_SPEC_TX_MICINST_CHUNK) {
189 if (flags & SND_MOTU_SPEC_TX_RETURN_CHUNK) {
194 if (flags & SND_MOTU_SPEC_RX_SEPARETED_MAIN) {
199 // Packets to v2 units include 2 chunks for phone 1/2, except
200 // for 176.4/192.0 kHz.
205 if (flags & SND_MOTU_SPEC_HAS_AESEBU_IFACE) {
211 * All of v2 models have a pair of coaxial interfaces for digital in/out
212 * port. At 44.1/48.0/88.2/96.0 kHz, packets includes PCM from these
218 formats->fixed_part_pcm_chunks[0] = pcm_chunks[0];
219 formats->fixed_part_pcm_chunks[1] = pcm_chunks[1];
220 formats->fixed_part_pcm_chunks[2] = pcm_chunks[2];
223 static void calculate_differed_part(struct snd_motu_packet_format *formats,
224 enum snd_motu_spec_flags flags,
225 u32 data, u32 mask, u32 shift)
227 unsigned char pcm_chunks[2] = {0, 0};
230 * When optical interfaces are configured for S/PDIF (TOSLINK),
231 * the above PCM frames come from them, instead of coaxial
234 data = (data & mask) >> shift;
235 if (data == V2_OPT_IFACE_MODE_ADAT) {
236 if (flags & SND_MOTU_SPEC_HAS_OPT_IFACE_A) {
240 // 8pre has two sets of optical interface and doesn't reduce
241 // chunks for ADAT signals.
242 if (flags & SND_MOTU_SPEC_HAS_OPT_IFACE_B) {
247 /* At mode x4, no data chunks are supported in this part. */
248 formats->differed_part_pcm_chunks[0] = pcm_chunks[0];
249 formats->differed_part_pcm_chunks[1] = pcm_chunks[1];
252 static int v2_cache_packet_formats(struct snd_motu *motu)
258 err = snd_motu_transaction_read(motu, V2_IN_OUT_CONF_OFFSET, ®,
262 data = be32_to_cpu(reg);
264 calculate_fixed_part(&motu->tx_packet_formats, AMDTP_IN_STREAM,
265 motu->spec->flags, motu->spec->analog_in_ports);
266 calculate_differed_part(&motu->tx_packet_formats, motu->spec->flags,
267 data, V2_OPT_IN_IFACE_MASK, V2_OPT_IN_IFACE_SHIFT);
269 calculate_fixed_part(&motu->rx_packet_formats, AMDTP_OUT_STREAM,
270 motu->spec->flags, motu->spec->analog_out_ports);
271 calculate_differed_part(&motu->rx_packet_formats, motu->spec->flags,
272 data, V2_OPT_OUT_IFACE_MASK, V2_OPT_OUT_IFACE_SHIFT);
274 motu->tx_packet_formats.pcm_byte_offset = 10;
275 motu->rx_packet_formats.pcm_byte_offset = 10;
280 const struct snd_motu_protocol snd_motu_protocol_v2 = {
281 .get_clock_rate = v2_get_clock_rate,
282 .set_clock_rate = v2_set_clock_rate,
283 .get_clock_source = v2_get_clock_source,
284 .switch_fetching_mode = v2_switch_fetching_mode,
285 .cache_packet_formats = v2_cache_packet_formats,