1 // SPDX-License-Identifier: GPL-2.0-only
3 // motu-protocol-v1.c - a part of driver for MOTU FireWire series
5 // Copyright (c) 2021 Takashi Sakamoto <o-takashi@sakamocchi.jp>
7 // Licensed under the terms of the GNU General Public License, version 2.
11 #include <linux/delay.h>
13 // Status register for MOTU 828 (0x'ffff'f000'0b00).
15 // 0xffff0000: ISOC_COMM_CONTROL_MASK in motu-stream.c.
16 // 0x00008000: mode of optical input interface.
17 // 0x00008000: for S/PDIF signal.
18 // 0x00000000: disabled or for ADAT signal.
19 // 0x00004000: mode of optical output interface.
20 // 0x00004000: for S/PDIF signal.
21 // 0x00000000: disabled or for ADAT signal.
22 // 0x00003f00: monitor input mode.
23 // 0x00000800: analog-1/2
24 // 0x00001a00: analog-3/4
25 // 0x00002c00: analog-5/6
26 // 0x00003e00: analog-7/8
27 // 0x00000000: analog-1
28 // 0x00000900: analog-2
29 // 0x00001200: analog-3
30 // 0x00001b00: analog-4
31 // 0x00002400: analog-5
32 // 0x00002d00: analog-6
33 // 0x00003600: analog-7
34 // 0x00003f00: analog-8
35 // 0x00000080: enable stream input.
36 // 0x00000040: disable monitor input.
37 // 0x00000008: enable main out.
38 // 0x00000004: rate of sampling clock.
39 // 0x00000004: 48.0 kHz
40 // 0x00000000: 44.1 kHz
41 // 0x00000023: source of sampling clock.
42 // 0x00000003: source packet header (SPH)
43 // 0x00000002: S/PDIF on optical/coaxial interface.
44 // 0x00000021: ADAT on optical interface
45 // 0x00000001: ADAT on Dsub 9pin
46 // 0x00000000: internal
48 #define CLK_828_STATUS_OFFSET 0x0b00
49 #define CLK_828_STATUS_MASK 0x0000ffff
50 #define CLK_828_STATUS_FLAG_OPT_IN_IFACE_IS_SPDIF 0x00008000
51 #define CLK_828_STATUS_FLAG_OPT_OUT_IFACE_IS_SPDIF 0x00004000
52 #define CLK_828_STATUS_FLAG_FETCH_PCM_FRAMES 0x00000080
53 #define CLK_828_STATUS_FLAG_ENABLE_OUTPUT 0x00000008
54 #define CLK_828_STATUS_FLAG_RATE_48000 0x00000004
55 #define CLK_828_STATUS_MASK_SRC 0x00000023
56 #define CLK_828_STATUS_FLAG_SRC_ADAT_ON_OPT 0x00000021
57 #define CLK_828_STATUS_FLAG_SRC_SPH 0x00000003
58 #define CLK_828_STATUS_FLAG_SRC_SPDIF 0x00000002
59 #define CLK_828_STATUS_FLAG_SRC_ADAT_ON_DSUB 0x00000001
60 #define CLK_828_STATUS_FLAG_SRC_INTERNAL 0x00000000
62 // Status register for MOTU 896 (0x'ffff'f000'0b14).
64 // 0xf0000000: enable physical and stream input to DAC.
65 // 0x80000000: disable
66 // 0x40000000: disable
67 // 0x20000000: enable (prior to the other bits)
68 // 0x10000000: disable
69 // 0x00000000: disable
70 // 0x08000000: speed of word clock signal output on BNC interface.
71 // 0x00000000: force to low rate (44.1/48.0 kHz).
72 // 0x08000000: follow to system clock.
73 // 0x04000000: something relevant to clock.
74 // 0x03000000: enable output.
75 // 0x02000000: enabled irreversibly once standing unless the device voluntarily disables it.
76 // 0x01000000: enabled irreversibly once standing unless the device voluntarily disables it.
77 // 0x00ffff00: monitor input mode.
78 // 0x00000000: disabled
79 // 0x00004800: analog-1/2
80 // 0x00005a00: analog-3/4
81 // 0x00006c00: analog-5/6
82 // 0x00007e00: analog-7/8
83 // 0x00104800: AES/EBU-1/2
84 // 0x00004000: analog-1
85 // 0x00004900: analog-2
86 // 0x00005200: analog-3
87 // 0x00005b00: analog-4
88 // 0x00006400: analog-5
89 // 0x00006d00: analog-6
90 // 0x00007600: analog-7
91 // 0x00007f00: analog-8
92 // 0x00104000: AES/EBU-1
93 // 0x00104900: AES/EBU-2
94 // 0x00000060: sample rate conversion for AES/EBU input/output.
96 // 0x00000020: input signal is converted to system rate
97 // 0x00000040: output is slave to input, ignoring system rate
98 // 0x00000060: output is double rate than system rate
99 // 0x00000018: nominal rate of sampling clock.
100 // 0x00000000: 44.1 kHz
101 // 0x00000008: 48.0 kHz
102 // 0x00000010: 88.2 kHz
103 // 0x00000018: 96.0 kHz
104 // 0x00000007: source of sampling clock.
105 // 0x00000000: internal
106 // 0x00000001: ADAT on optical interface
107 // 0x00000002: AES/EBU on XLR
108 // 0x00000003: source packet header (SPH)
109 // 0x00000004: word clock on BNC
110 // 0x00000005: ADAT on Dsub 9pin
112 #define CLK_896_STATUS_OFFSET 0x0b14
113 #define CLK_896_STATUS_FLAG_FETCH_ENABLE 0x20000000
114 #define CLK_896_STATUS_FLAG_OUTPUT_ON 0x03000000
115 #define CLK_896_STATUS_MASK_SRC 0x00000007
116 #define CLK_896_STATUS_FLAG_SRC_INTERNAL 0x00000000
117 #define CLK_896_STATUS_FLAG_SRC_ADAT_ON_OPT 0x00000001
118 #define CLK_896_STATUS_FLAG_SRC_AESEBU 0x00000002
119 #define CLK_896_STATUS_FLAG_SRC_SPH 0x00000003
120 #define CLK_896_STATUS_FLAG_SRC_WORD 0x00000004
121 #define CLK_896_STATUS_FLAG_SRC_ADAT_ON_DSUB 0x00000005
122 #define CLK_896_STATUS_MASK_RATE 0x00000018
123 #define CLK_896_STATUS_FLAG_RATE_44100 0x00000000
124 #define CLK_896_STATUS_FLAG_RATE_48000 0x00000008
125 #define CLK_896_STATUS_FLAG_RATE_88200 0x00000010
126 #define CLK_896_STATUS_FLAG_RATE_96000 0x00000018
128 static void parse_clock_rate_828(u32 data, unsigned int *rate)
130 if (data & CLK_828_STATUS_FLAG_RATE_48000)
136 static int get_clock_rate_828(struct snd_motu *motu, unsigned int *rate)
141 err = snd_motu_transaction_read(motu, CLK_828_STATUS_OFFSET, ®, sizeof(reg));
144 parse_clock_rate_828(be32_to_cpu(reg), rate);
149 static int parse_clock_rate_896(u32 data, unsigned int *rate)
151 switch (data & CLK_896_STATUS_MASK_RATE) {
152 case CLK_896_STATUS_FLAG_RATE_44100:
155 case CLK_896_STATUS_FLAG_RATE_48000:
158 case CLK_896_STATUS_FLAG_RATE_88200:
161 case CLK_896_STATUS_FLAG_RATE_96000:
171 static int get_clock_rate_896(struct snd_motu *motu, unsigned int *rate)
176 err = snd_motu_transaction_read(motu, CLK_896_STATUS_OFFSET, ®, sizeof(reg));
179 return parse_clock_rate_896(be32_to_cpu(reg), rate);
182 int snd_motu_protocol_v1_get_clock_rate(struct snd_motu *motu, unsigned int *rate)
184 if (motu->spec == &snd_motu_spec_828)
185 return get_clock_rate_828(motu, rate);
186 else if (motu->spec == &snd_motu_spec_896)
187 return get_clock_rate_896(motu, rate);
192 static int set_clock_rate_828(struct snd_motu *motu, unsigned int rate)
198 err = snd_motu_transaction_read(motu, CLK_828_STATUS_OFFSET, ®, sizeof(reg));
201 data = be32_to_cpu(reg) & CLK_828_STATUS_MASK;
203 data &= ~CLK_828_STATUS_FLAG_RATE_48000;
205 data |= CLK_828_STATUS_FLAG_RATE_48000;
207 reg = cpu_to_be32(data);
208 return snd_motu_transaction_write(motu, CLK_828_STATUS_OFFSET, ®, sizeof(reg));
211 static int set_clock_rate_896(struct snd_motu *motu, unsigned int rate)
218 err = snd_motu_transaction_read(motu, CLK_896_STATUS_OFFSET, ®, sizeof(reg));
221 data = be32_to_cpu(reg);
225 flag = CLK_896_STATUS_FLAG_RATE_44100;
228 flag = CLK_896_STATUS_FLAG_RATE_48000;
231 flag = CLK_896_STATUS_FLAG_RATE_88200;
234 flag = CLK_896_STATUS_FLAG_RATE_96000;
240 data &= ~CLK_896_STATUS_MASK_RATE;
243 reg = cpu_to_be32(data);
244 return snd_motu_transaction_write(motu, CLK_896_STATUS_OFFSET, ®, sizeof(reg));
247 int snd_motu_protocol_v1_set_clock_rate(struct snd_motu *motu, unsigned int rate)
249 if (motu->spec == &snd_motu_spec_828)
250 return set_clock_rate_828(motu, rate);
251 else if (motu->spec == &snd_motu_spec_896)
252 return set_clock_rate_896(motu, rate);
257 static int get_clock_source_828(struct snd_motu *motu, enum snd_motu_clock_source *src)
263 err = snd_motu_transaction_read(motu, CLK_828_STATUS_OFFSET, ®, sizeof(reg));
266 data = be32_to_cpu(reg) & CLK_828_STATUS_MASK;
268 switch (data & CLK_828_STATUS_MASK_SRC) {
269 case CLK_828_STATUS_FLAG_SRC_ADAT_ON_OPT:
270 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT;
272 case CLK_828_STATUS_FLAG_SRC_SPH:
273 *src = SND_MOTU_CLOCK_SOURCE_SPH;
275 case CLK_828_STATUS_FLAG_SRC_SPDIF:
277 if (data & CLK_828_STATUS_FLAG_OPT_IN_IFACE_IS_SPDIF)
278 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_COAX;
280 *src = SND_MOTU_CLOCK_SOURCE_SPDIF_ON_OPT;
283 case CLK_828_STATUS_FLAG_SRC_ADAT_ON_DSUB:
284 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_DSUB;
286 case CLK_828_STATUS_FLAG_SRC_INTERNAL:
287 *src = SND_MOTU_CLOCK_SOURCE_INTERNAL;
296 static int get_clock_source_896(struct snd_motu *motu, enum snd_motu_clock_source *src)
302 err = snd_motu_transaction_read(motu, CLK_896_STATUS_OFFSET, ®, sizeof(reg));
305 data = be32_to_cpu(reg);
307 switch (data & CLK_896_STATUS_MASK_SRC) {
308 case CLK_896_STATUS_FLAG_SRC_INTERNAL:
309 *src = SND_MOTU_CLOCK_SOURCE_INTERNAL;
311 case CLK_896_STATUS_FLAG_SRC_ADAT_ON_OPT:
312 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_OPT;
314 case CLK_896_STATUS_FLAG_SRC_AESEBU:
315 *src = SND_MOTU_CLOCK_SOURCE_AESEBU_ON_XLR;
317 case CLK_896_STATUS_FLAG_SRC_SPH:
318 *src = SND_MOTU_CLOCK_SOURCE_SPH;
320 case CLK_896_STATUS_FLAG_SRC_WORD:
321 *src = SND_MOTU_CLOCK_SOURCE_WORD_ON_BNC;
323 case CLK_896_STATUS_FLAG_SRC_ADAT_ON_DSUB:
324 *src = SND_MOTU_CLOCK_SOURCE_ADAT_ON_DSUB;
333 int snd_motu_protocol_v1_get_clock_source(struct snd_motu *motu, enum snd_motu_clock_source *src)
335 if (motu->spec == &snd_motu_spec_828)
336 return get_clock_source_828(motu, src);
337 else if (motu->spec == &snd_motu_spec_896)
338 return get_clock_source_896(motu, src);
343 static int switch_fetching_mode_828(struct snd_motu *motu, bool enable)
349 err = snd_motu_transaction_read(motu, CLK_828_STATUS_OFFSET, ®, sizeof(reg));
352 data = be32_to_cpu(reg) & CLK_828_STATUS_MASK;
354 data &= ~(CLK_828_STATUS_FLAG_FETCH_PCM_FRAMES | CLK_828_STATUS_FLAG_ENABLE_OUTPUT);
356 // This transaction should be initiated after the device receives batch of packets
357 // since the device voluntarily mutes outputs. As a workaround, yield processor over
360 data |= CLK_828_STATUS_FLAG_FETCH_PCM_FRAMES | CLK_828_STATUS_FLAG_ENABLE_OUTPUT;
363 reg = cpu_to_be32(data);
364 return snd_motu_transaction_write(motu, CLK_828_STATUS_OFFSET, ®, sizeof(reg));
367 static int switch_fetching_mode_896(struct snd_motu *motu, bool enable)
373 err = snd_motu_transaction_read(motu, CLK_896_STATUS_OFFSET, ®, sizeof(reg));
376 data = be32_to_cpu(reg);
378 data &= ~CLK_896_STATUS_FLAG_FETCH_ENABLE;
380 data |= CLK_896_STATUS_FLAG_FETCH_ENABLE | CLK_896_STATUS_FLAG_OUTPUT_ON;
382 reg = cpu_to_be32(data);
383 return snd_motu_transaction_write(motu, CLK_896_STATUS_OFFSET, ®, sizeof(reg));
386 int snd_motu_protocol_v1_switch_fetching_mode(struct snd_motu *motu, bool enable)
388 if (motu->spec == &snd_motu_spec_828)
389 return switch_fetching_mode_828(motu, enable);
390 else if (motu->spec == &snd_motu_spec_896)
391 return switch_fetching_mode_896(motu, enable);
396 static int detect_packet_formats_828(struct snd_motu *motu)
402 motu->tx_packet_formats.pcm_byte_offset = 4;
403 motu->tx_packet_formats.msg_chunks = 2;
405 motu->rx_packet_formats.pcm_byte_offset = 4;
406 motu->rx_packet_formats.msg_chunks = 0;
408 err = snd_motu_transaction_read(motu, CLK_828_STATUS_OFFSET, ®, sizeof(reg));
411 data = be32_to_cpu(reg) & CLK_828_STATUS_MASK;
413 // The number of chunks is just reduced when SPDIF is activated.
414 if (!(data & CLK_828_STATUS_FLAG_OPT_IN_IFACE_IS_SPDIF))
415 motu->tx_packet_formats.pcm_chunks[0] += 8;
417 if (!(data & CLK_828_STATUS_FLAG_OPT_OUT_IFACE_IS_SPDIF))
418 motu->rx_packet_formats.pcm_chunks[0] += 8;
423 static int detect_packet_formats_896(struct snd_motu *motu)
425 // 24bit PCM frames follow to source packet header without message chunk.
426 motu->tx_packet_formats.pcm_byte_offset = 4;
427 motu->rx_packet_formats.pcm_byte_offset = 4;
429 // No message chunk in data block.
430 motu->tx_packet_formats.msg_chunks = 0;
431 motu->rx_packet_formats.msg_chunks = 0;
433 // Always enable optical interface for ADAT signal since the device have no registers
434 // to refer to current configuration.
435 motu->tx_packet_formats.pcm_chunks[0] += 8;
436 motu->tx_packet_formats.pcm_chunks[1] += 8;
438 motu->rx_packet_formats.pcm_chunks[0] += 8;
439 motu->rx_packet_formats.pcm_chunks[1] += 8;
444 int snd_motu_protocol_v1_cache_packet_formats(struct snd_motu *motu)
446 memcpy(motu->tx_packet_formats.pcm_chunks, motu->spec->tx_fixed_pcm_chunks,
447 sizeof(motu->tx_packet_formats.pcm_chunks));
448 memcpy(motu->rx_packet_formats.pcm_chunks, motu->spec->rx_fixed_pcm_chunks,
449 sizeof(motu->rx_packet_formats.pcm_chunks));
451 if (motu->spec == &snd_motu_spec_828)
452 return detect_packet_formats_828(motu);
453 else if (motu->spec == &snd_motu_spec_896)
454 return detect_packet_formats_896(motu);
459 const struct snd_motu_spec snd_motu_spec_828 = {
461 .protocol_version = SND_MOTU_PROTOCOL_V1,
462 .tx_fixed_pcm_chunks = {10, 0, 0},
463 .rx_fixed_pcm_chunks = {10, 0, 0},
466 const struct snd_motu_spec snd_motu_spec_896 = {
468 .tx_fixed_pcm_chunks = {10, 10, 0},
469 .rx_fixed_pcm_chunks = {10, 10, 0},