sound/drivers/ml403-ac97cr.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * ALSA driver for Xilinx ML403 AC97 Controller Reference
   4  *   IP: opb_ac97_controller_ref_v1_00_a (EDK 8.1i)
   5  *   IP: opb_ac97_controller_ref_v1_00_a (EDK 9.1i)
   6  *
   7  *  Copyright (c) by 2007  Joachim Foerster <JOFT@gmx.de>
   8  */
   9
  10 /* Some notes / status of this driver:
  11  *
  12  * - Don't wonder about some strange implementations of things - especially the
  13  * (heavy) shadowing of codec registers, with which I tried to reduce read
  14  * accesses to a minimum, because after a variable amount of accesses, the AC97
  15  * controller doesn't raise the register access finished bit anymore ...
  16  *
  17  * - Playback support seems to be pretty stable - no issues here.
  18  * - Capture support "works" now, too. Overruns don't happen any longer so often.
  19  *   But there might still be some ...
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24
  25 #include <linux/platform_device.h>
  26
  27 #include <linux/ioport.h>
  28 #include <linux/slab.h>
  29 #include <linux/io.h>
  30 #include <linux/interrupt.h>
  31
  32 /* HZ */
  33 #include <linux/param.h>
  34 /* jiffies, time_*() */
  35 #include <linux/jiffies.h>
  36 /* schedule_timeout*() */
  37 #include <linux/sched.h>
  38 /* spin_lock*() */
  39 #include <linux/spinlock.h>
  40 /* struct mutex, mutex_init(), mutex_*lock() */
  41 #include <linux/mutex.h>
  42
  43 /* snd_printk(), snd_printd() */
  44 #include <sound/core.h>
  45 #include <sound/pcm.h>
  46 #include <sound/pcm_params.h>
  47 #include <sound/initval.h>
  48 #include <sound/ac97_codec.h>
  49
  50 #include "pcm-indirect2.h"
  51
  52
  53 #define SND_ML403_AC97CR_DRIVER "ml403-ac97cr"
  54
  55 MODULE_AUTHOR("Joachim Foerster <JOFT@gmx.de>");
  56 MODULE_DESCRIPTION("Xilinx ML403 AC97 Controller Reference");
  57 MODULE_LICENSE("GPL");
  58 MODULE_SUPPORTED_DEVICE("{{Xilinx,ML403 AC97 Controller Reference}}");
  59
  60 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  61 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  62 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE;
  63
  64 module_param_array(index, int, NULL, 0444);
  65 MODULE_PARM_DESC(index, "Index value for ML403 AC97 Controller Reference.");
  66 module_param_array(id, charp, NULL, 0444);
  67 MODULE_PARM_DESC(id, "ID string for ML403 AC97 Controller Reference.");
  68 module_param_array(enable, bool, NULL, 0444);
  69 MODULE_PARM_DESC(enable, "Enable this ML403 AC97 Controller Reference.");
  70
  71 /* Special feature options */
  72 /*#define CODEC_WRITE_CHECK_RAF*/ /* don't return after a write to a codec
  73                                    * register, while RAF bit is not set
  74                                    */
  75 /* Debug options for code which may be removed completely in a final version */
  76 #ifdef CONFIG_SND_DEBUG
  77 /*#define CODEC_STAT*/            /* turn on some minimal "statistics"
  78                                    * about codec register usage
  79                                    */
  80 #define SND_PCM_INDIRECT2_STAT    /* turn on some "statistics" about the
  81                                    * process of copying bytes from the
  82                                    * intermediate buffer to the hardware
  83                                    * fifo and the other way round
  84                                    */
  85 #endif
  86
  87 /* Definition of a "level/facility dependent" printk(); may be removed
  88  * completely in a final version
  89  */
  90 #undef PDEBUG
  91 #ifdef CONFIG_SND_DEBUG
  92 /* "facilities" for PDEBUG */
  93 #define UNKNOWN       (1<<0)
  94 #define CODEC_SUCCESS (1<<1)
  95 #define CODEC_FAKE    (1<<2)
  96 #define INIT_INFO     (1<<3)
  97 #define INIT_FAILURE  (1<<4)
  98 #define WORK_INFO     (1<<5)
  99 #define WORK_FAILURE  (1<<6)
 100
 101 #define PDEBUG_FACILITIES (UNKNOWN | INIT_FAILURE | WORK_FAILURE)
 102
 103 #define PDEBUG(fac, fmt, args...) do { \
 104                 if (fac & PDEBUG_FACILITIES) \
 105                         snd_printd(KERN_DEBUG SND_ML403_AC97CR_DRIVER ": " \
 106                                    fmt, ##args); \
 107         } while (0)
 108 #else
 109 #define PDEBUG(fac, fmt, args...) /* nothing */
 110 #endif
 111
 112
 113
 114 /* Defines for "waits"/timeouts (portions of HZ=250 on arch/ppc by default) */
 115 #define CODEC_TIMEOUT_ON_INIT       5   /* timeout for checking for codec
 116                                          * readiness (after insmod)
 117                                          */
 118 #ifndef CODEC_WRITE_CHECK_RAF
 119 #define CODEC_WAIT_AFTER_WRITE    100   /* general, static wait after a write
 120                                          * access to a codec register, may be
 121                                          * 0 to completely remove wait
 122                                          */
 123 #else
 124 #define CODEC_TIMEOUT_AFTER_WRITE   5   /* timeout after a write access to a
 125                                          * codec register, if RAF bit is used
 126                                          */
 127 #endif
 128 #define CODEC_TIMEOUT_AFTER_READ    5   /* timeout after a read access to a
 129                                          * codec register (checking RAF bit)
 130                                          */
 131
 132 /* Infrastructure for codec register shadowing */
 133 #define LM4550_REG_OK        (1<<0)   /* register exists */
 134 #define LM4550_REG_DONEREAD  (1<<1)   /* read register once, value should be
 135                                        * the same currently in the register
 136                                        */
 137 #define LM4550_REG_NOSAVE    (1<<2)   /* values written to this register will
 138                                        * not be saved in the register
 139                                        */
 140 #define LM4550_REG_NOSHADOW  (1<<3)   /* don't do register shadowing, use plain
 141                                        * hardware access
 142                                        */
 143 #define LM4550_REG_READONLY  (1<<4)   /* register is read only */
 144 #define LM4550_REG_FAKEPROBE (1<<5)   /* fake write _and_ read actions during
 145                                        * probe() correctly
 146                                        */
 147 #define LM4550_REG_FAKEREAD  (1<<6)   /* fake read access, always return
 148                                        * default value
 149                                        */
 150 #define LM4550_REG_ALLFAKE   (LM4550_REG_FAKEREAD | LM4550_REG_FAKEPROBE)
 151
 152 struct lm4550_reg {
 153         u16 value;
 154         u16 flag;
 155         u16 wmask;
 156         u16 def;
 157 };
 158
 159 struct lm4550_reg lm4550_regfile[64] = {
 160         [AC97_RESET / 2]              = {.flag = LM4550_REG_OK \
 161                                                 | LM4550_REG_NOSAVE \
 162                                                 | LM4550_REG_FAKEREAD,
 163                                          .def = 0x0D50},
 164         [AC97_MASTER / 2]             = {.flag = LM4550_REG_OK
 165                                                 | LM4550_REG_FAKEPROBE,
 166                                          .wmask = 0x9F1F,
 167                                          .def = 0x8000},
 168         [AC97_HEADPHONE / 2]          = {.flag = LM4550_REG_OK \
 169                                                 | LM4550_REG_FAKEPROBE,
 170                                          .wmask = 0x9F1F,
 171                                          .def = 0x8000},
 172         [AC97_MASTER_MONO / 2]        = {.flag = LM4550_REG_OK \
 173                                                 | LM4550_REG_FAKEPROBE,
 174                                          .wmask = 0x801F,
 175                                          .def = 0x8000},
 176         [AC97_PC_BEEP / 2]            = {.flag = LM4550_REG_OK \
 177                                                 | LM4550_REG_FAKEPROBE,
 178                                          .wmask = 0x801E,
 179                                          .def = 0x0},
 180         [AC97_PHONE / 2]              = {.flag = LM4550_REG_OK \
 181                                                 | LM4550_REG_FAKEPROBE,
 182                                          .wmask = 0x801F,
 183                                          .def = 0x8008},
 184         [AC97_MIC / 2]                = {.flag = LM4550_REG_OK \
 185                                                 | LM4550_REG_FAKEPROBE,
 186                                          .wmask = 0x805F,
 187                                          .def = 0x8008},
 188         [AC97_LINE / 2]               = {.flag = LM4550_REG_OK \
 189                                                 | LM4550_REG_FAKEPROBE,
 190                                          .wmask = 0x9F1F,
 191                                          .def = 0x8808},
 192         [AC97_CD / 2]                 = {.flag = LM4550_REG_OK \
 193                                                 | LM4550_REG_FAKEPROBE,
 194                                          .wmask = 0x9F1F,
 195                                          .def = 0x8808},
 196         [AC97_VIDEO / 2]              = {.flag = LM4550_REG_OK \
 197                                                 | LM4550_REG_FAKEPROBE,
 198                                          .wmask = 0x9F1F,
 199                                          .def = 0x8808},
 200         [AC97_AUX / 2]                = {.flag = LM4550_REG_OK \
 201                                                 | LM4550_REG_FAKEPROBE,
 202                                          .wmask = 0x9F1F,
 203                                          .def = 0x8808},
 204         [AC97_PCM / 2]                = {.flag = LM4550_REG_OK \
 205                                                 | LM4550_REG_FAKEPROBE,
 206                                          .wmask = 0x9F1F,
 207                                          .def = 0x8008},
 208         [AC97_REC_SEL / 2]            = {.flag = LM4550_REG_OK \
 209                                                 | LM4550_REG_FAKEPROBE,
 210                                          .wmask = 0x707,
 211                                          .def = 0x0},
 212         [AC97_REC_GAIN / 2]           = {.flag = LM4550_REG_OK \
 213                                                 | LM4550_REG_FAKEPROBE,
 214                                          .wmask = 0x8F0F,
 215                                          .def = 0x8000},
 216         [AC97_GENERAL_PURPOSE / 2]    = {.flag = LM4550_REG_OK \
 217                                                 | LM4550_REG_FAKEPROBE,
 218                                          .def = 0x0,
 219                                          .wmask = 0xA380},
 220         [AC97_3D_CONTROL / 2]         = {.flag = LM4550_REG_OK \
 221                                                 | LM4550_REG_FAKEREAD \
 222                                                 | LM4550_REG_READONLY,
 223                                          .def = 0x0101},
 224         [AC97_POWERDOWN / 2]          = {.flag = LM4550_REG_OK \
 225                                                 | LM4550_REG_NOSHADOW \
 226                                                 | LM4550_REG_NOSAVE,
 227                                          .wmask = 0xFF00},
 228                                         /* may not write ones to
 229                                          * REF/ANL/DAC/ADC bits
 230                                          * FIXME: Is this ok?
 231                                          */
 232         [AC97_EXTENDED_ID / 2]        = {.flag = LM4550_REG_OK \
 233                                                 | LM4550_REG_FAKEREAD \
 234                                                 | LM4550_REG_READONLY,
 235                                          .def = 0x0201}, /* primary codec */
 236         [AC97_EXTENDED_STATUS / 2]    = {.flag = LM4550_REG_OK \
 237                                                 | LM4550_REG_NOSHADOW \
 238                                                 | LM4550_REG_NOSAVE,
 239                                          .wmask = 0x1},
 240         [AC97_PCM_FRONT_DAC_RATE / 2] = {.flag = LM4550_REG_OK \
 241                                                 | LM4550_REG_FAKEPROBE,
 242                                          .def = 0xBB80,
 243                                          .wmask = 0xFFFF},
 244         [AC97_PCM_LR_ADC_RATE / 2]    = {.flag = LM4550_REG_OK \
 245                                                 | LM4550_REG_FAKEPROBE,
 246                                          .def = 0xBB80,
 247                                          .wmask = 0xFFFF},
 248         [AC97_VENDOR_ID1 / 2]         = {.flag = LM4550_REG_OK \
 249                                                 | LM4550_REG_READONLY \
 250                                                 | LM4550_REG_FAKEREAD,
 251                                          .def = 0x4E53},
 252         [AC97_VENDOR_ID2 / 2]         = {.flag = LM4550_REG_OK \
 253                                                 | LM4550_REG_READONLY \
 254                                                 | LM4550_REG_FAKEREAD,
 255                                          .def = 0x4350}
 256 };
 257
 258 #define LM4550_RF_OK(reg)    (lm4550_regfile[reg / 2].flag & LM4550_REG_OK)
 259
 260 static void lm4550_regfile_init(void)
 261 {
 262         int i;
 263         for (i = 0; i < 64; i++)
 264                 if (lm4550_regfile[i].flag & LM4550_REG_FAKEPROBE)
 265                         lm4550_regfile[i].value = lm4550_regfile[i].def;
 266 }
 267
 268 static void lm4550_regfile_write_values_after_init(struct snd_ac97 *ac97)
 269 {
 270         int i;
 271         for (i = 0; i < 64; i++)
 272                 if ((lm4550_regfile[i].flag & LM4550_REG_FAKEPROBE) &&
 273                     (lm4550_regfile[i].value != lm4550_regfile[i].def)) {
 274                         PDEBUG(CODEC_FAKE, "lm4550_regfile_write_values_after_"
 275                                "init(): reg=0x%x value=0x%x / %d is different "
 276                                "from def=0x%x / %d\n",
 277                                i, lm4550_regfile[i].value,
 278                                lm4550_regfile[i].value, lm4550_regfile[i].def,
 279                                lm4550_regfile[i].def);
 280                         snd_ac97_write(ac97, i * 2, lm4550_regfile[i].value);
 281                         lm4550_regfile[i].flag |= LM4550_REG_DONEREAD;
 282                 }
 283 }
 284
 285
 286 /* direct registers */
 287 #define CR_REG(ml403_ac97cr, x) ((ml403_ac97cr)->port + CR_REG_##x)
 288
 289 #define CR_REG_PLAYFIFO         0x00
 290 #define   CR_PLAYDATA(a)        ((a) & 0xFFFF)
 291
 292 #define CR_REG_RECFIFO          0x04
 293 #define   CR_RECDATA(a)         ((a) & 0xFFFF)
 294
 295 #define CR_REG_STATUS           0x08
 296 #define   CR_RECOVER            (1<<7)
 297 #define   CR_PLAYUNDER          (1<<6)
 298 #define   CR_CODECREADY         (1<<5)
 299 #define   CR_RAF                (1<<4)
 300 #define   CR_RECEMPTY           (1<<3)
 301 #define   CR_RECFULL            (1<<2)
 302 #define   CR_PLAYHALF           (1<<1)
 303 #define   CR_PLAYFULL           (1<<0)
 304
 305 #define CR_REG_RESETFIFO        0x0C
 306 #define   CR_RECRESET           (1<<1)
 307 #define   CR_PLAYRESET          (1<<0)
 308
 309 #define CR_REG_CODEC_ADDR       0x10
 310 /* UG082 says:
 311  * #define   CR_CODEC_ADDR(a)  ((a) << 1)
 312  * #define   CR_CODEC_READ     (1<<0)
 313  * #define   CR_CODEC_WRITE    (0<<0)
 314  */
 315 /* RefDesign example says: */
 316 #define   CR_CODEC_ADDR(a)      ((a) << 0)
 317 #define   CR_CODEC_READ         (1<<7)
 318 #define   CR_CODEC_WRITE        (0<<7)
 319
 320 #define CR_REG_CODEC_DATAREAD   0x14
 321 #define   CR_CODEC_DATAREAD(v)  ((v) & 0xFFFF)
 322
 323 #define CR_REG_CODEC_DATAWRITE  0x18
 324 #define   CR_CODEC_DATAWRITE(v) ((v) & 0xFFFF)
 325
 326 #define CR_FIFO_SIZE            32
 327
 328 struct snd_ml403_ac97cr {
 329         /* lock for access to (controller) registers */
 330         spinlock_t reg_lock;
 331         /* mutex for the whole sequence of accesses to (controller) registers
 332          * which affect codec registers
 333          */
 334         struct mutex cdc_mutex;
 335
 336         int irq; /* for playback */
 337         int enable_irq; /* for playback */
 338
 339         int capture_irq;
 340         int enable_capture_irq;
 341
 342         struct resource *res_port;
 343         void *port;
 344
 345         struct snd_ac97 *ac97;
 346         int ac97_fake;
 347 #ifdef CODEC_STAT
 348         int ac97_read;
 349         int ac97_write;
 350 #endif
 351
 352         struct platform_device *pfdev;
 353         struct snd_card *card;
 354         struct snd_pcm *pcm;
 355         struct snd_pcm_substream *playback_substream;
 356         struct snd_pcm_substream *capture_substream;
 357
 358         struct snd_pcm_indirect2 ind_rec; /* for playback */
 359         struct snd_pcm_indirect2 capture_ind2_rec;
 360 };
 361
 362 static const struct snd_pcm_hardware snd_ml403_ac97cr_playback = {
 363         .info =             (SNDRV_PCM_INFO_MMAP |
 364                              SNDRV_PCM_INFO_INTERLEAVED |
 365                              SNDRV_PCM_INFO_MMAP_VALID),
 366         .formats =          SNDRV_PCM_FMTBIT_S16_BE,
 367         .rates =            (SNDRV_PCM_RATE_CONTINUOUS |
 368                              SNDRV_PCM_RATE_8000_48000),
 369         .rate_min =         4000,
 370         .rate_max =         48000,
 371         .channels_min =     2,
 372         .channels_max =     2,
 373         .buffer_bytes_max = (128*1024),
 374         .period_bytes_min = CR_FIFO_SIZE/2,
 375         .period_bytes_max = (64*1024),
 376         .periods_min =      2,
 377         .periods_max =      (128*1024)/(CR_FIFO_SIZE/2),
 378         .fifo_size =        0,
 379 };
 380
 381 static const struct snd_pcm_hardware snd_ml403_ac97cr_capture = {
 382         .info =             (SNDRV_PCM_INFO_MMAP |
 383                              SNDRV_PCM_INFO_INTERLEAVED |
 384                              SNDRV_PCM_INFO_MMAP_VALID),
 385         .formats =          SNDRV_PCM_FMTBIT_S16_BE,
 386         .rates =            (SNDRV_PCM_RATE_CONTINUOUS |
 387                              SNDRV_PCM_RATE_8000_48000),
 388         .rate_min =         4000,
 389         .rate_max =         48000,
 390         .channels_min =     2,
 391         .channels_max =     2,
 392         .buffer_bytes_max = (128*1024),
 393         .period_bytes_min = CR_FIFO_SIZE/2,
 394         .period_bytes_max = (64*1024),
 395         .periods_min =      2,
 396         .periods_max =      (128*1024)/(CR_FIFO_SIZE/2),
 397         .fifo_size =        0,
 398 };
 399
 400 static size_t
 401 snd_ml403_ac97cr_playback_ind2_zero(struct snd_pcm_substream *substream,
 402                                     struct snd_pcm_indirect2 *rec)
 403 {
 404         struct snd_ml403_ac97cr *ml403_ac97cr;
 405         int copied_words = 0;
 406         u32 full = 0;
 407
 408         ml403_ac97cr = snd_pcm_substream_chip(substream);
 409
 410         spin_lock(&ml403_ac97cr->reg_lock);
 411         while ((full = (in_be32(CR_REG(ml403_ac97cr, STATUS)) &
 412                         CR_PLAYFULL)) != CR_PLAYFULL) {
 413                 out_be32(CR_REG(ml403_ac97cr, PLAYFIFO), 0);
 414                 copied_words++;
 415         }
 416         rec->hw_ready = 0;
 417         spin_unlock(&ml403_ac97cr->reg_lock);
 418
 419         return (size_t) (copied_words * 2);
 420 }
 421
 422 static size_t
 423 snd_ml403_ac97cr_playback_ind2_copy(struct snd_pcm_substream *substream,
 424                                     struct snd_pcm_indirect2 *rec,
 425                                     size_t bytes)
 426 {
 427         struct snd_ml403_ac97cr *ml403_ac97cr;
 428         u16 *src;
 429         int copied_words = 0;
 430         u32 full = 0;
 431
 432         ml403_ac97cr = snd_pcm_substream_chip(substream);
 433         src = (u16 *)(substream->runtime->dma_area + rec->sw_data);
 434
 435         spin_lock(&ml403_ac97cr->reg_lock);
 436         while (((full = (in_be32(CR_REG(ml403_ac97cr, STATUS)) &
 437                          CR_PLAYFULL)) != CR_PLAYFULL) && (bytes > 1)) {
 438                 out_be32(CR_REG(ml403_ac97cr, PLAYFIFO),
 439                          CR_PLAYDATA(src[copied_words]));
 440                 copied_words++;
 441                 bytes = bytes - 2;
 442         }
 443         if (full != CR_PLAYFULL)
 444                 rec->hw_ready = 1;
 445         else
 446                 rec->hw_ready = 0;
 447         spin_unlock(&ml403_ac97cr->reg_lock);
 448
 449         return (size_t) (copied_words * 2);
 450 }
 451
 452 static size_t
 453 snd_ml403_ac97cr_capture_ind2_null(struct snd_pcm_substream *substream,
 454                                    struct snd_pcm_indirect2 *rec)
 455 {
 456         struct snd_ml403_ac97cr *ml403_ac97cr;
 457         int copied_words = 0;
 458         u32 empty = 0;
 459
 460         ml403_ac97cr = snd_pcm_substream_chip(substream);
 461
 462         spin_lock(&ml403_ac97cr->reg_lock);
 463         while ((empty = (in_be32(CR_REG(ml403_ac97cr, STATUS)) &
 464                          CR_RECEMPTY)) != CR_RECEMPTY) {
 465                 volatile u32 trash;
 466
 467                 trash = CR_RECDATA(in_be32(CR_REG(ml403_ac97cr, RECFIFO)));
 468                 /* Hmmmm, really necessary? Don't want call to in_be32()
 469                  * to be optimised away!
 470                  */
 471                 trash++;
 472                 copied_words++;
 473         }
 474         rec->hw_ready = 0;
 475         spin_unlock(&ml403_ac97cr->reg_lock);
 476
 477         return (size_t) (copied_words * 2);
 478 }
 479
 480 static size_t
 481 snd_ml403_ac97cr_capture_ind2_copy(struct snd_pcm_substream *substream,
 482                                    struct snd_pcm_indirect2 *rec, size_t bytes)
 483 {
 484         struct snd_ml403_ac97cr *ml403_ac97cr;
 485         u16 *dst;
 486         int copied_words = 0;
 487         u32 empty = 0;
 488
 489         ml403_ac97cr = snd_pcm_substream_chip(substream);
 490         dst = (u16 *)(substream->runtime->dma_area + rec->sw_data);
 491
 492         spin_lock(&ml403_ac97cr->reg_lock);
 493         while (((empty = (in_be32(CR_REG(ml403_ac97cr, STATUS)) &
 494                           CR_RECEMPTY)) != CR_RECEMPTY) && (bytes > 1)) {
 495                 dst[copied_words] = CR_RECDATA(in_be32(CR_REG(ml403_ac97cr,
 496                                                               RECFIFO)));
 497                 copied_words++;
 498                 bytes = bytes - 2;
 499         }
 500         if (empty != CR_RECEMPTY)
 501                 rec->hw_ready = 1;
 502         else
 503                 rec->hw_ready = 0;
 504         spin_unlock(&ml403_ac97cr->reg_lock);
 505
 506         return (size_t) (copied_words * 2);
 507 }
 508
 509 static snd_pcm_uframes_t
 510 snd_ml403_ac97cr_pcm_pointer(struct snd_pcm_substream *substream)
 511 {
 512         struct snd_ml403_ac97cr *ml403_ac97cr;
 513         struct snd_pcm_indirect2 *ind2_rec = NULL;
 514
 515         ml403_ac97cr = snd_pcm_substream_chip(substream);
 516
 517         if (substream == ml403_ac97cr->playback_substream)
 518                 ind2_rec = &ml403_ac97cr->ind_rec;
 519         if (substream == ml403_ac97cr->capture_substream)
 520                 ind2_rec = &ml403_ac97cr->capture_ind2_rec;
 521
 522         if (ind2_rec != NULL)
 523                 return snd_pcm_indirect2_pointer(substream, ind2_rec);
 524         return (snd_pcm_uframes_t) 0;
 525 }
 526
 527 static int
 528 snd_ml403_ac97cr_pcm_playback_trigger(struct snd_pcm_substream *substream,
 529                                       int cmd)
 530 {
 531         struct snd_ml403_ac97cr *ml403_ac97cr;
 532         int err = 0;
 533
 534         ml403_ac97cr = snd_pcm_substream_chip(substream);
 535
 536         switch (cmd) {
 537         case SNDRV_PCM_TRIGGER_START:
 538                 PDEBUG(WORK_INFO, "trigger(playback): START\n");
 539                 ml403_ac97cr->ind_rec.hw_ready = 1;
 540
 541                 /* clear play FIFO */
 542                 out_be32(CR_REG(ml403_ac97cr, RESETFIFO), CR_PLAYRESET);
 543
 544                 /* enable play irq */
 545                 ml403_ac97cr->enable_irq = 1;
 546                 enable_irq(ml403_ac97cr->irq);
 547                 break;
 548         case SNDRV_PCM_TRIGGER_STOP:
 549                 PDEBUG(WORK_INFO, "trigger(playback): STOP\n");
 550                 ml403_ac97cr->ind_rec.hw_ready = 0;
 551 #ifdef SND_PCM_INDIRECT2_STAT
 552                 snd_pcm_indirect2_stat(substream, &ml403_ac97cr->ind_rec);
 553 #endif
 554                 /* disable play irq */
 555                 disable_irq_nosync(ml403_ac97cr->irq);
 556                 ml403_ac97cr->enable_irq = 0;
 557                 break;
 558         default:
 559                 err = -EINVAL;
 560                 break;
 561         }
 562         PDEBUG(WORK_INFO, "trigger(playback): (done)\n");
 563         return err;
 564 }
 565
 566 static int
 567 snd_ml403_ac97cr_pcm_capture_trigger(struct snd_pcm_substream *substream,
 568                                       int cmd)
 569 {
 570         struct snd_ml403_ac97cr *ml403_ac97cr;
 571         int err = 0;
 572
 573         ml403_ac97cr = snd_pcm_substream_chip(substream);
 574
 575         switch (cmd) {
 576         case SNDRV_PCM_TRIGGER_START:
 577                 PDEBUG(WORK_INFO, "trigger(capture): START\n");
 578                 ml403_ac97cr->capture_ind2_rec.hw_ready = 0;
 579
 580                 /* clear record FIFO */
 581                 out_be32(CR_REG(ml403_ac97cr, RESETFIFO), CR_RECRESET);
 582
 583                 /* enable record irq */
 584                 ml403_ac97cr->enable_capture_irq = 1;
 585                 enable_irq(ml403_ac97cr->capture_irq);
 586                 break;
 587         case SNDRV_PCM_TRIGGER_STOP:
 588                 PDEBUG(WORK_INFO, "trigger(capture): STOP\n");
 589                 ml403_ac97cr->capture_ind2_rec.hw_ready = 0;
 590 #ifdef SND_PCM_INDIRECT2_STAT
 591                 snd_pcm_indirect2_stat(substream,
 592                                        &ml403_ac97cr->capture_ind2_rec);
 593 #endif
 594                 /* disable capture irq */
 595                 disable_irq_nosync(ml403_ac97cr->capture_irq);
 596                 ml403_ac97cr->enable_capture_irq = 0;
 597                 break;
 598         default:
 599                 err = -EINVAL;
 600                 break;
 601         }
 602         PDEBUG(WORK_INFO, "trigger(capture): (done)\n");
 603         return err;
 604 }
 605
 606 static int
 607 snd_ml403_ac97cr_pcm_playback_prepare(struct snd_pcm_substream *substream)
 608 {
 609         struct snd_ml403_ac97cr *ml403_ac97cr;
 610         struct snd_pcm_runtime *runtime;
 611
 612         ml403_ac97cr = snd_pcm_substream_chip(substream);
 613         runtime = substream->runtime;
 614
 615         PDEBUG(WORK_INFO,
 616                "prepare(): period_bytes=%d, minperiod_bytes=%d\n",
 617                snd_pcm_lib_period_bytes(substream), CR_FIFO_SIZE / 2);
 618
 619         /* set sampling rate */
 620         snd_ac97_set_rate(ml403_ac97cr->ac97, AC97_PCM_FRONT_DAC_RATE,
 621                           runtime->rate);
 622         PDEBUG(WORK_INFO, "prepare(): rate=%d\n", runtime->rate);
 623
 624         /* init struct for intermediate buffer */
 625         memset(&ml403_ac97cr->ind_rec, 0,
 626                sizeof(struct snd_pcm_indirect2));
 627         ml403_ac97cr->ind_rec.hw_buffer_size = CR_FIFO_SIZE;
 628         ml403_ac97cr->ind_rec.sw_buffer_size =
 629                 snd_pcm_lib_buffer_bytes(substream);
 630         ml403_ac97cr->ind_rec.min_periods = -1;
 631         ml403_ac97cr->ind_rec.min_multiple =
 632                 snd_pcm_lib_period_bytes(substream) / (CR_FIFO_SIZE / 2);
 633         PDEBUG(WORK_INFO, "prepare(): hw_buffer_size=%d, "
 634                "sw_buffer_size=%d, min_multiple=%d\n",
 635                CR_FIFO_SIZE, ml403_ac97cr->ind_rec.sw_buffer_size,
 636                ml403_ac97cr->ind_rec.min_multiple);
 637         return 0;
 638 }
 639
 640 static int
 641 snd_ml403_ac97cr_pcm_capture_prepare(struct snd_pcm_substream *substream)
 642 {
 643         struct snd_ml403_ac97cr *ml403_ac97cr;
 644         struct snd_pcm_runtime *runtime;
 645
 646         ml403_ac97cr = snd_pcm_substream_chip(substream);
 647         runtime = substream->runtime;
 648
 649         PDEBUG(WORK_INFO,
 650                "prepare(capture): period_bytes=%d, minperiod_bytes=%d\n",
 651                snd_pcm_lib_period_bytes(substream), CR_FIFO_SIZE / 2);
 652
 653         /* set sampling rate */
 654         snd_ac97_set_rate(ml403_ac97cr->ac97, AC97_PCM_LR_ADC_RATE,
 655                           runtime->rate);
 656         PDEBUG(WORK_INFO, "prepare(capture): rate=%d\n", runtime->rate);
 657
 658         /* init struct for intermediate buffer */
 659         memset(&ml403_ac97cr->capture_ind2_rec, 0,
 660                sizeof(struct snd_pcm_indirect2));
 661         ml403_ac97cr->capture_ind2_rec.hw_buffer_size = CR_FIFO_SIZE;
 662         ml403_ac97cr->capture_ind2_rec.sw_buffer_size =
 663                 snd_pcm_lib_buffer_bytes(substream);
 664         ml403_ac97cr->capture_ind2_rec.min_multiple =
 665                 snd_pcm_lib_period_bytes(substream) / (CR_FIFO_SIZE / 2);
 666         PDEBUG(WORK_INFO, "prepare(capture): hw_buffer_size=%d, "
 667                "sw_buffer_size=%d, min_multiple=%d\n", CR_FIFO_SIZE,
 668                ml403_ac97cr->capture_ind2_rec.sw_buffer_size,
 669                ml403_ac97cr->capture_ind2_rec.min_multiple);
 670         return 0;
 671 }
 672
 673 static int snd_ml403_ac97cr_hw_free(struct snd_pcm_substream *substream)
 674 {
 675         PDEBUG(WORK_INFO, "hw_free()\n");
 676         return snd_pcm_lib_free_pages(substream);
 677 }
 678
 679 static int
 680 snd_ml403_ac97cr_hw_params(struct snd_pcm_substream *substream,
 681                            struct snd_pcm_hw_params *hw_params)
 682 {
 683         PDEBUG(WORK_INFO, "hw_params(): desired buffer bytes=%d, desired "
 684                "period bytes=%d\n",
 685                params_buffer_bytes(hw_params), params_period_bytes(hw_params));
 686         return snd_pcm_lib_malloc_pages(substream,
 687                                         params_buffer_bytes(hw_params));
 688 }
 689
 690 static int snd_ml403_ac97cr_playback_open(struct snd_pcm_substream *substream)
 691 {
 692         struct snd_ml403_ac97cr *ml403_ac97cr;
 693         struct snd_pcm_runtime *runtime;
 694
 695         ml403_ac97cr = snd_pcm_substream_chip(substream);
 696         runtime = substream->runtime;
 697
 698         PDEBUG(WORK_INFO, "open(playback)\n");
 699         ml403_ac97cr->playback_substream = substream;
 700         runtime->hw = snd_ml403_ac97cr_playback;
 701
 702         snd_pcm_hw_constraint_step(runtime, 0,
 703                                    SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
 704                                    CR_FIFO_SIZE / 2);
 705         return 0;
 706 }
 707
 708 static int snd_ml403_ac97cr_capture_open(struct snd_pcm_substream *substream)
 709 {
 710         struct snd_ml403_ac97cr *ml403_ac97cr;
 711         struct snd_pcm_runtime *runtime;
 712
 713         ml403_ac97cr = snd_pcm_substream_chip(substream);
 714         runtime = substream->runtime;
 715
 716         PDEBUG(WORK_INFO, "open(capture)\n");
 717         ml403_ac97cr->capture_substream = substream;
 718         runtime->hw = snd_ml403_ac97cr_capture;
 719
 720         snd_pcm_hw_constraint_step(runtime, 0,
 721                                    SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
 722                                    CR_FIFO_SIZE / 2);
 723         return 0;
 724 }
 725
 726 static int snd_ml403_ac97cr_playback_close(struct snd_pcm_substream *substream)
 727 {
 728         struct snd_ml403_ac97cr *ml403_ac97cr;
 729
 730         ml403_ac97cr = snd_pcm_substream_chip(substream);
 731
 732         PDEBUG(WORK_INFO, "close(playback)\n");
 733         ml403_ac97cr->playback_substream = NULL;
 734         return 0;
 735 }
 736
 737 static int snd_ml403_ac97cr_capture_close(struct snd_pcm_substream *substream)
 738 {
 739         struct snd_ml403_ac97cr *ml403_ac97cr;
 740
 741         ml403_ac97cr = snd_pcm_substream_chip(substream);
 742
 743         PDEBUG(WORK_INFO, "close(capture)\n");
 744         ml403_ac97cr->capture_substream = NULL;
 745         return 0;
 746 }
 747
 748 static const struct snd_pcm_ops snd_ml403_ac97cr_playback_ops = {
 749         .open = snd_ml403_ac97cr_playback_open,
 750         .close = snd_ml403_ac97cr_playback_close,
 751         .ioctl = snd_pcm_lib_ioctl,
 752         .hw_params = snd_ml403_ac97cr_hw_params,
 753         .hw_free = snd_ml403_ac97cr_hw_free,
 754         .prepare = snd_ml403_ac97cr_pcm_playback_prepare,
 755         .trigger = snd_ml403_ac97cr_pcm_playback_trigger,
 756         .pointer = snd_ml403_ac97cr_pcm_pointer,
 757 };
 758
 759 static const struct snd_pcm_ops snd_ml403_ac97cr_capture_ops = {
 760         .open = snd_ml403_ac97cr_capture_open,
 761         .close = snd_ml403_ac97cr_capture_close,
 762         .ioctl = snd_pcm_lib_ioctl,
 763         .hw_params = snd_ml403_ac97cr_hw_params,
 764         .hw_free = snd_ml403_ac97cr_hw_free,
 765         .prepare = snd_ml403_ac97cr_pcm_capture_prepare,
 766         .trigger = snd_ml403_ac97cr_pcm_capture_trigger,
 767         .pointer = snd_ml403_ac97cr_pcm_pointer,
 768 };
 769
 770 static irqreturn_t snd_ml403_ac97cr_irq(int irq, void *dev_id)
 771 {
 772         struct snd_ml403_ac97cr *ml403_ac97cr;
 773         struct platform_device *pfdev;
 774         int cmp_irq;
 775
 776         ml403_ac97cr = (struct snd_ml403_ac97cr *)dev_id;
 777         if (ml403_ac97cr == NULL)
 778                 return IRQ_NONE;
 779
 780         pfdev = ml403_ac97cr->pfdev;
 781
 782         /* playback interrupt */
 783         cmp_irq = platform_get_irq(pfdev, 0);
 784         if (irq == cmp_irq) {
 785                 if (ml403_ac97cr->enable_irq)
 786                         snd_pcm_indirect2_playback_interrupt(
 787                                 ml403_ac97cr->playback_substream,
 788                                 &ml403_ac97cr->ind_rec,
 789                                 snd_ml403_ac97cr_playback_ind2_copy,
 790                                 snd_ml403_ac97cr_playback_ind2_zero);
 791                 else
 792                         goto __disable_irq;
 793         } else {
 794                 /* record interrupt */
 795                 cmp_irq = platform_get_irq(pfdev, 1);
 796                 if (irq == cmp_irq) {
 797                         if (ml403_ac97cr->enable_capture_irq)
 798                                 snd_pcm_indirect2_capture_interrupt(
 799                                         ml403_ac97cr->capture_substream,
 800                                         &ml403_ac97cr->capture_ind2_rec,
 801                                         snd_ml403_ac97cr_capture_ind2_copy,
 802                                         snd_ml403_ac97cr_capture_ind2_null);
 803                         else
 804                                 goto __disable_irq;
 805                 } else
 806                         return IRQ_NONE;
 807         }
 808         return IRQ_HANDLED;
 809
 810 __disable_irq:
 811         PDEBUG(INIT_INFO, "irq(): irq %d is meant to be disabled! So, now try "
 812                "to disable it _really_!\n", irq);
 813         disable_irq_nosync(irq);
 814         return IRQ_HANDLED;
 815 }
 816
 817 static unsigned short
 818 snd_ml403_ac97cr_codec_read(struct snd_ac97 *ac97, unsigned short reg)
 819 {
 820         struct snd_ml403_ac97cr *ml403_ac97cr = ac97->private_data;
 821 #ifdef CODEC_STAT
 822         u32 stat;
 823         u32 rafaccess = 0;
 824 #endif
 825         unsigned long end_time;
 826         u16 value = 0;
 827
 828         if (!LM4550_RF_OK(reg)) {
 829                 snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
 830                            "access to unknown/unused codec register 0x%x "
 831                            "ignored!\n", reg);
 832                 return 0;
 833         }
 834         /* check if we can fake/answer this access from our shadow register */
 835         if ((lm4550_regfile[reg / 2].flag &
 836              (LM4550_REG_DONEREAD | LM4550_REG_ALLFAKE)) &&
 837             !(lm4550_regfile[reg / 2].flag & LM4550_REG_NOSHADOW)) {
 838                 if (lm4550_regfile[reg / 2].flag & LM4550_REG_FAKEREAD) {
 839                         PDEBUG(CODEC_FAKE, "codec_read(): faking read from "
 840                                "reg=0x%x, val=0x%x / %d\n",
 841                                reg, lm4550_regfile[reg / 2].def,
 842                                lm4550_regfile[reg / 2].def);
 843                         return lm4550_regfile[reg / 2].def;
 844                 } else if ((lm4550_regfile[reg / 2].flag &
 845                             LM4550_REG_FAKEPROBE) &&
 846                            ml403_ac97cr->ac97_fake) {
 847                         PDEBUG(CODEC_FAKE, "codec_read(): faking read from "
 848                                "reg=0x%x, val=0x%x / %d (probe)\n",
 849                                reg, lm4550_regfile[reg / 2].value,
 850                                lm4550_regfile[reg / 2].value);
 851                         return lm4550_regfile[reg / 2].value;
 852                 } else {
 853 #ifdef CODEC_STAT
 854                         PDEBUG(CODEC_FAKE, "codec_read(): read access "
 855                                "answered by shadow register 0x%x (value=0x%x "
 856                                "/ %d) (cw=%d cr=%d)\n",
 857                                reg, lm4550_regfile[reg / 2].value,
 858                                lm4550_regfile[reg / 2].value,
 859                                ml403_ac97cr->ac97_write,
 860                                ml403_ac97cr->ac97_read);
 861 #else
 862                         PDEBUG(CODEC_FAKE, "codec_read(): read access "
 863                                "answered by shadow register 0x%x (value=0x%x "
 864                                "/ %d)\n",
 865                                reg, lm4550_regfile[reg / 2].value,
 866                                lm4550_regfile[reg / 2].value);
 867 #endif
 868                         return lm4550_regfile[reg / 2].value;
 869                 }
 870         }
 871         /* if we are here, we _have_ to access the codec really, no faking */
 872         if (mutex_lock_interruptible(&ml403_ac97cr->cdc_mutex) != 0)
 873                 return 0;
 874 #ifdef CODEC_STAT
 875         ml403_ac97cr->ac97_read++;
 876 #endif
 877         spin_lock(&ml403_ac97cr->reg_lock);
 878         out_be32(CR_REG(ml403_ac97cr, CODEC_ADDR),
 879                  CR_CODEC_ADDR(reg) | CR_CODEC_READ);
 880         spin_unlock(&ml403_ac97cr->reg_lock);
 881         end_time = jiffies + (HZ / CODEC_TIMEOUT_AFTER_READ);
 882         do {
 883                 spin_lock(&ml403_ac97cr->reg_lock);
 884 #ifdef CODEC_STAT
 885                 rafaccess++;
 886                 stat = in_be32(CR_REG(ml403_ac97cr, STATUS));
 887                 if ((stat & CR_RAF) == CR_RAF) {
 888                         value = CR_CODEC_DATAREAD(
 889                                 in_be32(CR_REG(ml403_ac97cr, CODEC_DATAREAD)));
 890                         PDEBUG(CODEC_SUCCESS, "codec_read(): (done) reg=0x%x, "
 891                                "value=0x%x / %d (STATUS=0x%x)\n",
 892                                reg, value, value, stat);
 893 #else
 894                 if ((in_be32(CR_REG(ml403_ac97cr, STATUS)) &
 895                      CR_RAF) == CR_RAF) {
 896                         value = CR_CODEC_DATAREAD(
 897                                 in_be32(CR_REG(ml403_ac97cr, CODEC_DATAREAD)));
 898                         PDEBUG(CODEC_SUCCESS, "codec_read(): (done) "
 899                                "reg=0x%x, value=0x%x / %d\n",
 900                                reg, value, value);
 901 #endif
 902                         lm4550_regfile[reg / 2].value = value;
 903                         lm4550_regfile[reg / 2].flag |= LM4550_REG_DONEREAD;
 904                         spin_unlock(&ml403_ac97cr->reg_lock);
 905                         mutex_unlock(&ml403_ac97cr->cdc_mutex);
 906                         return value;
 907                 }
 908                 spin_unlock(&ml403_ac97cr->reg_lock);
 909                 schedule_timeout_uninterruptible(1);
 910         } while (time_after(end_time, jiffies));
 911         /* read the DATAREAD register anyway, see comment below */
 912         spin_lock(&ml403_ac97cr->reg_lock);
 913         value =
 914             CR_CODEC_DATAREAD(in_be32(CR_REG(ml403_ac97cr, CODEC_DATAREAD)));
 915         spin_unlock(&ml403_ac97cr->reg_lock);
 916 #ifdef CODEC_STAT
 917         snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
 918                    "timeout while codec read! "
 919                    "(reg=0x%x, last STATUS=0x%x, DATAREAD=0x%x / %d, %d) "
 920                    "(cw=%d, cr=%d)\n",
 921                    reg, stat, value, value, rafaccess,
 922                    ml403_ac97cr->ac97_write, ml403_ac97cr->ac97_read);
 923 #else
 924         snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
 925                    "timeout while codec read! "
 926                    "(reg=0x%x, DATAREAD=0x%x / %d)\n",
 927                    reg, value, value);
 928 #endif
 929         /* BUG: This is PURE speculation! But after _most_ read timeouts the
 930          * value in the register is ok!
 931          */
 932         lm4550_regfile[reg / 2].value = value;
 933         lm4550_regfile[reg / 2].flag |= LM4550_REG_DONEREAD;
 934         mutex_unlock(&ml403_ac97cr->cdc_mutex);
 935         return value;
 936 }
 937
 938 static void
 939 snd_ml403_ac97cr_codec_write(struct snd_ac97 *ac97, unsigned short reg,
 940                              unsigned short val)
 941 {
 942         struct snd_ml403_ac97cr *ml403_ac97cr = ac97->private_data;
 943
 944 #ifdef CODEC_STAT
 945         u32 stat;
 946         u32 rafaccess = 0;
 947 #endif
 948 #ifdef CODEC_WRITE_CHECK_RAF
 949         unsigned long end_time;
 950 #endif
 951
 952         if (!LM4550_RF_OK(reg)) {
 953                 snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
 954                            "access to unknown/unused codec register 0x%x "
 955                            "ignored!\n", reg);
 956                 return;
 957         }
 958         if (lm4550_regfile[reg / 2].flag & LM4550_REG_READONLY) {
 959                 snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
 960                            "write access to read only codec register 0x%x "
 961                            "ignored!\n", reg);
 962                 return;
 963         }
 964         if ((val & lm4550_regfile[reg / 2].wmask) != val) {
 965                 snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
 966                            "write access to codec register 0x%x "
 967                            "with bad value 0x%x / %d!\n",
 968                            reg, val, val);
 969                 val = val & lm4550_regfile[reg / 2].wmask;
 970         }
 971         if (((lm4550_regfile[reg / 2].flag & LM4550_REG_FAKEPROBE) &&
 972              ml403_ac97cr->ac97_fake) &&
 973             !(lm4550_regfile[reg / 2].flag & LM4550_REG_NOSHADOW)) {
 974                 PDEBUG(CODEC_FAKE, "codec_write(): faking write to reg=0x%x, "
 975                        "val=0x%x / %d\n", reg, val, val);
 976                 lm4550_regfile[reg / 2].value = (val &
 977                                                 lm4550_regfile[reg / 2].wmask);
 978                 return;
 979         }
 980         if (mutex_lock_interruptible(&ml403_ac97cr->cdc_mutex) != 0)
 981                 return;
 982 #ifdef CODEC_STAT
 983         ml403_ac97cr->ac97_write++;
 984 #endif
 985         spin_lock(&ml403_ac97cr->reg_lock);
 986         out_be32(CR_REG(ml403_ac97cr, CODEC_DATAWRITE),
 987                  CR_CODEC_DATAWRITE(val));
 988         out_be32(CR_REG(ml403_ac97cr, CODEC_ADDR),
 989                  CR_CODEC_ADDR(reg) | CR_CODEC_WRITE);
 990         spin_unlock(&ml403_ac97cr->reg_lock);
 991 #ifdef CODEC_WRITE_CHECK_RAF
 992         /* check CR_CODEC_RAF bit to see if write access to register is done;
 993          * loop until bit is set or timeout happens
 994          */
 995         end_time = jiffies + HZ / CODEC_TIMEOUT_AFTER_WRITE;
 996         do {
 997                 spin_lock(&ml403_ac97cr->reg_lock);
 998 #ifdef CODEC_STAT
 999                 rafaccess++;
1000                 stat = in_be32(CR_REG(ml403_ac97cr, STATUS))
1001                 if ((stat & CR_RAF) == CR_RAF) {
1002 #else
1003                 if ((in_be32(CR_REG(ml403_ac97cr, STATUS)) &
1004                      CR_RAF) == CR_RAF) {
1005 #endif
1006                         PDEBUG(CODEC_SUCCESS, "codec_write(): (done) "
1007                                "reg=0x%x, value=%d / 0x%x\n",
1008                                reg, val, val);
1009                         if (!(lm4550_regfile[reg / 2].flag &
1010                               LM4550_REG_NOSHADOW) &&
1011                             !(lm4550_regfile[reg / 2].flag &
1012                               LM4550_REG_NOSAVE))
1013                                 lm4550_regfile[reg / 2].value = val;
1014                         lm4550_regfile[reg / 2].flag |= LM4550_REG_DONEREAD;
1015                         spin_unlock(&ml403_ac97cr->reg_lock);
1016                         mutex_unlock(&ml403_ac97cr->cdc_mutex);
1017                         return;
1018                 }
1019                 spin_unlock(&ml403_ac97cr->reg_lock);
1020                 schedule_timeout_uninterruptible(1);
1021         } while (time_after(end_time, jiffies));
1022 #ifdef CODEC_STAT
1023         snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
1024                    "timeout while codec write "
1025                    "(reg=0x%x, val=0x%x / %d, last STATUS=0x%x, %d) "
1026                    "(cw=%d, cr=%d)\n",
1027                    reg, val, val, stat, rafaccess, ml403_ac97cr->ac97_write,
1028                    ml403_ac97cr->ac97_read);
1029 #else
1030         snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
1031                    "timeout while codec write (reg=0x%x, val=0x%x / %d)\n",
1032                    reg, val, val);
1033 #endif
1034 #else /* CODEC_WRITE_CHECK_RAF */
1035 #if CODEC_WAIT_AFTER_WRITE > 0
1036         /* officially, in AC97 spec there is no possibility for a AC97
1037          * controller to determine, if write access is done or not - so: How
1038          * is Xilinx able to provide a RAF bit for write access?
1039          * => very strange, thus just don't check RAF bit (compare with
1040          * Xilinx's example app in EDK 8.1i) and wait
1041          */
1042         schedule_timeout_uninterruptible(HZ / CODEC_WAIT_AFTER_WRITE);
1043 #endif
1044         PDEBUG(CODEC_SUCCESS, "codec_write(): (done) "
1045                "reg=0x%x, value=%d / 0x%x (no RAF check)\n",
1046                reg, val, val);
1047 #endif
1048         mutex_unlock(&ml403_ac97cr->cdc_mutex);
1049         return;
1050 }
1051
1052 static int
1053 snd_ml403_ac97cr_chip_init(struct snd_ml403_ac97cr *ml403_ac97cr)
1054 {
1055         unsigned long end_time;
1056         PDEBUG(INIT_INFO, "chip_init():\n");
1057         end_time = jiffies + HZ / CODEC_TIMEOUT_ON_INIT;
1058         do {
1059                 if (in_be32(CR_REG(ml403_ac97cr, STATUS)) & CR_CODECREADY) {
1060                         /* clear both hardware FIFOs */
1061                         out_be32(CR_REG(ml403_ac97cr, RESETFIFO),
1062                                  CR_RECRESET | CR_PLAYRESET);
1063                         PDEBUG(INIT_INFO, "chip_init(): (done)\n");
1064                         return 0;
1065                 }
1066                 schedule_timeout_uninterruptible(1);
1067         } while (time_after(end_time, jiffies));
1068         snd_printk(KERN_ERR SND_ML403_AC97CR_DRIVER ": "
1069                    "timeout while waiting for codec, "
1070                    "not ready!\n");
1071         return -EBUSY;
1072 }
1073
1074 static int snd_ml403_ac97cr_free(struct snd_ml403_ac97cr *ml403_ac97cr)
1075 {
1076         PDEBUG(INIT_INFO, "free():\n");
1077         /* irq release */
1078         if (ml403_ac97cr->irq >= 0)
1079                 free_irq(ml403_ac97cr->irq, ml403_ac97cr);
1080         if (ml403_ac97cr->capture_irq >= 0)
1081                 free_irq(ml403_ac97cr->capture_irq, ml403_ac97cr);
1082         /* give back "port" */
1083         iounmap(ml403_ac97cr->port);
1084         kfree(ml403_ac97cr);
1085         PDEBUG(INIT_INFO, "free(): (done)\n");
1086         return 0;
1087 }
1088
1089 static int snd_ml403_ac97cr_dev_free(struct snd_device *snddev)
1090 {
1091         struct snd_ml403_ac97cr *ml403_ac97cr = snddev->device_data;
1092         PDEBUG(INIT_INFO, "dev_free():\n");
1093         return snd_ml403_ac97cr_free(ml403_ac97cr);
1094 }
1095
1096 static int
1097 snd_ml403_ac97cr_create(struct snd_card *card, struct platform_device *pfdev,
1098                         struct snd_ml403_ac97cr **rml403_ac97cr)
1099 {
1100         struct snd_ml403_ac97cr *ml403_ac97cr;
1101         int err;
1102         static struct snd_device_ops ops = {
1103                 .dev_free = snd_ml403_ac97cr_dev_free,
1104         };
1105         struct resource *resource;
1106         int irq;
1107
1108         *rml403_ac97cr = NULL;
1109         ml403_ac97cr = kzalloc(sizeof(*ml403_ac97cr), GFP_KERNEL);
1110         if (ml403_ac97cr == NULL)
1111                 return -ENOMEM;
1112         spin_lock_init(&ml403_ac97cr->reg_lock);
1113         mutex_init(&ml403_ac97cr->cdc_mutex);
1114         ml403_ac97cr->card = card;
1115         ml403_ac97cr->pfdev = pfdev;
1116         ml403_ac97cr->irq = -1;
1117         ml403_ac97cr->enable_irq = 0;
1118         ml403_ac97cr->capture_irq = -1;
1119         ml403_ac97cr->enable_capture_irq = 0;
1120         ml403_ac97cr->port = NULL;
1121         ml403_ac97cr->res_port = NULL;
1122
1123         PDEBUG(INIT_INFO, "Trying to reserve resources now ...\n");
1124         resource = platform_get_resource(pfdev, IORESOURCE_MEM, 0);
1125         /* get "port" */
1126         ml403_ac97cr->port = ioremap_nocache(resource->start,
1127                                              (resource->end) -
1128                                              (resource->start) + 1);
1129         if (ml403_ac97cr->port == NULL) {
1130                 snd_printk(KERN_ERR SND_ML403_AC97CR_DRIVER ": "
1131                            "unable to remap memory region (%pR)\n",
1132                            resource);
1133                 snd_ml403_ac97cr_free(ml403_ac97cr);
1134                 return -EBUSY;
1135         }
1136         snd_printk(KERN_INFO SND_ML403_AC97CR_DRIVER ": "
1137                    "remap controller memory region to "
1138                    "0x%x done\n", (unsigned int)ml403_ac97cr->port);
1139         /* get irq */
1140         irq = platform_get_irq(pfdev, 0);
1141         if (request_irq(irq, snd_ml403_ac97cr_irq, 0,
1142                         dev_name(&pfdev->dev), (void *)ml403_ac97cr)) {
1143                 snd_printk(KERN_ERR SND_ML403_AC97CR_DRIVER ": "
1144                            "unable to grab IRQ %d\n",
1145                            irq);
1146                 snd_ml403_ac97cr_free(ml403_ac97cr);
1147                 return -EBUSY;
1148         }
1149         ml403_ac97cr->irq = irq;
1150         snd_printk(KERN_INFO SND_ML403_AC97CR_DRIVER ": "
1151                    "request (playback) irq %d done\n",
1152                    ml403_ac97cr->irq);
1153         irq = platform_get_irq(pfdev, 1);
1154         if (request_irq(irq, snd_ml403_ac97cr_irq, 0,
1155                         dev_name(&pfdev->dev), (void *)ml403_ac97cr)) {
1156                 snd_printk(KERN_ERR SND_ML403_AC97CR_DRIVER ": "
1157                            "unable to grab IRQ %d\n",
1158                            irq);
1159                 snd_ml403_ac97cr_free(ml403_ac97cr);
1160                 return -EBUSY;
1161         }
1162         ml403_ac97cr->capture_irq = irq;
1163         snd_printk(KERN_INFO SND_ML403_AC97CR_DRIVER ": "
1164                    "request (capture) irq %d done\n",
1165                    ml403_ac97cr->capture_irq);
1166
1167         err = snd_ml403_ac97cr_chip_init(ml403_ac97cr);
1168         if (err < 0) {
1169                 snd_ml403_ac97cr_free(ml403_ac97cr);
1170                 return err;
1171         }
1172
1173         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ml403_ac97cr, &ops);
1174         if (err < 0) {
1175                 PDEBUG(INIT_FAILURE, "probe(): snd_device_new() failed!\n");
1176                 snd_ml403_ac97cr_free(ml403_ac97cr);
1177                 return err;
1178         }
1179
1180         *rml403_ac97cr = ml403_ac97cr;
1181         return 0;
1182 }
1183
1184 static void snd_ml403_ac97cr_mixer_free(struct snd_ac97 *ac97)
1185 {
1186         struct snd_ml403_ac97cr *ml403_ac97cr = ac97->private_data;
1187         PDEBUG(INIT_INFO, "mixer_free():\n");
1188         ml403_ac97cr->ac97 = NULL;
1189         PDEBUG(INIT_INFO, "mixer_free(): (done)\n");
1190 }
1191
1192 static int
1193 snd_ml403_ac97cr_mixer(struct snd_ml403_ac97cr *ml403_ac97cr)
1194 {
1195         struct snd_ac97_bus *bus;
1196         struct snd_ac97_template ac97;
1197         int err;
1198         static struct snd_ac97_bus_ops ops = {
1199                 .write = snd_ml403_ac97cr_codec_write,
1200                 .read = snd_ml403_ac97cr_codec_read,
1201         };
1202         PDEBUG(INIT_INFO, "mixer():\n");
1203         err = snd_ac97_bus(ml403_ac97cr->card, 0, &ops, NULL, &bus);
1204         if (err < 0)
1205                 return err;
1206
1207         memset(&ac97, 0, sizeof(ac97));
1208         ml403_ac97cr->ac97_fake = 1;
1209         lm4550_regfile_init();
1210 #ifdef CODEC_STAT
1211         ml403_ac97cr->ac97_read = 0;
1212         ml403_ac97cr->ac97_write = 0;
1213 #endif
1214         ac97.private_data = ml403_ac97cr;
1215         ac97.private_free = snd_ml403_ac97cr_mixer_free;
1216         ac97.scaps = AC97_SCAP_AUDIO | AC97_SCAP_SKIP_MODEM |
1217             AC97_SCAP_NO_SPDIF;
1218         err = snd_ac97_mixer(bus, &ac97, &ml403_ac97cr->ac97);
1219         ml403_ac97cr->ac97_fake = 0;
1220         lm4550_regfile_write_values_after_init(ml403_ac97cr->ac97);
1221         PDEBUG(INIT_INFO, "mixer(): (done) snd_ac97_mixer()=%d\n", err);
1222         return err;
1223 }
1224
1225 static int
1226 snd_ml403_ac97cr_pcm(struct snd_ml403_ac97cr *ml403_ac97cr, int device)
1227 {
1228         struct snd_pcm *pcm;
1229         int err;
1230
1231         err = snd_pcm_new(ml403_ac97cr->card, "ML403AC97CR/1", device, 1, 1,
1232                           &pcm);
1233         if (err < 0)
1234                 return err;
1235         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1236                         &snd_ml403_ac97cr_playback_ops);
1237         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
1238                         &snd_ml403_ac97cr_capture_ops);
1239         pcm->private_data = ml403_ac97cr;
1240         pcm->info_flags = 0;
1241         strcpy(pcm->name, "ML403AC97CR DAC/ADC");
1242         ml403_ac97cr->pcm = pcm;
1243
1244         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1245                                           snd_dma_continuous_data(GFP_KERNEL),
1246                                           64 * 1024,
1247                                           128 * 1024);
1248         return 0;
1249 }
1250
1251 static int snd_ml403_ac97cr_probe(struct platform_device *pfdev)
1252 {
1253         struct snd_card *card;
1254         struct snd_ml403_ac97cr *ml403_ac97cr = NULL;
1255         int err;
1256         int dev = pfdev->id;
1257
1258         if (dev >= SNDRV_CARDS)
1259                 return -ENODEV;
1260         if (!enable[dev])
1261                 return -ENOENT;
1262
1263         err = snd_card_new(&pfdev->dev, index[dev], id[dev], THIS_MODULE,
1264                            0, &card);
1265         if (err < 0)
1266                 return err;
1267         err = snd_ml403_ac97cr_create(card, pfdev, &ml403_ac97cr);
1268         if (err < 0) {
1269                 PDEBUG(INIT_FAILURE, "probe(): create failed!\n");
1270                 snd_card_free(card);
1271                 return err;
1272         }
1273         PDEBUG(INIT_INFO, "probe(): create done\n");
1274         card->private_data = ml403_ac97cr;
1275         err = snd_ml403_ac97cr_mixer(ml403_ac97cr);
1276         if (err < 0) {
1277                 snd_card_free(card);
1278                 return err;
1279         }
1280         PDEBUG(INIT_INFO, "probe(): mixer done\n");
1281         err = snd_ml403_ac97cr_pcm(ml403_ac97cr, 0);
1282         if (err < 0) {
1283                 snd_card_free(card);
1284                 return err;
1285         }
1286         PDEBUG(INIT_INFO, "probe(): PCM done\n");
1287         strcpy(card->driver, SND_ML403_AC97CR_DRIVER);
1288         strcpy(card->shortname, "ML403 AC97 Controller Reference");
1289         sprintf(card->longname, "%s %s at 0x%lx, irq %i & %i, device %i",
1290                 card->shortname, card->driver,
1291                 (unsigned long)ml403_ac97cr->port, ml403_ac97cr->irq,
1292                 ml403_ac97cr->capture_irq, dev + 1);
1293
1294         err = snd_card_register(card);
1295         if (err < 0) {
1296                 snd_card_free(card);
1297                 return err;
1298         }
1299         platform_set_drvdata(pfdev, card);
1300         PDEBUG(INIT_INFO, "probe(): (done)\n");
1301         return 0;
1302 }
1303
1304 static int snd_ml403_ac97cr_remove(struct platform_device *pfdev)
1305 {
1306         snd_card_free(platform_get_drvdata(pfdev));
1307         return 0;
1308 }
1309
1310 /* work with hotplug and coldplug */
1311 MODULE_ALIAS("platform:" SND_ML403_AC97CR_DRIVER);
1312
1313 static struct platform_driver snd_ml403_ac97cr_driver = {
1314         .probe = snd_ml403_ac97cr_probe,
1315         .remove = snd_ml403_ac97cr_remove,
1316         .driver = {
1317                 .name = SND_ML403_AC97CR_DRIVER,
1318         },
1319 };
1320
1321 module_platform_driver(snd_ml403_ac97cr_driver);