2 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
5 * Author: Nicolas Pitre
6 * Created: Dec 02, 2004
7 * Copyright: MontaVista Software Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/interrupt.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/module.h>
21 #include <linux/gpio.h>
22 #include <linux/of_gpio.h>
24 #include <sound/pxa2xx-lib.h>
26 #include <mach/irqs.h>
27 #include <mach/regs-ac97.h>
28 #include <mach/audio.h>
30 static DEFINE_MUTEX(car_mutex);
31 static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
32 static volatile long gsr_bits;
33 static struct clk *ac97_clk;
34 static struct clk *ac97conf_clk;
35 static int reset_gpio;
37 extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);
42 * o Slot 12 read from modem space will hang controller.
43 * o CDONE, SDONE interrupt fails after any slot 12 IO.
45 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
46 * 1 jiffy timeout if interrupt never comes).
49 int pxa2xx_ac97_read(int slot, unsigned short reg)
52 volatile u32 *reg_addr;
57 mutex_lock(&car_mutex);
59 /* set up primary or secondary codec space */
60 if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
61 reg_addr = slot ? &SMC_REG_BASE : &PMC_REG_BASE;
63 reg_addr = slot ? &SAC_REG_BASE : &PAC_REG_BASE;
64 reg_addr += (reg >> 1);
66 /* start read access across the ac97 link */
67 GSR = GSR_CDONE | GSR_SDONE;
69 val = (*reg_addr & 0xffff);
70 if (reg == AC97_GPIO_STATUS)
72 if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
73 !((GSR | gsr_bits) & GSR_SDONE)) {
74 printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
75 __func__, reg, GSR | gsr_bits);
81 GSR = GSR_CDONE | GSR_SDONE;
83 val = (*reg_addr & 0xffff);
84 /* but we've just started another cycle... */
85 wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
87 out: mutex_unlock(&car_mutex);
90 EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
92 int pxa2xx_ac97_write(int slot, unsigned short reg, unsigned short val)
94 volatile u32 *reg_addr;
97 mutex_lock(&car_mutex);
99 /* set up primary or secondary codec space */
100 if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
101 reg_addr = slot ? &SMC_REG_BASE : &PMC_REG_BASE;
103 reg_addr = slot ? &SAC_REG_BASE : &PAC_REG_BASE;
104 reg_addr += (reg >> 1);
106 GSR = GSR_CDONE | GSR_SDONE;
109 if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
110 !((GSR | gsr_bits) & GSR_CDONE)) {
111 printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
112 __func__, reg, GSR | gsr_bits);
116 mutex_unlock(&car_mutex);
119 EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
122 static inline void pxa_ac97_warm_pxa25x(void)
129 static inline void pxa_ac97_cold_pxa25x(void)
131 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
132 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
141 static inline void pxa_ac97_warm_pxa27x(void)
145 /* warm reset broken on Bulverde, so manually keep AC97 reset high */
146 pxa27x_configure_ac97reset(reset_gpio, true);
149 pxa27x_configure_ac97reset(reset_gpio, false);
153 static inline void pxa_ac97_cold_pxa27x(void)
155 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
156 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
160 /* PXA27x Developers Manual section 13.5.2.2.1 */
161 clk_prepare_enable(ac97conf_clk);
163 clk_disable_unprepare(ac97conf_clk);
164 GCR = GCR_COLD_RST | GCR_WARM_RST;
169 static inline void pxa_ac97_warm_pxa3xx(void)
173 /* Can't use interrupts */
177 static inline void pxa_ac97_cold_pxa3xx(void)
179 /* Hold CLKBPB for 100us */
185 GCR &= GCR_COLD_RST; /* clear everything but nCRST */
186 GCR &= ~GCR_COLD_RST; /* then assert nCRST */
190 /* Can't use interrupts on PXA3xx */
191 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
193 GCR = GCR_WARM_RST | GCR_COLD_RST;
197 bool pxa2xx_ac97_try_warm_reset(void)
200 unsigned int timeout = 100;
204 pxa_ac97_warm_pxa25x();
209 pxa_ac97_warm_pxa27x();
214 pxa_ac97_warm_pxa3xx();
219 while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
222 gsr = GSR | gsr_bits;
223 if (!(gsr & (GSR_PCR | GSR_SCR))) {
224 printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
232 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
234 bool pxa2xx_ac97_try_cold_reset(void)
237 unsigned int timeout = 1000;
241 pxa_ac97_cold_pxa25x();
246 pxa_ac97_cold_pxa27x();
251 pxa_ac97_cold_pxa3xx();
256 while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
259 gsr = GSR | gsr_bits;
260 if (!(gsr & (GSR_PCR | GSR_SCR))) {
261 printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
269 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
272 void pxa2xx_ac97_finish_reset(void)
274 GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
275 GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
277 EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
279 static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
289 /* Although we don't use those we still need to clear them
290 since they tend to spuriously trigger when MMC is used
291 (hardware bug? go figure)... */
292 if (cpu_is_pxa27x()) {
305 int pxa2xx_ac97_hw_suspend(void)
307 GCR |= GCR_ACLINK_OFF;
308 clk_disable_unprepare(ac97_clk);
311 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
313 int pxa2xx_ac97_hw_resume(void)
315 clk_prepare_enable(ac97_clk);
318 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
321 int pxa2xx_ac97_hw_probe(struct platform_device *dev)
324 pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
327 switch (pdata->reset_gpio) {
330 reset_gpio = pdata->reset_gpio;
338 dev_err(&dev->dev, "Invalid reset GPIO %d\n",
341 } else if (!pdata && dev->dev.of_node) {
342 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
345 pdata->reset_gpio = of_get_named_gpio(dev->dev.of_node,
347 if (pdata->reset_gpio == -ENOENT)
348 pdata->reset_gpio = -1;
349 else if (pdata->reset_gpio < 0)
350 return pdata->reset_gpio;
351 reset_gpio = pdata->reset_gpio;
357 if (cpu_is_pxa27x()) {
359 * This gpio is needed for a work-around to a bug in the ac97
360 * controller during warm reset. The direction and level is set
361 * here so that it is an output driven high when switching from
362 * AC97_nRESET alt function to generic gpio.
364 ret = gpio_request_one(reset_gpio, GPIOF_OUT_INIT_HIGH,
365 "pxa27x ac97 reset");
367 pr_err("%s: gpio_request_one() failed: %d\n",
371 pxa27x_configure_ac97reset(reset_gpio, false);
373 ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
374 if (IS_ERR(ac97conf_clk)) {
375 ret = PTR_ERR(ac97conf_clk);
381 ac97_clk = clk_get(&dev->dev, "AC97CLK");
382 if (IS_ERR(ac97_clk)) {
383 ret = PTR_ERR(ac97_clk);
388 ret = clk_prepare_enable(ac97_clk);
392 ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
399 GCR |= GCR_ACLINK_OFF;
405 clk_put(ac97conf_clk);
411 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
413 void pxa2xx_ac97_hw_remove(struct platform_device *dev)
416 gpio_free(reset_gpio);
417 GCR |= GCR_ACLINK_OFF;
418 free_irq(IRQ_AC97, NULL);
420 clk_put(ac97conf_clk);
423 clk_disable_unprepare(ac97_clk);
427 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
429 MODULE_AUTHOR("Nicolas Pitre");
430 MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
431 MODULE_LICENSE("GPL");