1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
5 #include <linux/slab.h>
6 #include <linux/dma-mapping.h>
8 #include <linux/module.h>
10 #include <linux/of_platform.h>
11 #include <linux/pinctrl/consumer.h>
12 #include <linux/platform_device.h>
13 #include <linux/qcom-geni-se.h>
18 * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced
19 * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper
20 * controller. QUP Wrapper is designed to support various serial bus protocols
21 * like UART, SPI, I2C, I3C, etc.
25 * DOC: Hardware description
27 * GENI based QUP is a highly-flexible and programmable module for supporting
28 * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single
29 * QUP module can provide upto 8 serial interfaces, using its internal
30 * serial engines. The actual configuration is determined by the target
31 * platform configuration. The protocol supported by each interface is
32 * determined by the firmware loaded to the serial engine. Each SE consists
33 * of a DMA Engine and GENI sub modules which enable serial engines to
34 * support FIFO and DMA modes of operation.
37 * +-----------------------------------------+
39 * | +----------------------------+ |
40 * --QUP & SE Clocks--> | Serial Engine N | +-IO------>
41 * | | ... | | Interface
42 * <---Clock Perf.----+ +----+-----------------------+ | |
43 * State Interface | | Serial Engine 1 | | |
46 * <--------AHB-------> | | | |
50 * <------SE IRQ------+ +----------------------------+ |
52 * +-----------------------------------------+
54 * Figure 1: GENI based QUP Wrapper
56 * The GENI submodules include primary and secondary sequencers which are
57 * used to drive TX & RX operations. On serial interfaces that operate using
58 * master-slave model, primary sequencer drives both TX & RX operations. On
59 * serial interfaces that operate using peer-to-peer model, primary sequencer
60 * drives TX operation and secondary sequencer drives RX operation.
64 * DOC: Software description
66 * GENI SE Wrapper driver is structured into 2 parts:
68 * geni_wrapper represents QUP Wrapper controller. This part of the driver
69 * manages QUP Wrapper information such as hardware version, clock
70 * performance table that is common to all the internal serial engines.
72 * geni_se represents serial engine. This part of the driver manages serial
73 * engine information such as clocks, containing QUP Wrapper, etc. This part
74 * of driver also supports operations (eg. initialize the concerned serial
75 * engine, select between FIFO and DMA mode of operation etc.) that are
76 * common to all the serial engines and are independent of serial interfaces.
79 #define MAX_CLK_PERF_LEVEL 32
80 #define NUM_AHB_CLKS 2
83 * @struct geni_wrapper - Data structure to represent the QUP Wrapper Core
84 * @dev: Device pointer of the QUP wrapper core
85 * @base: Base address of this instance of QUP wrapper core
86 * @ahb_clks: Handle to the primary & secondary AHB clocks
91 struct clk_bulk_data ahb_clks[NUM_AHB_CLKS];
94 #define QUP_HW_VER_REG 0x4
96 /* Common SE registers */
97 #define GENI_INIT_CFG_REVISION 0x0
98 #define GENI_S_INIT_CFG_REVISION 0x4
99 #define GENI_OUTPUT_CTRL 0x24
100 #define GENI_CGC_CTRL 0x28
101 #define GENI_CLK_CTRL_RO 0x60
102 #define GENI_IF_DISABLE_RO 0x64
103 #define GENI_FW_S_REVISION_RO 0x6c
104 #define SE_GENI_BYTE_GRAN 0x254
105 #define SE_GENI_TX_PACKING_CFG0 0x260
106 #define SE_GENI_TX_PACKING_CFG1 0x264
107 #define SE_GENI_RX_PACKING_CFG0 0x284
108 #define SE_GENI_RX_PACKING_CFG1 0x288
109 #define SE_GENI_M_GP_LENGTH 0x910
110 #define SE_GENI_S_GP_LENGTH 0x914
111 #define SE_DMA_TX_PTR_L 0xc30
112 #define SE_DMA_TX_PTR_H 0xc34
113 #define SE_DMA_TX_ATTR 0xc38
114 #define SE_DMA_TX_LEN 0xc3c
115 #define SE_DMA_TX_IRQ_EN 0xc48
116 #define SE_DMA_TX_IRQ_EN_SET 0xc4c
117 #define SE_DMA_TX_IRQ_EN_CLR 0xc50
118 #define SE_DMA_TX_LEN_IN 0xc54
119 #define SE_DMA_TX_MAX_BURST 0xc5c
120 #define SE_DMA_RX_PTR_L 0xd30
121 #define SE_DMA_RX_PTR_H 0xd34
122 #define SE_DMA_RX_ATTR 0xd38
123 #define SE_DMA_RX_LEN 0xd3c
124 #define SE_DMA_RX_IRQ_EN 0xd48
125 #define SE_DMA_RX_IRQ_EN_SET 0xd4c
126 #define SE_DMA_RX_IRQ_EN_CLR 0xd50
127 #define SE_DMA_RX_LEN_IN 0xd54
128 #define SE_DMA_RX_MAX_BURST 0xd5c
129 #define SE_DMA_RX_FLUSH 0xd60
130 #define SE_GSI_EVENT_EN 0xe18
131 #define SE_IRQ_EN 0xe1c
132 #define SE_DMA_GENERAL_CFG 0xe30
134 /* GENI_OUTPUT_CTRL fields */
135 #define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0)
137 /* GENI_CGC_CTRL fields */
138 #define CFG_AHB_CLK_CGC_ON BIT(0)
139 #define CFG_AHB_WR_ACLK_CGC_ON BIT(1)
140 #define DATA_AHB_CLK_CGC_ON BIT(2)
141 #define SCLK_CGC_ON BIT(3)
142 #define TX_CLK_CGC_ON BIT(4)
143 #define RX_CLK_CGC_ON BIT(5)
144 #define EXT_CLK_CGC_ON BIT(6)
145 #define PROG_RAM_HCLK_OFF BIT(8)
146 #define PROG_RAM_SCLK_OFF BIT(9)
147 #define DEFAULT_CGC_EN GENMASK(6, 0)
149 /* SE_GSI_EVENT_EN fields */
150 #define DMA_RX_EVENT_EN BIT(0)
151 #define DMA_TX_EVENT_EN BIT(1)
152 #define GENI_M_EVENT_EN BIT(2)
153 #define GENI_S_EVENT_EN BIT(3)
155 /* SE_IRQ_EN fields */
156 #define DMA_RX_IRQ_EN BIT(0)
157 #define DMA_TX_IRQ_EN BIT(1)
158 #define GENI_M_IRQ_EN BIT(2)
159 #define GENI_S_IRQ_EN BIT(3)
161 /* SE_DMA_GENERAL_CFG */
162 #define DMA_RX_CLK_CGC_ON BIT(0)
163 #define DMA_TX_CLK_CGC_ON BIT(1)
164 #define DMA_AHB_SLV_CFG_ON BIT(2)
165 #define AHB_SEC_SLV_CLK_CGC_ON BIT(3)
166 #define DUMMY_RX_NON_BUFFERABLE BIT(4)
167 #define RX_DMA_ZERO_PADDING_EN BIT(5)
168 #define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6)
169 #define RX_DMA_IRQ_DELAY_SHFT 6
172 * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version
173 * @se: Pointer to the corresponding serial engine.
175 * Return: Hardware Version of the wrapper.
177 u32 geni_se_get_qup_hw_version(struct geni_se *se)
179 struct geni_wrapper *wrapper = se->wrapper;
181 return readl_relaxed(wrapper->base + QUP_HW_VER_REG);
183 EXPORT_SYMBOL(geni_se_get_qup_hw_version);
185 static void geni_se_io_set_mode(void __iomem *base)
189 val = readl_relaxed(base + SE_IRQ_EN);
190 val |= GENI_M_IRQ_EN | GENI_S_IRQ_EN;
191 val |= DMA_TX_IRQ_EN | DMA_RX_IRQ_EN;
192 writel_relaxed(val, base + SE_IRQ_EN);
194 val = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
195 val &= ~GENI_DMA_MODE_EN;
196 writel_relaxed(val, base + SE_GENI_DMA_MODE_EN);
198 writel_relaxed(0, base + SE_GSI_EVENT_EN);
201 static void geni_se_io_init(void __iomem *base)
205 val = readl_relaxed(base + GENI_CGC_CTRL);
206 val |= DEFAULT_CGC_EN;
207 writel_relaxed(val, base + GENI_CGC_CTRL);
209 val = readl_relaxed(base + SE_DMA_GENERAL_CFG);
210 val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON;
211 val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON;
212 writel_relaxed(val, base + SE_DMA_GENERAL_CFG);
214 writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL);
215 writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG);
219 * geni_se_init() - Initialize the GENI serial engine
220 * @se: Pointer to the concerned serial engine.
221 * @rx_wm: Receive watermark, in units of FIFO words.
222 * @rx_rfr_wm: Ready-for-receive watermark, in units of FIFO words.
224 * This function is used to initialize the GENI serial engine, configure
225 * receive watermark and ready-for-receive watermarks.
227 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr)
231 geni_se_io_init(se->base);
232 geni_se_io_set_mode(se->base);
234 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG);
235 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG);
237 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
238 val |= M_COMMON_GENI_M_IRQ_EN;
239 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
241 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
242 val |= S_COMMON_GENI_S_IRQ_EN;
243 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
245 EXPORT_SYMBOL(geni_se_init);
247 static void geni_se_select_fifo_mode(struct geni_se *se)
249 u32 proto = geni_se_read_proto(se);
252 writel_relaxed(0, se->base + SE_GSI_EVENT_EN);
253 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);
254 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);
255 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);
256 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);
257 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);
259 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
260 if (proto != GENI_SE_UART) {
261 val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN;
262 val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
264 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
266 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
267 if (proto != GENI_SE_UART)
268 val |= S_CMD_DONE_EN;
269 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
271 val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
272 val &= ~GENI_DMA_MODE_EN;
273 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
276 static void geni_se_select_dma_mode(struct geni_se *se)
278 u32 proto = geni_se_read_proto(se);
281 writel_relaxed(0, se->base + SE_GSI_EVENT_EN);
282 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);
283 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);
284 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);
285 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);
286 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);
288 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
289 if (proto != GENI_SE_UART) {
290 val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
291 val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
293 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
295 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
296 if (proto != GENI_SE_UART)
297 val &= ~S_CMD_DONE_EN;
298 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
300 val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
301 val |= GENI_DMA_MODE_EN;
302 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
306 * geni_se_select_mode() - Select the serial engine transfer mode
307 * @se: Pointer to the concerned serial engine.
308 * @mode: Transfer mode to be selected.
310 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode)
312 WARN_ON(mode != GENI_SE_FIFO && mode != GENI_SE_DMA);
316 geni_se_select_fifo_mode(se);
319 geni_se_select_dma_mode(se);
321 case GENI_SE_INVALID:
326 EXPORT_SYMBOL(geni_se_select_mode);
331 * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist
332 * of up to 4 operations, each operation represented by 4 configuration vectors
333 * of 10 bits programmed in GENI_TX_PACKING_CFG0 and GENI_TX_PACKING_CFG1 for
334 * TX FIFO and in GENI_RX_PACKING_CFG0 and GENI_RX_PACKING_CFG1 for RX FIFO.
335 * Refer to below examples for detailed bit-field description.
337 * Example 1: word_size = 7, packing_mode = 4 x 8, msb_to_lsb = 1
339 * +-----------+-------+-------+-------+-------+
340 * | | vec_0 | vec_1 | vec_2 | vec_3 |
341 * +-----------+-------+-------+-------+-------+
342 * | start | 0x6 | 0xe | 0x16 | 0x1e |
343 * | direction | 1 | 1 | 1 | 1 |
344 * | length | 6 | 6 | 6 | 6 |
345 * | stop | 0 | 0 | 0 | 1 |
346 * +-----------+-------+-------+-------+-------+
348 * Example 2: word_size = 15, packing_mode = 2 x 16, msb_to_lsb = 0
350 * +-----------+-------+-------+-------+-------+
351 * | | vec_0 | vec_1 | vec_2 | vec_3 |
352 * +-----------+-------+-------+-------+-------+
353 * | start | 0x0 | 0x8 | 0x10 | 0x18 |
354 * | direction | 0 | 0 | 0 | 0 |
355 * | length | 7 | 6 | 7 | 6 |
356 * | stop | 0 | 0 | 0 | 1 |
357 * +-----------+-------+-------+-------+-------+
359 * Example 3: word_size = 23, packing_mode = 1 x 32, msb_to_lsb = 1
361 * +-----------+-------+-------+-------+-------+
362 * | | vec_0 | vec_1 | vec_2 | vec_3 |
363 * +-----------+-------+-------+-------+-------+
364 * | start | 0x16 | 0xe | 0x6 | 0x0 |
365 * | direction | 1 | 1 | 1 | 1 |
366 * | length | 7 | 7 | 6 | 0 |
367 * | stop | 0 | 0 | 1 | 0 |
368 * +-----------+-------+-------+-------+-------+
372 #define NUM_PACKING_VECTORS 4
373 #define PACKING_START_SHIFT 5
374 #define PACKING_DIR_SHIFT 4
375 #define PACKING_LEN_SHIFT 1
376 #define PACKING_STOP_BIT BIT(0)
377 #define PACKING_VECTOR_SHIFT 10
379 * geni_se_config_packing() - Packing configuration of the serial engine
380 * @se: Pointer to the concerned serial engine
381 * @bpw: Bits of data per transfer word.
382 * @pack_words: Number of words per fifo element.
383 * @msb_to_lsb: Transfer from MSB to LSB or vice-versa.
384 * @tx_cfg: Flag to configure the TX Packing.
385 * @rx_cfg: Flag to configure the RX Packing.
387 * This function is used to configure the packing rules for the current
390 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
391 bool msb_to_lsb, bool tx_cfg, bool rx_cfg)
393 u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0};
396 int idx_start = msb_to_lsb ? bpw - 1 : 0;
398 int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE;
399 int ceil_bpw = ALIGN(bpw, BITS_PER_BYTE);
400 int iter = (ceil_bpw * pack_words) / BITS_PER_BYTE;
403 if (iter <= 0 || iter > NUM_PACKING_VECTORS)
406 for (i = 0; i < iter; i++) {
407 len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1;
408 cfg[i] = idx << PACKING_START_SHIFT;
409 cfg[i] |= msb_to_lsb << PACKING_DIR_SHIFT;
410 cfg[i] |= len << PACKING_LEN_SHIFT;
412 if (temp_bpw <= BITS_PER_BYTE) {
413 idx = ((i + 1) * BITS_PER_BYTE) + idx_start;
416 idx = idx + idx_delta;
417 temp_bpw = temp_bpw - BITS_PER_BYTE;
420 cfg[iter - 1] |= PACKING_STOP_BIT;
421 cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT);
422 cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT);
425 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0);
426 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1);
429 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0);
430 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1);
434 * Number of protocol words in each FIFO entry
435 * 0 - 4x8, four words in each entry, max word size of 8 bits
436 * 1 - 2x16, two words in each entry, max word size of 16 bits
437 * 2 - 1x32, one word in each entry, max word size of 32 bits
440 if (pack_words || bpw == 32)
441 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN);
443 EXPORT_SYMBOL(geni_se_config_packing);
445 static void geni_se_clks_off(struct geni_se *se)
447 struct geni_wrapper *wrapper = se->wrapper;
449 clk_disable_unprepare(se->clk);
450 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks),
455 * geni_se_resources_off() - Turn off resources associated with the serial
457 * @se: Pointer to the concerned serial engine.
459 * Return: 0 on success, standard Linux error codes on failure/error.
461 int geni_se_resources_off(struct geni_se *se)
465 ret = pinctrl_pm_select_sleep_state(se->dev);
469 geni_se_clks_off(se);
472 EXPORT_SYMBOL(geni_se_resources_off);
474 static int geni_se_clks_on(struct geni_se *se)
477 struct geni_wrapper *wrapper = se->wrapper;
479 ret = clk_bulk_prepare_enable(ARRAY_SIZE(wrapper->ahb_clks),
484 ret = clk_prepare_enable(se->clk);
486 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks),
492 * geni_se_resources_on() - Turn on resources associated with the serial
494 * @se: Pointer to the concerned serial engine.
496 * Return: 0 on success, standard Linux error codes on failure/error.
498 int geni_se_resources_on(struct geni_se *se)
502 ret = geni_se_clks_on(se);
506 ret = pinctrl_pm_select_default_state(se->dev);
508 geni_se_clks_off(se);
512 EXPORT_SYMBOL(geni_se_resources_on);
515 * geni_se_clk_tbl_get() - Get the clock table to program DFS
516 * @se: Pointer to the concerned serial engine.
517 * @tbl: Table in which the output is returned.
519 * This function is called by the protocol drivers to determine the different
520 * clock frequencies supported by serial engine core clock. The protocol
521 * drivers use the output to determine the clock frequency index to be
522 * programmed into DFS.
524 * Return: number of valid performance levels in the table on success,
525 * standard Linux error codes on failure.
527 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl)
532 if (se->clk_perf_tbl) {
533 *tbl = se->clk_perf_tbl;
534 return se->num_clk_levels;
537 se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL,
538 sizeof(*se->clk_perf_tbl),
540 if (!se->clk_perf_tbl)
543 for (i = 0; i < MAX_CLK_PERF_LEVEL; i++) {
544 freq = clk_round_rate(se->clk, freq + 1);
545 if (freq <= 0 || freq == se->clk_perf_tbl[i - 1])
547 se->clk_perf_tbl[i] = freq;
549 se->num_clk_levels = i;
550 *tbl = se->clk_perf_tbl;
551 return se->num_clk_levels;
553 EXPORT_SYMBOL(geni_se_clk_tbl_get);
556 * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency
557 * @se: Pointer to the concerned serial engine.
558 * @req_freq: Requested clock frequency.
559 * @index: Index of the resultant frequency in the table.
560 * @res_freq: Resultant frequency of the source clock.
561 * @exact: Flag to indicate exact multiple requirement of the requested
564 * This function is called by the protocol drivers to determine the best match
565 * of the requested frequency as provided by the serial engine clock in order
566 * to meet the performance requirements.
568 * If we return success:
569 * - if @exact is true then @res_freq / <an_integer> == @req_freq
570 * - if @exact is false then @res_freq / <an_integer> <= @req_freq
572 * Return: 0 on success, standard Linux error codes on failure.
574 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
575 unsigned int *index, unsigned long *res_freq,
581 unsigned long best_delta;
582 unsigned long new_delta;
583 unsigned int divider;
585 num_clk_levels = geni_se_clk_tbl_get(se, &tbl);
586 if (num_clk_levels < 0)
587 return num_clk_levels;
589 if (num_clk_levels == 0)
592 best_delta = ULONG_MAX;
593 for (i = 0; i < num_clk_levels; i++) {
594 divider = DIV_ROUND_UP(tbl[i], req_freq);
595 new_delta = req_freq - tbl[i] / divider;
596 if (new_delta < best_delta) {
597 /* We have a new best! */
601 /* If the new best is exact then we're done */
605 /* Record how close we got */
606 best_delta = new_delta;
615 EXPORT_SYMBOL(geni_se_clk_freq_match);
617 #define GENI_SE_DMA_DONE_EN BIT(0)
618 #define GENI_SE_DMA_EOT_EN BIT(1)
619 #define GENI_SE_DMA_AHB_ERR_EN BIT(2)
620 #define GENI_SE_DMA_EOT_BUF BIT(0)
622 * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer
623 * @se: Pointer to the concerned serial engine.
624 * @buf: Pointer to the TX buffer.
625 * @len: Length of the TX buffer.
626 * @iova: Pointer to store the mapped DMA address.
628 * This function is used to prepare the buffers for DMA TX.
630 * Return: 0 on success, standard Linux error codes on failure.
632 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,
635 struct geni_wrapper *wrapper = se->wrapper;
638 *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE);
639 if (dma_mapping_error(wrapper->dev, *iova))
642 val = GENI_SE_DMA_DONE_EN;
643 val |= GENI_SE_DMA_EOT_EN;
644 val |= GENI_SE_DMA_AHB_ERR_EN;
645 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET);
646 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L);
647 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H);
648 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR);
649 writel(len, se->base + SE_DMA_TX_LEN);
652 EXPORT_SYMBOL(geni_se_tx_dma_prep);
655 * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer
656 * @se: Pointer to the concerned serial engine.
657 * @buf: Pointer to the RX buffer.
658 * @len: Length of the RX buffer.
659 * @iova: Pointer to store the mapped DMA address.
661 * This function is used to prepare the buffers for DMA RX.
663 * Return: 0 on success, standard Linux error codes on failure.
665 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
668 struct geni_wrapper *wrapper = se->wrapper;
671 *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE);
672 if (dma_mapping_error(wrapper->dev, *iova))
675 val = GENI_SE_DMA_DONE_EN;
676 val |= GENI_SE_DMA_EOT_EN;
677 val |= GENI_SE_DMA_AHB_ERR_EN;
678 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET);
679 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L);
680 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H);
681 /* RX does not have EOT buffer type bit. So just reset RX_ATTR */
682 writel_relaxed(0, se->base + SE_DMA_RX_ATTR);
683 writel(len, se->base + SE_DMA_RX_LEN);
686 EXPORT_SYMBOL(geni_se_rx_dma_prep);
689 * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer
690 * @se: Pointer to the concerned serial engine.
691 * @iova: DMA address of the TX buffer.
692 * @len: Length of the TX buffer.
694 * This function is used to unprepare the DMA buffers after DMA TX.
696 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
698 struct geni_wrapper *wrapper = se->wrapper;
700 if (iova && !dma_mapping_error(wrapper->dev, iova))
701 dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE);
703 EXPORT_SYMBOL(geni_se_tx_dma_unprep);
706 * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer
707 * @se: Pointer to the concerned serial engine.
708 * @iova: DMA address of the RX buffer.
709 * @len: Length of the RX buffer.
711 * This function is used to unprepare the DMA buffers after DMA RX.
713 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
715 struct geni_wrapper *wrapper = se->wrapper;
717 if (iova && !dma_mapping_error(wrapper->dev, iova))
718 dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE);
720 EXPORT_SYMBOL(geni_se_rx_dma_unprep);
722 static int geni_se_probe(struct platform_device *pdev)
724 struct device *dev = &pdev->dev;
725 struct resource *res;
726 struct geni_wrapper *wrapper;
729 wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL);
734 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
735 wrapper->base = devm_ioremap_resource(dev, res);
736 if (IS_ERR(wrapper->base))
737 return PTR_ERR(wrapper->base);
739 wrapper->ahb_clks[0].id = "m-ahb";
740 wrapper->ahb_clks[1].id = "s-ahb";
741 ret = devm_clk_bulk_get(dev, NUM_AHB_CLKS, wrapper->ahb_clks);
743 dev_err(dev, "Err getting AHB clks %d\n", ret);
747 dev_set_drvdata(dev, wrapper);
748 dev_dbg(dev, "GENI SE Driver probed\n");
749 return devm_of_platform_populate(dev);
752 static const struct of_device_id geni_se_dt_match[] = {
753 { .compatible = "qcom,geni-se-qup", },
756 MODULE_DEVICE_TABLE(of, geni_se_dt_match);
758 static struct platform_driver geni_se_driver = {
760 .name = "geni_se_qup",
761 .of_match_table = geni_se_dt_match,
763 .probe = geni_se_probe,
765 module_platform_driver(geni_se_driver);
767 MODULE_DESCRIPTION("GENI Serial Engine Driver");
768 MODULE_LICENSE("GPL v2");