soc/mediatek/mtk-pmic-wrap.c

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Flora Fu, MediaTek
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <linux/clk.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/of_device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/regmap.h>
  22 #include <linux/reset.h>
  23
  24 #define PWRAP_MT8135_BRIDGE_IORD_ARB_EN         0x4
  25 #define PWRAP_MT8135_BRIDGE_WACS3_EN            0x10
  26 #define PWRAP_MT8135_BRIDGE_INIT_DONE3          0x14
  27 #define PWRAP_MT8135_BRIDGE_WACS4_EN            0x24
  28 #define PWRAP_MT8135_BRIDGE_INIT_DONE4          0x28
  29 #define PWRAP_MT8135_BRIDGE_INT_EN              0x38
  30 #define PWRAP_MT8135_BRIDGE_TIMER_EN            0x48
  31 #define PWRAP_MT8135_BRIDGE_WDT_UNIT            0x50
  32 #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN          0x54
  33
  34 /* macro for wrapper status */
  35 #define PWRAP_GET_WACS_RDATA(x)         (((x) >> 0) & 0x0000ffff)
  36 #define PWRAP_GET_WACS_FSM(x)           (((x) >> 16) & 0x00000007)
  37 #define PWRAP_GET_WACS_REQ(x)           (((x) >> 19) & 0x00000001)
  38 #define PWRAP_STATE_SYNC_IDLE0          (1 << 20)
  39 #define PWRAP_STATE_INIT_DONE0          (1 << 21)
  40
  41 /* macro for WACS FSM */
  42 #define PWRAP_WACS_FSM_IDLE             0x00
  43 #define PWRAP_WACS_FSM_REQ              0x02
  44 #define PWRAP_WACS_FSM_WFDLE            0x04
  45 #define PWRAP_WACS_FSM_WFVLDCLR         0x06
  46 #define PWRAP_WACS_INIT_DONE            0x01
  47 #define PWRAP_WACS_WACS_SYNC_IDLE       0x01
  48 #define PWRAP_WACS_SYNC_BUSY            0x00
  49
  50 /* macro for device wrapper default value */
  51 #define PWRAP_DEW_READ_TEST_VAL         0x5aa5
  52 #define PWRAP_DEW_WRITE_TEST_VAL        0xa55a
  53
  54 /* macro for manual command */
  55 #define PWRAP_MAN_CMD_SPI_WRITE_NEW     (1 << 14)
  56 #define PWRAP_MAN_CMD_SPI_WRITE         (1 << 13)
  57 #define PWRAP_MAN_CMD_OP_CSH            (0x0 << 8)
  58 #define PWRAP_MAN_CMD_OP_CSL            (0x1 << 8)
  59 #define PWRAP_MAN_CMD_OP_CK             (0x2 << 8)
  60 #define PWRAP_MAN_CMD_OP_OUTS           (0x8 << 8)
  61 #define PWRAP_MAN_CMD_OP_OUTD           (0x9 << 8)
  62 #define PWRAP_MAN_CMD_OP_OUTQ           (0xa << 8)
  63
  64 /* macro for Watch Dog Timer Source */
  65 #define PWRAP_WDT_SRC_EN_STAUPD_TRIG            (1 << 25)
  66 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE        (1 << 20)
  67 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE        (1 << 6)
  68 #define PWRAP_WDT_SRC_MASK_ALL                  0xffffffff
  69 #define PWRAP_WDT_SRC_MASK_NO_STAUPD    ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \
  70                                           PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
  71                                           PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
  72
  73 /* Group of bits used for shown slave capability */
  74 #define PWRAP_SLV_CAP_SPI       BIT(0)
  75 #define PWRAP_SLV_CAP_DUALIO    BIT(1)
  76 #define PWRAP_SLV_CAP_SECURITY  BIT(2)
  77 #define HAS_CAP(_c, _x) (((_c) & (_x)) == (_x))
  78
  79 /* defines for slave device wrapper registers */
  80 enum dew_regs {
  81         PWRAP_DEW_BASE,
  82         PWRAP_DEW_DIO_EN,
  83         PWRAP_DEW_READ_TEST,
  84         PWRAP_DEW_WRITE_TEST,
  85         PWRAP_DEW_CRC_EN,
  86         PWRAP_DEW_CRC_VAL,
  87         PWRAP_DEW_MON_GRP_SEL,
  88         PWRAP_DEW_CIPHER_KEY_SEL,
  89         PWRAP_DEW_CIPHER_IV_SEL,
  90         PWRAP_DEW_CIPHER_RDY,
  91         PWRAP_DEW_CIPHER_MODE,
  92         PWRAP_DEW_CIPHER_SWRST,
  93
  94         /* MT6397 only regs */
  95         PWRAP_DEW_EVENT_OUT_EN,
  96         PWRAP_DEW_EVENT_SRC_EN,
  97         PWRAP_DEW_EVENT_SRC,
  98         PWRAP_DEW_EVENT_FLAG,
  99         PWRAP_DEW_MON_FLAG_SEL,
 100         PWRAP_DEW_EVENT_TEST,
 101         PWRAP_DEW_CIPHER_LOAD,
 102         PWRAP_DEW_CIPHER_START,
 103
 104         /* MT6323 only regs */
 105         PWRAP_DEW_CIPHER_EN,
 106         PWRAP_DEW_RDDMY_NO,
 107 };
 108
 109 static const u32 mt6323_regs[] = {
 110         [PWRAP_DEW_BASE] =              0x0000,
 111         [PWRAP_DEW_DIO_EN] =            0x018a,
 112         [PWRAP_DEW_READ_TEST] =         0x018c,
 113         [PWRAP_DEW_WRITE_TEST] =        0x018e,
 114         [PWRAP_DEW_CRC_EN] =            0x0192,
 115         [PWRAP_DEW_CRC_VAL] =           0x0194,
 116         [PWRAP_DEW_MON_GRP_SEL] =       0x0196,
 117         [PWRAP_DEW_CIPHER_KEY_SEL] =    0x0198,
 118         [PWRAP_DEW_CIPHER_IV_SEL] =     0x019a,
 119         [PWRAP_DEW_CIPHER_EN] =         0x019c,
 120         [PWRAP_DEW_CIPHER_RDY] =        0x019e,
 121         [PWRAP_DEW_CIPHER_MODE] =       0x01a0,
 122         [PWRAP_DEW_CIPHER_SWRST] =      0x01a2,
 123         [PWRAP_DEW_RDDMY_NO] =          0x01a4,
 124 };
 125
 126 static const u32 mt6397_regs[] = {
 127         [PWRAP_DEW_BASE] =              0xbc00,
 128         [PWRAP_DEW_EVENT_OUT_EN] =      0xbc00,
 129         [PWRAP_DEW_DIO_EN] =            0xbc02,
 130         [PWRAP_DEW_EVENT_SRC_EN] =      0xbc04,
 131         [PWRAP_DEW_EVENT_SRC] =         0xbc06,
 132         [PWRAP_DEW_EVENT_FLAG] =        0xbc08,
 133         [PWRAP_DEW_READ_TEST] =         0xbc0a,
 134         [PWRAP_DEW_WRITE_TEST] =        0xbc0c,
 135         [PWRAP_DEW_CRC_EN] =            0xbc0e,
 136         [PWRAP_DEW_CRC_VAL] =           0xbc10,
 137         [PWRAP_DEW_MON_GRP_SEL] =       0xbc12,
 138         [PWRAP_DEW_MON_FLAG_SEL] =      0xbc14,
 139         [PWRAP_DEW_EVENT_TEST] =        0xbc16,
 140         [PWRAP_DEW_CIPHER_KEY_SEL] =    0xbc18,
 141         [PWRAP_DEW_CIPHER_IV_SEL] =     0xbc1a,
 142         [PWRAP_DEW_CIPHER_LOAD] =       0xbc1c,
 143         [PWRAP_DEW_CIPHER_START] =      0xbc1e,
 144         [PWRAP_DEW_CIPHER_RDY] =        0xbc20,
 145         [PWRAP_DEW_CIPHER_MODE] =       0xbc22,
 146         [PWRAP_DEW_CIPHER_SWRST] =      0xbc24,
 147 };
 148
 149 static const u32 mt6351_regs[] = {
 150         [PWRAP_DEW_DIO_EN] =            0x02F2,
 151         [PWRAP_DEW_READ_TEST] =         0x02F4,
 152         [PWRAP_DEW_WRITE_TEST] =        0x02F6,
 153         [PWRAP_DEW_CRC_EN] =            0x02FA,
 154         [PWRAP_DEW_CRC_VAL] =           0x02FC,
 155         [PWRAP_DEW_CIPHER_KEY_SEL] =    0x0300,
 156         [PWRAP_DEW_CIPHER_IV_SEL] =     0x0302,
 157         [PWRAP_DEW_CIPHER_EN] =         0x0304,
 158         [PWRAP_DEW_CIPHER_RDY] =        0x0306,
 159         [PWRAP_DEW_CIPHER_MODE] =       0x0308,
 160         [PWRAP_DEW_CIPHER_SWRST] =      0x030A,
 161         [PWRAP_DEW_RDDMY_NO] =          0x030C,
 162 };
 163
 164 enum pwrap_regs {
 165         PWRAP_MUX_SEL,
 166         PWRAP_WRAP_EN,
 167         PWRAP_DIO_EN,
 168         PWRAP_SIDLY,
 169         PWRAP_CSHEXT_WRITE,
 170         PWRAP_CSHEXT_READ,
 171         PWRAP_CSLEXT_START,
 172         PWRAP_CSLEXT_END,
 173         PWRAP_STAUPD_PRD,
 174         PWRAP_STAUPD_GRPEN,
 175         PWRAP_STAUPD_MAN_TRIG,
 176         PWRAP_STAUPD_STA,
 177         PWRAP_WRAP_STA,
 178         PWRAP_HARB_INIT,
 179         PWRAP_HARB_HPRIO,
 180         PWRAP_HIPRIO_ARB_EN,
 181         PWRAP_HARB_STA0,
 182         PWRAP_HARB_STA1,
 183         PWRAP_MAN_EN,
 184         PWRAP_MAN_CMD,
 185         PWRAP_MAN_RDATA,
 186         PWRAP_MAN_VLDCLR,
 187         PWRAP_WACS0_EN,
 188         PWRAP_INIT_DONE0,
 189         PWRAP_WACS0_CMD,
 190         PWRAP_WACS0_RDATA,
 191         PWRAP_WACS0_VLDCLR,
 192         PWRAP_WACS1_EN,
 193         PWRAP_INIT_DONE1,
 194         PWRAP_WACS1_CMD,
 195         PWRAP_WACS1_RDATA,
 196         PWRAP_WACS1_VLDCLR,
 197         PWRAP_WACS2_EN,
 198         PWRAP_INIT_DONE2,
 199         PWRAP_WACS2_CMD,
 200         PWRAP_WACS2_RDATA,
 201         PWRAP_WACS2_VLDCLR,
 202         PWRAP_INT_EN,
 203         PWRAP_INT_FLG_RAW,
 204         PWRAP_INT_FLG,
 205         PWRAP_INT_CLR,
 206         PWRAP_SIG_ADR,
 207         PWRAP_SIG_MODE,
 208         PWRAP_SIG_VALUE,
 209         PWRAP_SIG_ERRVAL,
 210         PWRAP_CRC_EN,
 211         PWRAP_TIMER_EN,
 212         PWRAP_TIMER_STA,
 213         PWRAP_WDT_UNIT,
 214         PWRAP_WDT_SRC_EN,
 215         PWRAP_WDT_FLG,
 216         PWRAP_DEBUG_INT_SEL,
 217         PWRAP_CIPHER_KEY_SEL,
 218         PWRAP_CIPHER_IV_SEL,
 219         PWRAP_CIPHER_RDY,
 220         PWRAP_CIPHER_MODE,
 221         PWRAP_CIPHER_SWRST,
 222         PWRAP_DCM_EN,
 223         PWRAP_DCM_DBC_PRD,
 224
 225         /* MT2701 only regs */
 226         PWRAP_ADC_CMD_ADDR,
 227         PWRAP_PWRAP_ADC_CMD,
 228         PWRAP_ADC_RDY_ADDR,
 229         PWRAP_ADC_RDATA_ADDR1,
 230         PWRAP_ADC_RDATA_ADDR2,
 231
 232         /* MT7622 only regs */
 233         PWRAP_EINT_STA0_ADR,
 234         PWRAP_EINT_STA1_ADR,
 235         PWRAP_STA,
 236         PWRAP_CLR,
 237         PWRAP_DVFS_ADR8,
 238         PWRAP_DVFS_WDATA8,
 239         PWRAP_DVFS_ADR9,
 240         PWRAP_DVFS_WDATA9,
 241         PWRAP_DVFS_ADR10,
 242         PWRAP_DVFS_WDATA10,
 243         PWRAP_DVFS_ADR11,
 244         PWRAP_DVFS_WDATA11,
 245         PWRAP_DVFS_ADR12,
 246         PWRAP_DVFS_WDATA12,
 247         PWRAP_DVFS_ADR13,
 248         PWRAP_DVFS_WDATA13,
 249         PWRAP_DVFS_ADR14,
 250         PWRAP_DVFS_WDATA14,
 251         PWRAP_DVFS_ADR15,
 252         PWRAP_DVFS_WDATA15,
 253         PWRAP_EXT_CK,
 254         PWRAP_ADC_RDATA_ADDR,
 255         PWRAP_GPS_STA,
 256         PWRAP_SW_RST,
 257         PWRAP_DVFS_STEP_CTRL0,
 258         PWRAP_DVFS_STEP_CTRL1,
 259         PWRAP_DVFS_STEP_CTRL2,
 260         PWRAP_SPI2_CTRL,
 261
 262         /* MT8135 only regs */
 263         PWRAP_CSHEXT,
 264         PWRAP_EVENT_IN_EN,
 265         PWRAP_EVENT_DST_EN,
 266         PWRAP_RRARB_INIT,
 267         PWRAP_RRARB_EN,
 268         PWRAP_RRARB_STA0,
 269         PWRAP_RRARB_STA1,
 270         PWRAP_EVENT_STA,
 271         PWRAP_EVENT_STACLR,
 272         PWRAP_CIPHER_LOAD,
 273         PWRAP_CIPHER_START,
 274
 275         /* MT8173 only regs */
 276         PWRAP_RDDMY,
 277         PWRAP_SI_CK_CON,
 278         PWRAP_DVFS_ADR0,
 279         PWRAP_DVFS_WDATA0,
 280         PWRAP_DVFS_ADR1,
 281         PWRAP_DVFS_WDATA1,
 282         PWRAP_DVFS_ADR2,
 283         PWRAP_DVFS_WDATA2,
 284         PWRAP_DVFS_ADR3,
 285         PWRAP_DVFS_WDATA3,
 286         PWRAP_DVFS_ADR4,
 287         PWRAP_DVFS_WDATA4,
 288         PWRAP_DVFS_ADR5,
 289         PWRAP_DVFS_WDATA5,
 290         PWRAP_DVFS_ADR6,
 291         PWRAP_DVFS_WDATA6,
 292         PWRAP_DVFS_ADR7,
 293         PWRAP_DVFS_WDATA7,
 294         PWRAP_SPMINF_STA,
 295         PWRAP_CIPHER_EN,
 296 };
 297
 298 static int mt2701_regs[] = {
 299         [PWRAP_MUX_SEL] =               0x0,
 300         [PWRAP_WRAP_EN] =               0x4,
 301         [PWRAP_DIO_EN] =                0x8,
 302         [PWRAP_SIDLY] =                 0xc,
 303         [PWRAP_RDDMY] =                 0x18,
 304         [PWRAP_SI_CK_CON] =             0x1c,
 305         [PWRAP_CSHEXT_WRITE] =          0x20,
 306         [PWRAP_CSHEXT_READ] =           0x24,
 307         [PWRAP_CSLEXT_START] =          0x28,
 308         [PWRAP_CSLEXT_END] =            0x2c,
 309         [PWRAP_STAUPD_PRD] =            0x30,
 310         [PWRAP_STAUPD_GRPEN] =          0x34,
 311         [PWRAP_STAUPD_MAN_TRIG] =       0x38,
 312         [PWRAP_STAUPD_STA] =            0x3c,
 313         [PWRAP_WRAP_STA] =              0x44,
 314         [PWRAP_HARB_INIT] =             0x48,
 315         [PWRAP_HARB_HPRIO] =            0x4c,
 316         [PWRAP_HIPRIO_ARB_EN] =         0x50,
 317         [PWRAP_HARB_STA0] =             0x54,
 318         [PWRAP_HARB_STA1] =             0x58,
 319         [PWRAP_MAN_EN] =                0x5c,
 320         [PWRAP_MAN_CMD] =               0x60,
 321         [PWRAP_MAN_RDATA] =             0x64,
 322         [PWRAP_MAN_VLDCLR] =            0x68,
 323         [PWRAP_WACS0_EN] =              0x6c,
 324         [PWRAP_INIT_DONE0] =            0x70,
 325         [PWRAP_WACS0_CMD] =             0x74,
 326         [PWRAP_WACS0_RDATA] =           0x78,
 327         [PWRAP_WACS0_VLDCLR] =          0x7c,
 328         [PWRAP_WACS1_EN] =              0x80,
 329         [PWRAP_INIT_DONE1] =            0x84,
 330         [PWRAP_WACS1_CMD] =             0x88,
 331         [PWRAP_WACS1_RDATA] =           0x8c,
 332         [PWRAP_WACS1_VLDCLR] =          0x90,
 333         [PWRAP_WACS2_EN] =              0x94,
 334         [PWRAP_INIT_DONE2] =            0x98,
 335         [PWRAP_WACS2_CMD] =             0x9c,
 336         [PWRAP_WACS2_RDATA] =           0xa0,
 337         [PWRAP_WACS2_VLDCLR] =          0xa4,
 338         [PWRAP_INT_EN] =                0xa8,
 339         [PWRAP_INT_FLG_RAW] =           0xac,
 340         [PWRAP_INT_FLG] =               0xb0,
 341         [PWRAP_INT_CLR] =               0xb4,
 342         [PWRAP_SIG_ADR] =               0xb8,
 343         [PWRAP_SIG_MODE] =              0xbc,
 344         [PWRAP_SIG_VALUE] =             0xc0,
 345         [PWRAP_SIG_ERRVAL] =            0xc4,
 346         [PWRAP_CRC_EN] =                0xc8,
 347         [PWRAP_TIMER_EN] =              0xcc,
 348         [PWRAP_TIMER_STA] =             0xd0,
 349         [PWRAP_WDT_UNIT] =              0xd4,
 350         [PWRAP_WDT_SRC_EN] =            0xd8,
 351         [PWRAP_WDT_FLG] =               0xdc,
 352         [PWRAP_DEBUG_INT_SEL] =         0xe0,
 353         [PWRAP_DVFS_ADR0] =             0xe4,
 354         [PWRAP_DVFS_WDATA0] =           0xe8,
 355         [PWRAP_DVFS_ADR1] =             0xec,
 356         [PWRAP_DVFS_WDATA1] =           0xf0,
 357         [PWRAP_DVFS_ADR2] =             0xf4,
 358         [PWRAP_DVFS_WDATA2] =           0xf8,
 359         [PWRAP_DVFS_ADR3] =             0xfc,
 360         [PWRAP_DVFS_WDATA3] =           0x100,
 361         [PWRAP_DVFS_ADR4] =             0x104,
 362         [PWRAP_DVFS_WDATA4] =           0x108,
 363         [PWRAP_DVFS_ADR5] =             0x10c,
 364         [PWRAP_DVFS_WDATA5] =           0x110,
 365         [PWRAP_DVFS_ADR6] =             0x114,
 366         [PWRAP_DVFS_WDATA6] =           0x118,
 367         [PWRAP_DVFS_ADR7] =             0x11c,
 368         [PWRAP_DVFS_WDATA7] =           0x120,
 369         [PWRAP_CIPHER_KEY_SEL] =        0x124,
 370         [PWRAP_CIPHER_IV_SEL] =         0x128,
 371         [PWRAP_CIPHER_EN] =             0x12c,
 372         [PWRAP_CIPHER_RDY] =            0x130,
 373         [PWRAP_CIPHER_MODE] =           0x134,
 374         [PWRAP_CIPHER_SWRST] =          0x138,
 375         [PWRAP_DCM_EN] =                0x13c,
 376         [PWRAP_DCM_DBC_PRD] =           0x140,
 377         [PWRAP_ADC_CMD_ADDR] =          0x144,
 378         [PWRAP_PWRAP_ADC_CMD] =         0x148,
 379         [PWRAP_ADC_RDY_ADDR] =          0x14c,
 380         [PWRAP_ADC_RDATA_ADDR1] =       0x150,
 381         [PWRAP_ADC_RDATA_ADDR2] =       0x154,
 382 };
 383
 384 static int mt6797_regs[] = {
 385         [PWRAP_MUX_SEL] =               0x0,
 386         [PWRAP_WRAP_EN] =               0x4,
 387         [PWRAP_DIO_EN] =                0x8,
 388         [PWRAP_SIDLY] =                 0xC,
 389         [PWRAP_RDDMY] =                 0x10,
 390         [PWRAP_CSHEXT_WRITE] =          0x18,
 391         [PWRAP_CSHEXT_READ] =           0x1C,
 392         [PWRAP_CSLEXT_START] =          0x20,
 393         [PWRAP_CSLEXT_END] =            0x24,
 394         [PWRAP_STAUPD_PRD] =            0x28,
 395         [PWRAP_HARB_HPRIO] =            0x50,
 396         [PWRAP_HIPRIO_ARB_EN] =         0x54,
 397         [PWRAP_MAN_EN] =                0x60,
 398         [PWRAP_MAN_CMD] =               0x64,
 399         [PWRAP_WACS0_EN] =              0x70,
 400         [PWRAP_WACS1_EN] =              0x84,
 401         [PWRAP_WACS2_EN] =              0x98,
 402         [PWRAP_INIT_DONE2] =            0x9C,
 403         [PWRAP_WACS2_CMD] =             0xA0,
 404         [PWRAP_WACS2_RDATA] =           0xA4,
 405         [PWRAP_WACS2_VLDCLR] =          0xA8,
 406         [PWRAP_INT_EN] =                0xC0,
 407         [PWRAP_INT_FLG_RAW] =           0xC4,
 408         [PWRAP_INT_FLG] =               0xC8,
 409         [PWRAP_INT_CLR] =               0xCC,
 410         [PWRAP_TIMER_EN] =              0xF4,
 411         [PWRAP_WDT_UNIT] =              0xFC,
 412         [PWRAP_WDT_SRC_EN] =            0x100,
 413         [PWRAP_DCM_EN] =                0x1CC,
 414         [PWRAP_DCM_DBC_PRD] =           0x1D4,
 415 };
 416
 417 static int mt7622_regs[] = {
 418         [PWRAP_MUX_SEL] =               0x0,
 419         [PWRAP_WRAP_EN] =               0x4,
 420         [PWRAP_DIO_EN] =                0x8,
 421         [PWRAP_SIDLY] =                 0xC,
 422         [PWRAP_RDDMY] =                 0x10,
 423         [PWRAP_SI_CK_CON] =             0x14,
 424         [PWRAP_CSHEXT_WRITE] =          0x18,
 425         [PWRAP_CSHEXT_READ] =           0x1C,
 426         [PWRAP_CSLEXT_START] =          0x20,
 427         [PWRAP_CSLEXT_END] =            0x24,
 428         [PWRAP_STAUPD_PRD] =            0x28,
 429         [PWRAP_STAUPD_GRPEN] =          0x2C,
 430         [PWRAP_EINT_STA0_ADR] =         0x30,
 431         [PWRAP_EINT_STA1_ADR] =         0x34,
 432         [PWRAP_STA] =                   0x38,
 433         [PWRAP_CLR] =                   0x3C,
 434         [PWRAP_STAUPD_MAN_TRIG] =       0x40,
 435         [PWRAP_STAUPD_STA] =            0x44,
 436         [PWRAP_WRAP_STA] =              0x48,
 437         [PWRAP_HARB_INIT] =             0x4C,
 438         [PWRAP_HARB_HPRIO] =            0x50,
 439         [PWRAP_HIPRIO_ARB_EN] =         0x54,
 440         [PWRAP_HARB_STA0] =             0x58,
 441         [PWRAP_HARB_STA1] =             0x5C,
 442         [PWRAP_MAN_EN] =                0x60,
 443         [PWRAP_MAN_CMD] =               0x64,
 444         [PWRAP_MAN_RDATA] =             0x68,
 445         [PWRAP_MAN_VLDCLR] =            0x6C,
 446         [PWRAP_WACS0_EN] =              0x70,
 447         [PWRAP_INIT_DONE0] =            0x74,
 448         [PWRAP_WACS0_CMD] =             0x78,
 449         [PWRAP_WACS0_RDATA] =           0x7C,
 450         [PWRAP_WACS0_VLDCLR] =          0x80,
 451         [PWRAP_WACS1_EN] =              0x84,
 452         [PWRAP_INIT_DONE1] =            0x88,
 453         [PWRAP_WACS1_CMD] =             0x8C,
 454         [PWRAP_WACS1_RDATA] =           0x90,
 455         [PWRAP_WACS1_VLDCLR] =          0x94,
 456         [PWRAP_WACS2_EN] =              0x98,
 457         [PWRAP_INIT_DONE2] =            0x9C,
 458         [PWRAP_WACS2_CMD] =             0xA0,
 459         [PWRAP_WACS2_RDATA] =           0xA4,
 460         [PWRAP_WACS2_VLDCLR] =          0xA8,
 461         [PWRAP_INT_EN] =                0xAC,
 462         [PWRAP_INT_FLG_RAW] =           0xB0,
 463         [PWRAP_INT_FLG] =               0xB4,
 464         [PWRAP_INT_CLR] =               0xB8,
 465         [PWRAP_SIG_ADR] =               0xBC,
 466         [PWRAP_SIG_MODE] =              0xC0,
 467         [PWRAP_SIG_VALUE] =             0xC4,
 468         [PWRAP_SIG_ERRVAL] =            0xC8,
 469         [PWRAP_CRC_EN] =                0xCC,
 470         [PWRAP_TIMER_EN] =              0xD0,
 471         [PWRAP_TIMER_STA] =             0xD4,
 472         [PWRAP_WDT_UNIT] =              0xD8,
 473         [PWRAP_WDT_SRC_EN] =            0xDC,
 474         [PWRAP_WDT_FLG] =               0xE0,
 475         [PWRAP_DEBUG_INT_SEL] =         0xE4,
 476         [PWRAP_DVFS_ADR0] =             0xE8,
 477         [PWRAP_DVFS_WDATA0] =           0xEC,
 478         [PWRAP_DVFS_ADR1] =             0xF0,
 479         [PWRAP_DVFS_WDATA1] =           0xF4,
 480         [PWRAP_DVFS_ADR2] =             0xF8,
 481         [PWRAP_DVFS_WDATA2] =           0xFC,
 482         [PWRAP_DVFS_ADR3] =             0x100,
 483         [PWRAP_DVFS_WDATA3] =           0x104,
 484         [PWRAP_DVFS_ADR4] =             0x108,
 485         [PWRAP_DVFS_WDATA4] =           0x10C,
 486         [PWRAP_DVFS_ADR5] =             0x110,
 487         [PWRAP_DVFS_WDATA5] =           0x114,
 488         [PWRAP_DVFS_ADR6] =             0x118,
 489         [PWRAP_DVFS_WDATA6] =           0x11C,
 490         [PWRAP_DVFS_ADR7] =             0x120,
 491         [PWRAP_DVFS_WDATA7] =           0x124,
 492         [PWRAP_DVFS_ADR8] =             0x128,
 493         [PWRAP_DVFS_WDATA8] =           0x12C,
 494         [PWRAP_DVFS_ADR9] =             0x130,
 495         [PWRAP_DVFS_WDATA9] =           0x134,
 496         [PWRAP_DVFS_ADR10] =            0x138,
 497         [PWRAP_DVFS_WDATA10] =          0x13C,
 498         [PWRAP_DVFS_ADR11] =            0x140,
 499         [PWRAP_DVFS_WDATA11] =          0x144,
 500         [PWRAP_DVFS_ADR12] =            0x148,
 501         [PWRAP_DVFS_WDATA12] =          0x14C,
 502         [PWRAP_DVFS_ADR13] =            0x150,
 503         [PWRAP_DVFS_WDATA13] =          0x154,
 504         [PWRAP_DVFS_ADR14] =            0x158,
 505         [PWRAP_DVFS_WDATA14] =          0x15C,
 506         [PWRAP_DVFS_ADR15] =            0x160,
 507         [PWRAP_DVFS_WDATA15] =          0x164,
 508         [PWRAP_SPMINF_STA] =            0x168,
 509         [PWRAP_CIPHER_KEY_SEL] =        0x16C,
 510         [PWRAP_CIPHER_IV_SEL] =         0x170,
 511         [PWRAP_CIPHER_EN] =             0x174,
 512         [PWRAP_CIPHER_RDY] =            0x178,
 513         [PWRAP_CIPHER_MODE] =           0x17C,
 514         [PWRAP_CIPHER_SWRST] =          0x180,
 515         [PWRAP_DCM_EN] =                0x184,
 516         [PWRAP_DCM_DBC_PRD] =           0x188,
 517         [PWRAP_EXT_CK] =                0x18C,
 518         [PWRAP_ADC_CMD_ADDR] =          0x190,
 519         [PWRAP_PWRAP_ADC_CMD] =         0x194,
 520         [PWRAP_ADC_RDATA_ADDR] =        0x198,
 521         [PWRAP_GPS_STA] =               0x19C,
 522         [PWRAP_SW_RST] =                0x1A0,
 523         [PWRAP_DVFS_STEP_CTRL0] =       0x238,
 524         [PWRAP_DVFS_STEP_CTRL1] =       0x23C,
 525         [PWRAP_DVFS_STEP_CTRL2] =       0x240,
 526         [PWRAP_SPI2_CTRL] =             0x244,
 527 };
 528
 529 static int mt8173_regs[] = {
 530         [PWRAP_MUX_SEL] =               0x0,
 531         [PWRAP_WRAP_EN] =               0x4,
 532         [PWRAP_DIO_EN] =                0x8,
 533         [PWRAP_SIDLY] =                 0xc,
 534         [PWRAP_RDDMY] =                 0x10,
 535         [PWRAP_SI_CK_CON] =             0x14,
 536         [PWRAP_CSHEXT_WRITE] =          0x18,
 537         [PWRAP_CSHEXT_READ] =           0x1c,
 538         [PWRAP_CSLEXT_START] =          0x20,
 539         [PWRAP_CSLEXT_END] =            0x24,
 540         [PWRAP_STAUPD_PRD] =            0x28,
 541         [PWRAP_STAUPD_GRPEN] =          0x2c,
 542         [PWRAP_STAUPD_MAN_TRIG] =       0x40,
 543         [PWRAP_STAUPD_STA] =            0x44,
 544         [PWRAP_WRAP_STA] =              0x48,
 545         [PWRAP_HARB_INIT] =             0x4c,
 546         [PWRAP_HARB_HPRIO] =            0x50,
 547         [PWRAP_HIPRIO_ARB_EN] =         0x54,
 548         [PWRAP_HARB_STA0] =             0x58,
 549         [PWRAP_HARB_STA1] =             0x5c,
 550         [PWRAP_MAN_EN] =                0x60,
 551         [PWRAP_MAN_CMD] =               0x64,
 552         [PWRAP_MAN_RDATA] =             0x68,
 553         [PWRAP_MAN_VLDCLR] =            0x6c,
 554         [PWRAP_WACS0_EN] =              0x70,
 555         [PWRAP_INIT_DONE0] =            0x74,
 556         [PWRAP_WACS0_CMD] =             0x78,
 557         [PWRAP_WACS0_RDATA] =           0x7c,
 558         [PWRAP_WACS0_VLDCLR] =          0x80,
 559         [PWRAP_WACS1_EN] =              0x84,
 560         [PWRAP_INIT_DONE1] =            0x88,
 561         [PWRAP_WACS1_CMD] =             0x8c,
 562         [PWRAP_WACS1_RDATA] =           0x90,
 563         [PWRAP_WACS1_VLDCLR] =          0x94,
 564         [PWRAP_WACS2_EN] =              0x98,
 565         [PWRAP_INIT_DONE2] =            0x9c,
 566         [PWRAP_WACS2_CMD] =             0xa0,
 567         [PWRAP_WACS2_RDATA] =           0xa4,
 568         [PWRAP_WACS2_VLDCLR] =          0xa8,
 569         [PWRAP_INT_EN] =                0xac,
 570         [PWRAP_INT_FLG_RAW] =           0xb0,
 571         [PWRAP_INT_FLG] =               0xb4,
 572         [PWRAP_INT_CLR] =               0xb8,
 573         [PWRAP_SIG_ADR] =               0xbc,
 574         [PWRAP_SIG_MODE] =              0xc0,
 575         [PWRAP_SIG_VALUE] =             0xc4,
 576         [PWRAP_SIG_ERRVAL] =            0xc8,
 577         [PWRAP_CRC_EN] =                0xcc,
 578         [PWRAP_TIMER_EN] =              0xd0,
 579         [PWRAP_TIMER_STA] =             0xd4,
 580         [PWRAP_WDT_UNIT] =              0xd8,
 581         [PWRAP_WDT_SRC_EN] =            0xdc,
 582         [PWRAP_WDT_FLG] =               0xe0,
 583         [PWRAP_DEBUG_INT_SEL] =         0xe4,
 584         [PWRAP_DVFS_ADR0] =             0xe8,
 585         [PWRAP_DVFS_WDATA0] =           0xec,
 586         [PWRAP_DVFS_ADR1] =             0xf0,
 587         [PWRAP_DVFS_WDATA1] =           0xf4,
 588         [PWRAP_DVFS_ADR2] =             0xf8,
 589         [PWRAP_DVFS_WDATA2] =           0xfc,
 590         [PWRAP_DVFS_ADR3] =             0x100,
 591         [PWRAP_DVFS_WDATA3] =           0x104,
 592         [PWRAP_DVFS_ADR4] =             0x108,
 593         [PWRAP_DVFS_WDATA4] =           0x10c,
 594         [PWRAP_DVFS_ADR5] =             0x110,
 595         [PWRAP_DVFS_WDATA5] =           0x114,
 596         [PWRAP_DVFS_ADR6] =             0x118,
 597         [PWRAP_DVFS_WDATA6] =           0x11c,
 598         [PWRAP_DVFS_ADR7] =             0x120,
 599         [PWRAP_DVFS_WDATA7] =           0x124,
 600         [PWRAP_SPMINF_STA] =            0x128,
 601         [PWRAP_CIPHER_KEY_SEL] =        0x12c,
 602         [PWRAP_CIPHER_IV_SEL] =         0x130,
 603         [PWRAP_CIPHER_EN] =             0x134,
 604         [PWRAP_CIPHER_RDY] =            0x138,
 605         [PWRAP_CIPHER_MODE] =           0x13c,
 606         [PWRAP_CIPHER_SWRST] =          0x140,
 607         [PWRAP_DCM_EN] =                0x144,
 608         [PWRAP_DCM_DBC_PRD] =           0x148,
 609 };
 610
 611 static int mt8135_regs[] = {
 612         [PWRAP_MUX_SEL] =               0x0,
 613         [PWRAP_WRAP_EN] =               0x4,
 614         [PWRAP_DIO_EN] =                0x8,
 615         [PWRAP_SIDLY] =                 0xc,
 616         [PWRAP_CSHEXT] =                0x10,
 617         [PWRAP_CSHEXT_WRITE] =          0x14,
 618         [PWRAP_CSHEXT_READ] =           0x18,
 619         [PWRAP_CSLEXT_START] =          0x1c,
 620         [PWRAP_CSLEXT_END] =            0x20,
 621         [PWRAP_STAUPD_PRD] =            0x24,
 622         [PWRAP_STAUPD_GRPEN] =          0x28,
 623         [PWRAP_STAUPD_MAN_TRIG] =       0x2c,
 624         [PWRAP_STAUPD_STA] =            0x30,
 625         [PWRAP_EVENT_IN_EN] =           0x34,
 626         [PWRAP_EVENT_DST_EN] =          0x38,
 627         [PWRAP_WRAP_STA] =              0x3c,
 628         [PWRAP_RRARB_INIT] =            0x40,
 629         [PWRAP_RRARB_EN] =              0x44,
 630         [PWRAP_RRARB_STA0] =            0x48,
 631         [PWRAP_RRARB_STA1] =            0x4c,
 632         [PWRAP_HARB_INIT] =             0x50,
 633         [PWRAP_HARB_HPRIO] =            0x54,
 634         [PWRAP_HIPRIO_ARB_EN] =         0x58,
 635         [PWRAP_HARB_STA0] =             0x5c,
 636         [PWRAP_HARB_STA1] =             0x60,
 637         [PWRAP_MAN_EN] =                0x64,
 638         [PWRAP_MAN_CMD] =               0x68,
 639         [PWRAP_MAN_RDATA] =             0x6c,
 640         [PWRAP_MAN_VLDCLR] =            0x70,
 641         [PWRAP_WACS0_EN] =              0x74,
 642         [PWRAP_INIT_DONE0] =            0x78,
 643         [PWRAP_WACS0_CMD] =             0x7c,
 644         [PWRAP_WACS0_RDATA] =           0x80,
 645         [PWRAP_WACS0_VLDCLR] =          0x84,
 646         [PWRAP_WACS1_EN] =              0x88,
 647         [PWRAP_INIT_DONE1] =            0x8c,
 648         [PWRAP_WACS1_CMD] =             0x90,
 649         [PWRAP_WACS1_RDATA] =           0x94,
 650         [PWRAP_WACS1_VLDCLR] =          0x98,
 651         [PWRAP_WACS2_EN] =              0x9c,
 652         [PWRAP_INIT_DONE2] =            0xa0,
 653         [PWRAP_WACS2_CMD] =             0xa4,
 654         [PWRAP_WACS2_RDATA] =           0xa8,
 655         [PWRAP_WACS2_VLDCLR] =          0xac,
 656         [PWRAP_INT_EN] =                0xb0,
 657         [PWRAP_INT_FLG_RAW] =           0xb4,
 658         [PWRAP_INT_FLG] =               0xb8,
 659         [PWRAP_INT_CLR] =               0xbc,
 660         [PWRAP_SIG_ADR] =               0xc0,
 661         [PWRAP_SIG_MODE] =              0xc4,
 662         [PWRAP_SIG_VALUE] =             0xc8,
 663         [PWRAP_SIG_ERRVAL] =            0xcc,
 664         [PWRAP_CRC_EN] =                0xd0,
 665         [PWRAP_EVENT_STA] =             0xd4,
 666         [PWRAP_EVENT_STACLR] =          0xd8,
 667         [PWRAP_TIMER_EN] =              0xdc,
 668         [PWRAP_TIMER_STA] =             0xe0,
 669         [PWRAP_WDT_UNIT] =              0xe4,
 670         [PWRAP_WDT_SRC_EN] =            0xe8,
 671         [PWRAP_WDT_FLG] =               0xec,
 672         [PWRAP_DEBUG_INT_SEL] =         0xf0,
 673         [PWRAP_CIPHER_KEY_SEL] =        0x134,
 674         [PWRAP_CIPHER_IV_SEL] =         0x138,
 675         [PWRAP_CIPHER_LOAD] =           0x13c,
 676         [PWRAP_CIPHER_START] =          0x140,
 677         [PWRAP_CIPHER_RDY] =            0x144,
 678         [PWRAP_CIPHER_MODE] =           0x148,
 679         [PWRAP_CIPHER_SWRST] =          0x14c,
 680         [PWRAP_DCM_EN] =                0x15c,
 681         [PWRAP_DCM_DBC_PRD] =           0x160,
 682 };
 683
 684 enum pmic_type {
 685         PMIC_MT6323,
 686         PMIC_MT6351,
 687         PMIC_MT6380,
 688         PMIC_MT6397,
 689 };
 690
 691 enum pwrap_type {
 692         PWRAP_MT2701,
 693         PWRAP_MT6797,
 694         PWRAP_MT7622,
 695         PWRAP_MT8135,
 696         PWRAP_MT8173,
 697 };
 698
 699 struct pmic_wrapper;
 700 struct pwrap_slv_type {
 701         const u32 *dew_regs;
 702         enum pmic_type type;
 703         const struct regmap_config *regmap;
 704         /* Flags indicating the capability for the target slave */
 705         u32 caps;
 706         /*
 707          * pwrap operations are highly associated with the PMIC types,
 708          * so the pointers added increases flexibility allowing determination
 709          * which type is used by the detection through device tree.
 710          */
 711         int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
 712         int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
 713 };
 714
 715 struct pmic_wrapper {
 716         struct device *dev;
 717         void __iomem *base;
 718         struct regmap *regmap;
 719         const struct pmic_wrapper_type *master;
 720         const struct pwrap_slv_type *slave;
 721         struct clk *clk_spi;
 722         struct clk *clk_wrap;
 723         struct reset_control *rstc;
 724
 725         struct reset_control *rstc_bridge;
 726         void __iomem *bridge_base;
 727 };
 728
 729 struct pmic_wrapper_type {
 730         int *regs;
 731         enum pwrap_type type;
 732         u32 arb_en_all;
 733         u32 int_en_all;
 734         u32 spi_w;
 735         u32 wdt_src;
 736         unsigned int has_bridge:1;
 737         int (*init_reg_clock)(struct pmic_wrapper *wrp);
 738         int (*init_soc_specific)(struct pmic_wrapper *wrp);
 739 };
 740
 741 static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
 742 {
 743         return readl(wrp->base + wrp->master->regs[reg]);
 744 }
 745
 746 static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
 747 {
 748         writel(val, wrp->base + wrp->master->regs[reg]);
 749 }
 750
 751 static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
 752 {
 753         u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
 754
 755         return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE;
 756 }
 757
 758 static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
 759 {
 760         u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
 761
 762         return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR;
 763 }
 764
 765 /*
 766  * Timeout issue sometimes caused by the last read command
 767  * failed because pmic wrap could not got the FSM_VLDCLR
 768  * in time after finishing WACS2_CMD. It made state machine
 769  * still on FSM_VLDCLR and timeout next time.
 770  * Check the status of FSM and clear the vldclr to recovery the
 771  * error.
 772  */
 773 static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp)
 774 {
 775         if (pwrap_is_fsm_vldclr(wrp))
 776                 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
 777 }
 778
 779 static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
 780 {
 781         return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
 782 }
 783
 784 static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp)
 785 {
 786         u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
 787
 788         return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) &&
 789                 (val & PWRAP_STATE_SYNC_IDLE0);
 790 }
 791
 792 static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
 793                 bool (*fp)(struct pmic_wrapper *))
 794 {
 795         unsigned long timeout;
 796
 797         timeout = jiffies + usecs_to_jiffies(10000);
 798
 799         do {
 800                 if (time_after(jiffies, timeout))
 801                         return fp(wrp) ? 0 : -ETIMEDOUT;
 802                 if (fp(wrp))
 803                         return 0;
 804         } while (1);
 805 }
 806
 807 static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
 808 {
 809         int ret;
 810
 811         ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
 812         if (ret) {
 813                 pwrap_leave_fsm_vldclr(wrp);
 814                 return ret;
 815         }
 816
 817         pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
 818
 819         ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
 820         if (ret)
 821                 return ret;
 822
 823         *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA));
 824
 825         pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
 826
 827         return 0;
 828 }
 829
 830 static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
 831 {
 832         int ret, msb;
 833
 834         *rdata = 0;
 835         for (msb = 0; msb < 2; msb++) {
 836                 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
 837                 if (ret) {
 838                         pwrap_leave_fsm_vldclr(wrp);
 839                         return ret;
 840                 }
 841
 842                 pwrap_writel(wrp, ((msb << 30) | (adr << 16)),
 843                              PWRAP_WACS2_CMD);
 844
 845                 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
 846                 if (ret)
 847                         return ret;
 848
 849                 *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp,
 850                            PWRAP_WACS2_RDATA)) << (16 * msb));
 851
 852                 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
 853         }
 854
 855         return 0;
 856 }
 857
 858 static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
 859 {
 860         return wrp->slave->pwrap_read(wrp, adr, rdata);
 861 }
 862
 863 static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
 864 {
 865         int ret;
 866
 867         ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
 868         if (ret) {
 869                 pwrap_leave_fsm_vldclr(wrp);
 870                 return ret;
 871         }
 872
 873         pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
 874                      PWRAP_WACS2_CMD);
 875
 876         return 0;
 877 }
 878
 879 static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
 880 {
 881         int ret, msb, rdata;
 882
 883         for (msb = 0; msb < 2; msb++) {
 884                 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
 885                 if (ret) {
 886                         pwrap_leave_fsm_vldclr(wrp);
 887                         return ret;
 888                 }
 889
 890                 pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) |
 891                              ((wdata >> (msb * 16)) & 0xffff),
 892                              PWRAP_WACS2_CMD);
 893
 894                 /*
 895                  * The pwrap_read operation is the requirement of hardware used
 896                  * for the synchronization between two successive 16-bit
 897                  * pwrap_writel operations composing one 32-bit bus writing.
 898                  * Otherwise, we'll find the result fails on the lower 16-bit
 899                  * pwrap writing.
 900                  */
 901                 if (!msb)
 902                         pwrap_read(wrp, adr, &rdata);
 903         }
 904
 905         return 0;
 906 }
 907
 908 static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
 909 {
 910         return wrp->slave->pwrap_write(wrp, adr, wdata);
 911 }
 912
 913 static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
 914 {
 915         return pwrap_read(context, adr, rdata);
 916 }
 917
 918 static int pwrap_regmap_write(void *context, u32 adr, u32 wdata)
 919 {
 920         return pwrap_write(context, adr, wdata);
 921 }
 922
 923 static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
 924 {
 925         int ret, i;
 926
 927         pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN);
 928         pwrap_writel(wrp, 0, PWRAP_WRAP_EN);
 929         pwrap_writel(wrp, 1, PWRAP_MUX_SEL);
 930         pwrap_writel(wrp, 1, PWRAP_MAN_EN);
 931         pwrap_writel(wrp, 0, PWRAP_DIO_EN);
 932
 933         pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL,
 934                         PWRAP_MAN_CMD);
 935         pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
 936                         PWRAP_MAN_CMD);
 937         pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH,
 938                         PWRAP_MAN_CMD);
 939
 940         for (i = 0; i < 4; i++)
 941                 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
 942                                 PWRAP_MAN_CMD);
 943
 944         ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
 945         if (ret) {
 946                 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
 947                 return ret;
 948         }
 949
 950         pwrap_writel(wrp, 0, PWRAP_MAN_EN);
 951         pwrap_writel(wrp, 0, PWRAP_MUX_SEL);
 952
 953         return 0;
 954 }
 955
 956 /*
 957  * pwrap_init_sidly - configure serial input delay
 958  *
 959  * This configures the serial input delay. We can configure 0, 2, 4 or 6ns
 960  * delay. Do a read test with all possible values and chose the best delay.
 961  */
 962 static int pwrap_init_sidly(struct pmic_wrapper *wrp)
 963 {
 964         u32 rdata;
 965         u32 i;
 966         u32 pass = 0;
 967         signed char dly[16] = {
 968                 -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1
 969         };
 970
 971         for (i = 0; i < 4; i++) {
 972                 pwrap_writel(wrp, i, PWRAP_SIDLY);
 973                 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST],
 974                            &rdata);
 975                 if (rdata == PWRAP_DEW_READ_TEST_VAL) {
 976                         dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
 977                         pass |= 1 << i;
 978                 }
 979         }
 980
 981         if (dly[pass] < 0) {
 982                 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n",
 983                                 pass);
 984                 return -EIO;
 985         }
 986
 987         pwrap_writel(wrp, dly[pass], PWRAP_SIDLY);
 988
 989         return 0;
 990 }
 991
 992 static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
 993 {
 994         int ret;
 995         u32 rdata;
 996
 997         /* Enable dual IO mode */
 998         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
 999
1000         /* Check IDLE & INIT_DONE in advance */
1001         ret = pwrap_wait_for_state(wrp,
1002                                    pwrap_is_fsm_idle_and_sync_idle);
1003         if (ret) {
1004                 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1005                 return ret;
1006         }
1007
1008         pwrap_writel(wrp, 1, PWRAP_DIO_EN);
1009
1010         /* Read Test */
1011         pwrap_read(wrp,
1012                    wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
1013         if (rdata != PWRAP_DEW_READ_TEST_VAL) {
1014                 dev_err(wrp->dev,
1015                         "Read failed on DIO mode: 0x%04x!=0x%04x\n",
1016                         PWRAP_DEW_READ_TEST_VAL, rdata);
1017                 return -EFAULT;
1018         }
1019
1020         return 0;
1021 }
1022
1023 /*
1024  * pwrap_init_chip_select_ext is used to configure CS extension time for each
1025  * phase during data transactions on the pwrap bus.
1026  */
1027 static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
1028                                        u8 hext_read, u8 lext_start,
1029                                        u8 lext_end)
1030 {
1031         /*
1032          * After finishing a write and read transaction, extends CS high time
1033          * to be at least xT of BUS CLK as hext_write and hext_read specifies
1034          * respectively.
1035          */
1036         pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);
1037         pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);
1038
1039         /*
1040          * Extends CS low time after CSL and before CSH command to be at
1041          * least xT of BUS CLK as lext_start and lext_end specifies
1042          * respectively.
1043          */
1044         pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);
1045         pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);
1046 }
1047
1048 static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
1049 {
1050         switch (wrp->master->type) {
1051         case PWRAP_MT8173:
1052                 pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
1053                 break;
1054         case PWRAP_MT8135:
1055                 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
1056                 pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);
1057                 break;
1058         default:
1059                 break;
1060         }
1061
1062         return 0;
1063 }
1064
1065 static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
1066 {
1067         switch (wrp->slave->type) {
1068         case PMIC_MT6397:
1069                 pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
1070                 pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);
1071                 break;
1072
1073         case PMIC_MT6323:
1074                 pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
1075                 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
1076                             0x8);
1077                 pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);
1078                 break;
1079         default:
1080                 break;
1081         }
1082
1083         return 0;
1084 }
1085
1086 static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
1087 {
1088         return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
1089 }
1090
1091 static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
1092 {
1093         u32 rdata;
1094         int ret;
1095
1096         ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY],
1097                          &rdata);
1098         if (ret)
1099                 return 0;
1100
1101         return rdata == 1;
1102 }
1103
1104 static int pwrap_init_cipher(struct pmic_wrapper *wrp)
1105 {
1106         int ret;
1107         u32 rdata = 0;
1108
1109         pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
1110         pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
1111         pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
1112         pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
1113
1114         switch (wrp->master->type) {
1115         case PWRAP_MT8135:
1116                 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
1117                 pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
1118                 break;
1119         case PWRAP_MT2701:
1120         case PWRAP_MT6797:
1121         case PWRAP_MT8173:
1122                 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
1123                 break;
1124         case PWRAP_MT7622:
1125                 pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
1126                 break;
1127         }
1128
1129         /* Config cipher mode @PMIC */
1130         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
1131         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
1132         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
1133         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
1134
1135         switch (wrp->slave->type) {
1136         case PMIC_MT6397:
1137                 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD],
1138                             0x1);
1139                 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START],
1140                             0x1);
1141                 break;
1142         case PMIC_MT6323:
1143         case PMIC_MT6351:
1144                 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
1145                             0x1);
1146                 break;
1147         default:
1148                 break;
1149         }
1150
1151         /* wait for cipher data ready@AP */
1152         ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
1153         if (ret) {
1154                 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);
1155                 return ret;
1156         }
1157
1158         /* wait for cipher data ready@PMIC */
1159         ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready);
1160         if (ret) {
1161                 dev_err(wrp->dev,
1162                         "timeout waiting for cipher data ready@PMIC\n");
1163                 return ret;
1164         }
1165
1166         /* wait for cipher mode idle */
1167         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);
1168         ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
1169         if (ret) {
1170                 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
1171                 return ret;
1172         }
1173
1174         pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
1175
1176         /* Write Test */
1177         if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1178                         PWRAP_DEW_WRITE_TEST_VAL) ||
1179             pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1180                        &rdata) ||
1181             (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
1182                 dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
1183                 return -EFAULT;
1184         }
1185
1186         return 0;
1187 }
1188
1189 static int pwrap_init_security(struct pmic_wrapper *wrp)
1190 {
1191         int ret;
1192
1193         /* Enable encryption */
1194         ret = pwrap_init_cipher(wrp);
1195         if (ret)
1196                 return ret;
1197
1198         /* Signature checking - using CRC */
1199         if (pwrap_write(wrp,
1200                         wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
1201                 return -EFAULT;
1202
1203         pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
1204         pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
1205         pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
1206                      PWRAP_SIG_ADR);
1207         pwrap_writel(wrp,
1208                      wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
1209
1210         return 0;
1211 }
1212
1213 static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
1214 {
1215         /* enable pwrap events and pwrap bridge in AP side */
1216         pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN);
1217         pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN);
1218         writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
1219         writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
1220         writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
1221         writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
1222         writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
1223         writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
1224         writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
1225
1226         /* enable PMIC event out and sources */
1227         if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1228                         0x1) ||
1229             pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1230                         0xffff)) {
1231                 dev_err(wrp->dev, "enable dewrap fail\n");
1232                 return -EFAULT;
1233         }
1234
1235         return 0;
1236 }
1237
1238 static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
1239 {
1240         /* PMIC_DEWRAP enables */
1241         if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1242                         0x1) ||
1243             pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1244                         0xffff)) {
1245                 dev_err(wrp->dev, "enable dewrap fail\n");
1246                 return -EFAULT;
1247         }
1248
1249         return 0;
1250 }
1251
1252 static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
1253 {
1254         /* GPS_INTF initialization */
1255         switch (wrp->slave->type) {
1256         case PMIC_MT6323:
1257                 pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR);
1258                 pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD);
1259                 pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR);
1260                 pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1);
1261                 pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2);
1262                 break;
1263         default:
1264                 break;
1265         }
1266
1267         return 0;
1268 }
1269
1270 static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
1271 {
1272         pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
1273         /* enable 2wire SPI master */
1274         pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
1275
1276         return 0;
1277 }
1278
1279 static int pwrap_init(struct pmic_wrapper *wrp)
1280 {
1281         int ret;
1282
1283         reset_control_reset(wrp->rstc);
1284         if (wrp->rstc_bridge)
1285                 reset_control_reset(wrp->rstc_bridge);
1286
1287         if (wrp->master->type == PWRAP_MT8173) {
1288                 /* Enable DCM */
1289                 pwrap_writel(wrp, 3, PWRAP_DCM_EN);
1290                 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
1291         }
1292
1293         if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
1294                 /* Reset SPI slave */
1295                 ret = pwrap_reset_spislave(wrp);
1296                 if (ret)
1297                         return ret;
1298         }
1299
1300         pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
1301
1302         pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
1303
1304         pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
1305
1306         ret = wrp->master->init_reg_clock(wrp);
1307         if (ret)
1308                 return ret;
1309
1310         if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
1311                 /* Setup serial input delay */
1312                 ret = pwrap_init_sidly(wrp);
1313                 if (ret)
1314                         return ret;
1315         }
1316
1317         if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) {
1318                 /* Enable dual I/O mode */
1319                 ret = pwrap_init_dual_io(wrp);
1320                 if (ret)
1321                         return ret;
1322         }
1323
1324         if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) {
1325                 /* Enable security on bus */
1326                 ret = pwrap_init_security(wrp);
1327                 if (ret)
1328                         return ret;
1329         }
1330
1331         if (wrp->master->type == PWRAP_MT8135)
1332                 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
1333
1334         pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
1335         pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN);
1336         pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
1337         pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
1338         pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
1339
1340         if (wrp->master->init_soc_specific) {
1341                 ret = wrp->master->init_soc_specific(wrp);
1342                 if (ret)
1343                         return ret;
1344         }
1345
1346         /* Setup the init done registers */
1347         pwrap_writel(wrp, 1, PWRAP_INIT_DONE2);
1348         pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
1349         pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
1350
1351         if (wrp->master->has_bridge) {
1352                 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
1353                 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
1354         }
1355
1356         return 0;
1357 }
1358
1359 static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)
1360 {
1361         u32 rdata;
1362         struct pmic_wrapper *wrp = dev_id;
1363
1364         rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
1365
1366         dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
1367
1368         pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
1369
1370         return IRQ_HANDLED;
1371 }
1372
1373 static const struct regmap_config pwrap_regmap_config16 = {
1374         .reg_bits = 16,
1375         .val_bits = 16,
1376         .reg_stride = 2,
1377         .reg_read = pwrap_regmap_read,
1378         .reg_write = pwrap_regmap_write,
1379         .max_register = 0xffff,
1380 };
1381
1382 static const struct regmap_config pwrap_regmap_config32 = {
1383         .reg_bits = 32,
1384         .val_bits = 32,
1385         .reg_stride = 4,
1386         .reg_read = pwrap_regmap_read,
1387         .reg_write = pwrap_regmap_write,
1388         .max_register = 0xffff,
1389 };
1390
1391 static const struct pwrap_slv_type pmic_mt6323 = {
1392         .dew_regs = mt6323_regs,
1393         .type = PMIC_MT6323,
1394         .regmap = &pwrap_regmap_config16,
1395         .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
1396                 PWRAP_SLV_CAP_SECURITY,
1397         .pwrap_read = pwrap_read16,
1398         .pwrap_write = pwrap_write16,
1399 };
1400
1401 static const struct pwrap_slv_type pmic_mt6380 = {
1402         .dew_regs = NULL,
1403         .type = PMIC_MT6380,
1404         .regmap = &pwrap_regmap_config32,
1405         .caps = 0,
1406         .pwrap_read = pwrap_read32,
1407         .pwrap_write = pwrap_write32,
1408 };
1409
1410 static const struct pwrap_slv_type pmic_mt6397 = {
1411         .dew_regs = mt6397_regs,
1412         .type = PMIC_MT6397,
1413         .regmap = &pwrap_regmap_config16,
1414         .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
1415                 PWRAP_SLV_CAP_SECURITY,
1416         .pwrap_read = pwrap_read16,
1417         .pwrap_write = pwrap_write16,
1418 };
1419
1420 static const struct pwrap_slv_type pmic_mt6351 = {
1421         .dew_regs = mt6351_regs,
1422         .type = PMIC_MT6351,
1423         .regmap = &pwrap_regmap_config16,
1424         .caps = 0,
1425         .pwrap_read = pwrap_read16,
1426         .pwrap_write = pwrap_write16,
1427 };
1428
1429 static const struct of_device_id of_slave_match_tbl[] = {
1430         {
1431                 .compatible = "mediatek,mt6323",
1432                 .data = &pmic_mt6323,
1433         }, {
1434                 /* The MT6380 PMIC only implements a regulator, so we bind it
1435                  * directly instead of using a MFD.
1436                  */
1437                 .compatible = "mediatek,mt6380-regulator",
1438                 .data = &pmic_mt6380,
1439         }, {
1440                 .compatible = "mediatek,mt6397",
1441                 .data = &pmic_mt6397,
1442         }, {
1443                 .compatible = "mediatek,mt6351",
1444                 .data = &pmic_mt6351,
1445         }, {
1446                 /* sentinel */
1447         }
1448 };
1449 MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
1450
1451 static const struct pmic_wrapper_type pwrap_mt2701 = {
1452         .regs = mt2701_regs,
1453         .type = PWRAP_MT2701,
1454         .arb_en_all = 0x3f,
1455         .int_en_all = ~(u32)(BIT(31) | BIT(2)),
1456         .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
1457         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1458         .has_bridge = 0,
1459         .init_reg_clock = pwrap_mt2701_init_reg_clock,
1460         .init_soc_specific = pwrap_mt2701_init_soc_specific,
1461 };
1462
1463 static const struct pmic_wrapper_type pwrap_mt6797 = {
1464         .regs = mt6797_regs,
1465         .type = PWRAP_MT6797,
1466         .arb_en_all = 0x01fff,
1467         .int_en_all = 0xffffffc6,
1468         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1469         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1470         .has_bridge = 0,
1471         .init_reg_clock = pwrap_common_init_reg_clock,
1472         .init_soc_specific = NULL,
1473 };
1474
1475 static const struct pmic_wrapper_type pwrap_mt7622 = {
1476         .regs = mt7622_regs,
1477         .type = PWRAP_MT7622,
1478         .arb_en_all = 0xff,
1479         .int_en_all = ~(u32)BIT(31),
1480         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1481         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1482         .has_bridge = 0,
1483         .init_reg_clock = pwrap_common_init_reg_clock,
1484         .init_soc_specific = pwrap_mt7622_init_soc_specific,
1485 };
1486
1487 static const struct pmic_wrapper_type pwrap_mt8135 = {
1488         .regs = mt8135_regs,
1489         .type = PWRAP_MT8135,
1490         .arb_en_all = 0x1ff,
1491         .int_en_all = ~(u32)(BIT(31) | BIT(1)),
1492         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1493         .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1494         .has_bridge = 1,
1495         .init_reg_clock = pwrap_common_init_reg_clock,
1496         .init_soc_specific = pwrap_mt8135_init_soc_specific,
1497 };
1498
1499 static const struct pmic_wrapper_type pwrap_mt8173 = {
1500         .regs = mt8173_regs,
1501         .type = PWRAP_MT8173,
1502         .arb_en_all = 0x3f,
1503         .int_en_all = ~(u32)(BIT(31) | BIT(1)),
1504         .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1505         .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
1506         .has_bridge = 0,
1507         .init_reg_clock = pwrap_common_init_reg_clock,
1508         .init_soc_specific = pwrap_mt8173_init_soc_specific,
1509 };
1510
1511 static const struct of_device_id of_pwrap_match_tbl[] = {
1512         {
1513                 .compatible = "mediatek,mt2701-pwrap",
1514                 .data = &pwrap_mt2701,
1515         }, {
1516                 .compatible = "mediatek,mt6797-pwrap",
1517                 .data = &pwrap_mt6797,
1518         }, {
1519                 .compatible = "mediatek,mt7622-pwrap",
1520                 .data = &pwrap_mt7622,
1521         }, {
1522                 .compatible = "mediatek,mt8135-pwrap",
1523                 .data = &pwrap_mt8135,
1524         }, {
1525                 .compatible = "mediatek,mt8173-pwrap",
1526                 .data = &pwrap_mt8173,
1527         }, {
1528                 /* sentinel */
1529         }
1530 };
1531 MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
1532
1533 static int pwrap_probe(struct platform_device *pdev)
1534 {
1535         int ret, irq;
1536         struct pmic_wrapper *wrp;
1537         struct device_node *np = pdev->dev.of_node;
1538         const struct of_device_id *of_slave_id = NULL;
1539         struct resource *res;
1540
1541         if (np->child)
1542                 of_slave_id = of_match_node(of_slave_match_tbl, np->child);
1543
1544         if (!of_slave_id) {
1545                 dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n");
1546                 return -EINVAL;
1547         }
1548
1549         wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
1550         if (!wrp)
1551                 return -ENOMEM;
1552
1553         platform_set_drvdata(pdev, wrp);
1554
1555         wrp->master = of_device_get_match_data(&pdev->dev);
1556         wrp->slave = of_slave_id->data;
1557         wrp->dev = &pdev->dev;
1558
1559         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
1560         wrp->base = devm_ioremap_resource(wrp->dev, res);
1561         if (IS_ERR(wrp->base))
1562                 return PTR_ERR(wrp->base);
1563
1564         wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
1565         if (IS_ERR(wrp->rstc)) {
1566                 ret = PTR_ERR(wrp->rstc);
1567                 dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
1568                 return ret;
1569         }
1570
1571         if (wrp->master->has_bridge) {
1572                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1573                                 "pwrap-bridge");
1574                 wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
1575                 if (IS_ERR(wrp->bridge_base))
1576                         return PTR_ERR(wrp->bridge_base);
1577
1578                 wrp->rstc_bridge = devm_reset_control_get(wrp->dev,
1579                                                           "pwrap-bridge");
1580                 if (IS_ERR(wrp->rstc_bridge)) {
1581                         ret = PTR_ERR(wrp->rstc_bridge);
1582                         dev_dbg(wrp->dev,
1583                                 "cannot get pwrap-bridge reset: %d\n", ret);
1584                         return ret;
1585                 }
1586         }
1587
1588         wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
1589         if (IS_ERR(wrp->clk_spi)) {
1590                 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
1591                         PTR_ERR(wrp->clk_spi));
1592                 return PTR_ERR(wrp->clk_spi);
1593         }
1594
1595         wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
1596         if (IS_ERR(wrp->clk_wrap)) {
1597                 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
1598                         PTR_ERR(wrp->clk_wrap));
1599                 return PTR_ERR(wrp->clk_wrap);
1600         }
1601
1602         ret = clk_prepare_enable(wrp->clk_spi);
1603         if (ret)
1604                 return ret;
1605
1606         ret = clk_prepare_enable(wrp->clk_wrap);
1607         if (ret)
1608                 goto err_out1;
1609
1610         /* Enable internal dynamic clock */
1611         pwrap_writel(wrp, 1, PWRAP_DCM_EN);
1612         pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
1613
1614         /*
1615          * The PMIC could already be initialized by the bootloader.
1616          * Skip initialization here in this case.
1617          */
1618         if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) {
1619                 ret = pwrap_init(wrp);
1620                 if (ret) {
1621                         dev_dbg(wrp->dev, "init failed with %d\n", ret);
1622                         goto err_out2;
1623                 }
1624         }
1625
1626         if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_INIT_DONE0)) {
1627                 dev_dbg(wrp->dev, "initialization isn't finished\n");
1628                 ret = -ENODEV;
1629                 goto err_out2;
1630         }
1631
1632         /* Initialize watchdog, may not be done by the bootloader */
1633         pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
1634         /*
1635          * Since STAUPD was not used on mt8173 platform,
1636          * so STAUPD of WDT_SRC which should be turned off
1637          */
1638         pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN);
1639         pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
1640         pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
1641
1642         irq = platform_get_irq(pdev, 0);
1643         ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,
1644                                IRQF_TRIGGER_HIGH,
1645                                "mt-pmic-pwrap", wrp);
1646         if (ret)
1647                 goto err_out2;
1648
1649         wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regmap);
1650         if (IS_ERR(wrp->regmap)) {
1651                 ret = PTR_ERR(wrp->regmap);
1652                 goto err_out2;
1653         }
1654
1655         ret = of_platform_populate(np, NULL, NULL, wrp->dev);
1656         if (ret) {
1657                 dev_dbg(wrp->dev, "failed to create child devices at %pOF\n",
1658                                 np);
1659                 goto err_out2;
1660         }
1661
1662         return 0;
1663
1664 err_out2:
1665         clk_disable_unprepare(wrp->clk_wrap);
1666 err_out1:
1667         clk_disable_unprepare(wrp->clk_spi);
1668
1669         return ret;
1670 }
1671
1672 static struct platform_driver pwrap_drv = {
1673         .driver = {
1674                 .name = "mt-pmic-pwrap",
1675                 .of_match_table = of_match_ptr(of_pwrap_match_tbl),
1676         },
1677         .probe = pwrap_probe,
1678 };
1679
1680 module_platform_driver(pwrap_drv);
1681
1682 MODULE_AUTHOR("Flora Fu, MediaTek");
1683 MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver");
1684 MODULE_LICENSE("GPL v2");