2 * skl.c - Implementation of ASoC Intel SKL HD Audio driver
4 * Copyright (C) 2014-2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
7 * Derived mostly from Intel HDA driver with following copyrights:
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/platform_device.h>
28 #include <linux/firmware.h>
29 #include <linux/delay.h>
30 #include <sound/pcm.h>
31 #include <sound/soc-acpi.h>
32 #include <sound/soc-acpi-intel-match.h>
33 #include <sound/hda_register.h>
34 #include <sound/hdaudio.h>
35 #include <sound/hda_i915.h>
37 #include "skl-sst-dsp.h"
38 #include "skl-sst-ipc.h"
41 * initialize the PCI registers
43 static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg,
44 unsigned char mask, unsigned char val)
48 pci_read_config_byte(pci, reg, &data);
51 pci_write_config_byte(pci, reg, data);
54 static void skl_init_pci(struct skl *skl)
56 struct hdac_bus *bus = skl_to_bus(skl);
59 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
60 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
61 * Ensuring these bits are 0 clears playback static on some HD Audio
63 * The PCI register TCSEL is defined in the Intel manuals.
65 dev_dbg(bus->dev, "Clearing TCSEL\n");
66 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0);
69 static void update_pci_dword(struct pci_dev *pci,
70 unsigned int reg, u32 mask, u32 val)
74 pci_read_config_dword(pci, reg, &data);
77 pci_write_config_dword(pci, reg, data);
81 * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits
83 * @dev: device pointer
84 * @enable: enable/disable flag
86 static void skl_enable_miscbdcge(struct device *dev, bool enable)
88 struct pci_dev *pci = to_pci_dev(dev);
91 val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0;
93 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val);
97 * skl_clock_power_gating: Enable/Disable clock and power gating
99 * @dev: Device pointer
100 * @enable: Enable/Disable flag
102 static void skl_clock_power_gating(struct device *dev, bool enable)
104 struct pci_dev *pci = to_pci_dev(dev);
105 struct hdac_bus *bus = pci_get_drvdata(pci);
108 /* Update PDCGE bit of CGCTL register */
109 val = enable ? AZX_CGCTL_ADSPDCGE : 0;
110 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val);
112 /* Update L1SEN bit of EM2 register */
113 val = enable ? AZX_REG_VS_EM2_L1SEN : 0;
114 snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val);
116 /* Update ADSPPGD bit of PGCTL register */
117 val = enable ? 0 : AZX_PGCTL_ADSPPGD;
118 update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val);
122 * While performing reset, controller may not come back properly causing
123 * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset
124 * (init chip) and then again set CGCTL.MISCBDCGE to 1
126 static int skl_init_chip(struct hdac_bus *bus, bool full_reset)
128 struct hdac_ext_link *hlink;
131 skl_enable_miscbdcge(bus->dev, false);
132 ret = snd_hdac_bus_init_chip(bus, full_reset);
134 /* Reset stream-to-link mapping */
135 list_for_each_entry(hlink, &bus->hlink_list, list)
136 bus->io_ops->reg_writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
138 skl_enable_miscbdcge(bus->dev, true);
143 void skl_update_d0i3c(struct device *dev, bool enable)
145 struct pci_dev *pci = to_pci_dev(dev);
146 struct hdac_bus *bus = pci_get_drvdata(pci);
150 reg = snd_hdac_chip_readb(bus, VS_D0I3C);
151 /* Do not write to D0I3C until command in progress bit is cleared */
152 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) {
154 reg = snd_hdac_chip_readb(bus, VS_D0I3C);
157 /* Highly unlikely. But if it happens, flag error explicitly */
159 dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n");
164 reg = reg | AZX_REG_VS_D0I3C_I3;
166 reg = reg & (~AZX_REG_VS_D0I3C_I3);
168 snd_hdac_chip_writeb(bus, VS_D0I3C, reg);
171 /* Wait for cmd in progress to be cleared before exiting the function */
172 reg = snd_hdac_chip_readb(bus, VS_D0I3C);
173 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) {
175 reg = snd_hdac_chip_readb(bus, VS_D0I3C);
178 /* Highly unlikely. But if it happens, flag error explicitly */
180 dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n");
184 dev_dbg(bus->dev, "D0I3C register = 0x%x\n",
185 snd_hdac_chip_readb(bus, VS_D0I3C));
188 /* called from IRQ */
189 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr)
191 snd_pcm_period_elapsed(hstr->substream);
194 static irqreturn_t skl_interrupt(int irq, void *dev_id)
196 struct hdac_bus *bus = dev_id;
199 if (!pm_runtime_active(bus->dev))
202 spin_lock(&bus->reg_lock);
204 status = snd_hdac_chip_readl(bus, INTSTS);
205 if (status == 0 || status == 0xffffffff) {
206 spin_unlock(&bus->reg_lock);
211 status = snd_hdac_chip_readb(bus, RIRBSTS);
212 if (status & RIRB_INT_MASK) {
213 if (status & RIRB_INT_RESPONSE)
214 snd_hdac_bus_update_rirb(bus);
215 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
218 spin_unlock(&bus->reg_lock);
220 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
223 static irqreturn_t skl_threaded_handler(int irq, void *dev_id)
225 struct hdac_bus *bus = dev_id;
228 status = snd_hdac_chip_readl(bus, INTSTS);
230 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update);
235 static int skl_acquire_irq(struct hdac_bus *bus, int do_disconnect)
237 struct skl *skl = bus_to_skl(bus);
240 ret = request_threaded_irq(skl->pci->irq, skl_interrupt,
241 skl_threaded_handler,
243 KBUILD_MODNAME, bus);
246 "unable to grab IRQ %d, disabling device\n",
251 bus->irq = skl->pci->irq;
252 pci_intx(skl->pci, 1);
257 static int skl_suspend_late(struct device *dev)
259 struct pci_dev *pci = to_pci_dev(dev);
260 struct hdac_bus *bus = pci_get_drvdata(pci);
261 struct skl *skl = bus_to_skl(bus);
263 return skl_suspend_late_dsp(skl);
267 static int _skl_suspend(struct hdac_bus *bus)
269 struct skl *skl = bus_to_skl(bus);
270 struct pci_dev *pci = to_pci_dev(bus->dev);
273 snd_hdac_ext_bus_link_power_down_all(bus);
275 ret = skl_suspend_dsp(skl);
279 snd_hdac_bus_stop_chip(bus);
280 update_pci_dword(pci, AZX_PCIREG_PGCTL,
281 AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK);
282 skl_enable_miscbdcge(bus->dev, false);
283 snd_hdac_bus_enter_link_reset(bus);
284 skl_enable_miscbdcge(bus->dev, true);
285 skl_cleanup_resources(skl);
290 static int _skl_resume(struct hdac_bus *bus)
292 struct skl *skl = bus_to_skl(bus);
295 skl_init_chip(bus, true);
297 return skl_resume_dsp(skl);
301 #ifdef CONFIG_PM_SLEEP
305 static int skl_suspend(struct device *dev)
307 struct pci_dev *pci = to_pci_dev(dev);
308 struct hdac_bus *bus = pci_get_drvdata(pci);
309 struct skl *skl = bus_to_skl(bus);
313 * Do not suspend if streams which are marked ignore suspend are
314 * running, we need to save the state for these and continue
316 if (skl->supend_active) {
317 /* turn off the links and stop the CORB/RIRB DMA if it is On */
318 snd_hdac_ext_bus_link_power_down_all(bus);
320 if (bus->cmd_dma_state)
321 snd_hdac_bus_stop_cmd_io(bus);
323 enable_irq_wake(bus->irq);
326 ret = _skl_suspend(bus);
329 skl->skl_sst->fw_loaded = false;
332 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
333 ret = snd_hdac_display_power(bus, false);
336 "Cannot turn OFF display power on i915\n");
342 static int skl_resume(struct device *dev)
344 struct pci_dev *pci = to_pci_dev(dev);
345 struct hdac_bus *bus = pci_get_drvdata(pci);
346 struct skl *skl = bus_to_skl(bus);
347 struct hdac_ext_link *hlink = NULL;
350 /* Turned OFF in HDMI codec driver after codec reconfiguration */
351 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
352 ret = snd_hdac_display_power(bus, true);
355 "Cannot turn on display power on i915\n");
361 * resume only when we are not in suspend active, otherwise need to
364 if (skl->supend_active) {
365 pci_restore_state(pci);
366 snd_hdac_ext_bus_link_power_up_all(bus);
367 disable_irq_wake(bus->irq);
369 * turn On the links which are On before active suspend
370 * and start the CORB/RIRB DMA if On before
373 list_for_each_entry(hlink, &bus->hlink_list, list) {
374 if (hlink->ref_count)
375 snd_hdac_ext_bus_link_power_up(hlink);
379 if (bus->cmd_dma_state)
380 snd_hdac_bus_init_cmd_io(bus);
382 ret = _skl_resume(bus);
384 /* turn off the links which are off before suspend */
385 list_for_each_entry(hlink, &bus->hlink_list, list) {
386 if (!hlink->ref_count)
387 snd_hdac_ext_bus_link_power_down(hlink);
390 if (!bus->cmd_dma_state)
391 snd_hdac_bus_stop_cmd_io(bus);
396 #endif /* CONFIG_PM_SLEEP */
399 static int skl_runtime_suspend(struct device *dev)
401 struct pci_dev *pci = to_pci_dev(dev);
402 struct hdac_bus *bus = pci_get_drvdata(pci);
404 dev_dbg(bus->dev, "in %s\n", __func__);
406 return _skl_suspend(bus);
409 static int skl_runtime_resume(struct device *dev)
411 struct pci_dev *pci = to_pci_dev(dev);
412 struct hdac_bus *bus = pci_get_drvdata(pci);
414 dev_dbg(bus->dev, "in %s\n", __func__);
416 return _skl_resume(bus);
418 #endif /* CONFIG_PM */
420 static const struct dev_pm_ops skl_pm = {
421 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume)
422 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL)
423 .suspend_late = skl_suspend_late,
429 static int skl_free(struct hdac_bus *bus)
431 struct skl *skl = bus_to_skl(bus);
433 skl->init_done = 0; /* to be sure */
435 snd_hdac_ext_stop_streams(bus);
438 free_irq(bus->irq, (void *)bus);
439 snd_hdac_bus_free_stream_pages(bus);
440 snd_hdac_stream_free_all(bus);
441 snd_hdac_link_free_all(bus);
444 iounmap(bus->remap_addr);
446 pci_release_regions(skl->pci);
447 pci_disable_device(skl->pci);
449 snd_hdac_ext_bus_exit(bus);
451 cancel_work_sync(&skl->probe_work);
452 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
453 snd_hdac_i915_exit(bus);
459 * For each ssp there are 3 clocks (mclk/sclk/sclkfs).
460 * e.g. for ssp0, clocks will be named as
461 * "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs"
462 * So for skl+, there are 6 ssps, so 18 clocks will be created.
464 static struct skl_ssp_clk skl_ssp_clks[] = {
465 {.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"},
466 {.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"},
467 {.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"},
468 {.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"},
469 {.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"},
470 {.name = "ssp2_sclkfs"},
471 {.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"},
472 {.name = "ssp5_sclkfs"},
475 static int skl_find_machine(struct skl *skl, void *driver_data)
477 struct hdac_bus *bus = skl_to_bus(skl);
478 struct snd_soc_acpi_mach *mach = driver_data;
479 struct skl_machine_pdata *pdata;
481 mach = snd_soc_acpi_find_machine(mach);
483 dev_err(bus->dev, "No matching machine driver found\n");
488 skl->fw_name = mach->fw_filename;
492 skl->use_tplg_pcm = pdata->use_tplg_pcm;
493 pdata->dmic_num = skl_get_dmic_geo(skl);
499 static int skl_machine_device_register(struct skl *skl)
501 struct hdac_bus *bus = skl_to_bus(skl);
502 struct snd_soc_acpi_mach *mach = skl->mach;
503 struct platform_device *pdev;
506 pdev = platform_device_alloc(mach->drv_name, -1);
508 dev_err(bus->dev, "platform device alloc failed\n");
512 ret = platform_device_add(pdev);
514 dev_err(bus->dev, "failed to add machine device\n");
515 platform_device_put(pdev);
520 dev_set_drvdata(&pdev->dev, mach->pdata);
527 static void skl_machine_device_unregister(struct skl *skl)
530 platform_device_unregister(skl->i2s_dev);
533 static int skl_dmic_device_register(struct skl *skl)
535 struct hdac_bus *bus = skl_to_bus(skl);
536 struct platform_device *pdev;
539 /* SKL has one dmic port, so allocate dmic device for this */
540 pdev = platform_device_alloc("dmic-codec", -1);
542 dev_err(bus->dev, "failed to allocate dmic device\n");
546 ret = platform_device_add(pdev);
548 dev_err(bus->dev, "failed to add dmic device: %d\n", ret);
549 platform_device_put(pdev);
552 skl->dmic_dev = pdev;
557 static void skl_dmic_device_unregister(struct skl *skl)
560 platform_device_unregister(skl->dmic_dev);
563 static struct skl_clk_parent_src skl_clk_src[] = {
564 { .clk_id = SKL_XTAL, .name = "xtal" },
565 { .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 },
566 { .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 },
569 struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id)
573 for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) {
574 if (skl_clk_src[i].clk_id == clk_id)
575 return &skl_clk_src[i];
581 static void init_skl_xtal_rate(int pci_id)
586 skl_clk_src[0].rate = 24000000;
590 skl_clk_src[0].rate = 19200000;
595 static int skl_clock_device_register(struct skl *skl)
597 struct platform_device_info pdevinfo = {NULL};
598 struct skl_clk_pdata *clk_pdata;
600 clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata),
605 init_skl_xtal_rate(skl->pci->device);
607 clk_pdata->parent_clks = skl_clk_src;
608 clk_pdata->ssp_clks = skl_ssp_clks;
609 clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks);
611 /* Query NHLT to fill the rates and parent */
612 skl_get_clks(skl, clk_pdata->ssp_clks);
613 clk_pdata->pvt_data = skl;
615 /* Register Platform device */
616 pdevinfo.parent = &skl->pci->dev;
618 pdevinfo.name = "skl-ssp-clk";
619 pdevinfo.data = clk_pdata;
620 pdevinfo.size_data = sizeof(*clk_pdata);
621 skl->clk_dev = platform_device_register_full(&pdevinfo);
622 return PTR_ERR_OR_ZERO(skl->clk_dev);
625 static void skl_clock_device_unregister(struct skl *skl)
628 platform_device_unregister(skl->clk_dev);
632 * Probe the given codec address
634 static int probe_codec(struct hdac_bus *bus, int addr)
636 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
637 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
638 unsigned int res = -1;
639 struct skl *skl = bus_to_skl(bus);
640 struct hdac_device *hdev;
642 mutex_lock(&bus->cmd_mutex);
643 snd_hdac_bus_send_cmd(bus, cmd);
644 snd_hdac_bus_get_response(bus, addr, &res);
645 mutex_unlock(&bus->cmd_mutex);
648 dev_dbg(bus->dev, "codec #%d probed OK\n", addr);
650 hdev = devm_kzalloc(&skl->pci->dev, sizeof(*hdev), GFP_KERNEL);
654 return snd_hdac_ext_bus_device_init(bus, addr, hdev);
657 /* Codec initialization */
658 static void skl_codec_create(struct hdac_bus *bus)
662 max_slots = HDA_MAX_CODECS;
664 /* First try to probe all given codec slots */
665 for (c = 0; c < max_slots; c++) {
666 if ((bus->codec_mask & (1 << c))) {
667 if (probe_codec(bus, c) < 0) {
669 * Some BIOSen give you wrong codec addresses
673 "Codec #%d probe error; disabling it...\n", c);
674 bus->codec_mask &= ~(1 << c);
676 * More badly, accessing to a non-existing
677 * codec often screws up the controller bus,
678 * and disturbs the further communications.
679 * Thus if an error occurs during probing,
680 * better to reset the controller bus to get
681 * back to the sanity state.
683 snd_hdac_bus_stop_chip(bus);
684 skl_init_chip(bus, true);
690 static const struct hdac_bus_ops bus_core_ops = {
691 .command = snd_hdac_bus_send_cmd,
692 .get_response = snd_hdac_bus_get_response,
695 static int skl_i915_init(struct hdac_bus *bus)
700 * The HDMI codec is in GPU so we need to ensure that it is powered
701 * up and ready for probe
703 err = snd_hdac_i915_init(bus);
707 err = snd_hdac_display_power(bus, true);
709 dev_err(bus->dev, "Cannot turn on display power on i915\n");
714 static void skl_probe_work(struct work_struct *work)
716 struct skl *skl = container_of(work, struct skl, probe_work);
717 struct hdac_bus *bus = skl_to_bus(skl);
718 struct hdac_ext_link *hlink = NULL;
721 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
722 err = skl_i915_init(bus);
727 err = skl_init_chip(bus, true);
729 dev_err(bus->dev, "Init chip failed with err: %d\n", err);
733 /* codec detection */
734 if (!bus->codec_mask)
735 dev_info(bus->dev, "no hda codecs found!\n");
737 /* create codec instances */
738 skl_codec_create(bus);
740 /* register platform dai and controls */
741 err = skl_platform_register(bus->dev);
743 dev_err(bus->dev, "platform register failed: %d\n", err);
748 err = skl_machine_device_register(skl);
750 dev_err(bus->dev, "machine register failed: %d\n", err);
756 * we are done probing so decrement link counts
758 list_for_each_entry(hlink, &bus->hlink_list, list)
759 snd_hdac_ext_bus_link_put(bus, hlink);
761 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
762 err = snd_hdac_display_power(bus, false);
764 dev_err(bus->dev, "Cannot turn off display power on i915\n");
765 skl_machine_device_unregister(skl);
771 pm_runtime_put_noidle(bus->dev);
772 pm_runtime_allow(bus->dev);
778 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
779 err = snd_hdac_display_power(bus, false);
785 static int skl_create(struct pci_dev *pci,
786 const struct hdac_io_ops *io_ops,
790 struct hdac_bus *bus;
796 err = pci_enable_device(pci);
800 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL);
802 pci_disable_device(pci);
806 bus = skl_to_bus(skl);
807 snd_hdac_ext_bus_init(bus, &pci->dev, &bus_core_ops, io_ops, NULL);
810 INIT_WORK(&skl->probe_work, skl_probe_work);
811 bus->bdl_pos_adj = 0;
818 static int skl_first_init(struct hdac_bus *bus)
820 struct skl *skl = bus_to_skl(bus);
821 struct pci_dev *pci = skl->pci;
824 int cp_streams, pb_streams, start_idx;
826 err = pci_request_regions(pci, "Skylake HD audio");
830 bus->addr = pci_resource_start(pci, 0);
831 bus->remap_addr = pci_ioremap_bar(pci, 0);
832 if (bus->remap_addr == NULL) {
833 dev_err(bus->dev, "ioremap error\n");
837 snd_hdac_bus_reset_link(bus, true);
839 snd_hdac_bus_parse_capabilities(bus);
841 if (skl_acquire_irq(bus, 0) < 0)
845 synchronize_irq(bus->irq);
847 gcap = snd_hdac_chip_readw(bus, GCAP);
848 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap);
850 /* allow 64bit DMA address if supported by H/W */
851 if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) {
852 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64));
854 dma_set_mask(bus->dev, DMA_BIT_MASK(32));
855 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32));
858 /* read number of streams from GCAP register */
859 cp_streams = (gcap >> 8) & 0x0f;
860 pb_streams = (gcap >> 12) & 0x0f;
862 if (!pb_streams && !cp_streams)
865 bus->num_streams = cp_streams + pb_streams;
867 /* initialize streams */
868 snd_hdac_ext_stream_init_all
869 (bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE);
870 start_idx = cp_streams;
871 snd_hdac_ext_stream_init_all
872 (bus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK);
874 err = snd_hdac_bus_alloc_stream_pages(bus);
878 /* initialize chip */
881 return skl_init_chip(bus, true);
884 static int skl_probe(struct pci_dev *pci,
885 const struct pci_device_id *pci_id)
888 struct hdac_bus *bus = NULL;
891 /* we use ext core ops, so provide NULL for ops here */
892 err = skl_create(pci, NULL, &skl);
896 bus = skl_to_bus(skl);
898 err = skl_first_init(bus);
902 skl->pci_id = pci->device;
904 device_disable_async_suspend(bus->dev);
906 skl->nhlt = skl_nhlt_init(bus->dev);
908 if (skl->nhlt == NULL) {
913 err = skl_nhlt_create_sysfs(skl);
917 skl_nhlt_update_topology_bin(skl);
919 pci_set_drvdata(skl->pci, bus);
921 /* check if dsp is there */
923 /* create device for dsp clk */
924 err = skl_clock_device_register(skl);
928 err = skl_find_machine(skl, (void *)pci_id->driver_data);
932 err = skl_init_dsp(skl);
934 dev_dbg(bus->dev, "error failed to register dsp\n");
937 skl->skl_sst->enable_miscbdcge = skl_enable_miscbdcge;
938 skl->skl_sst->clock_power_gating = skl_clock_power_gating;
941 snd_hdac_ext_bus_get_ml_capabilities(bus);
943 snd_hdac_bus_stop_chip(bus);
945 /* create device for soc dmic */
946 err = skl_dmic_device_register(skl);
950 schedule_work(&skl->probe_work);
957 skl_clock_device_unregister(skl);
959 skl_nhlt_free(skl->nhlt);
966 static void skl_shutdown(struct pci_dev *pci)
968 struct hdac_bus *bus = pci_get_drvdata(pci);
969 struct hdac_stream *s;
970 struct hdac_ext_stream *stream;
976 skl = bus_to_skl(bus);
981 snd_hdac_ext_stop_streams(bus);
982 list_for_each_entry(s, &bus->stream_list, list) {
983 stream = stream_to_hdac_ext_stream(s);
984 snd_hdac_ext_stream_decouple(bus, stream, false);
987 snd_hdac_bus_stop_chip(bus);
990 static void skl_remove(struct pci_dev *pci)
992 struct hdac_bus *bus = pci_get_drvdata(pci);
993 struct skl *skl = bus_to_skl(bus);
995 release_firmware(skl->tplg);
997 pm_runtime_get_noresume(&pci->dev);
999 /* codec removal, invoke bus_device_remove */
1000 snd_hdac_ext_bus_device_remove(bus);
1002 skl->debugfs = NULL;
1003 skl_platform_unregister(&pci->dev);
1005 skl_machine_device_unregister(skl);
1006 skl_dmic_device_unregister(skl);
1007 skl_clock_device_unregister(skl);
1008 skl_nhlt_remove_sysfs(skl);
1009 skl_nhlt_free(skl->nhlt);
1011 dev_set_drvdata(&pci->dev, NULL);
1015 static const struct pci_device_id skl_ids[] = {
1016 /* Sunrise Point-LP */
1017 { PCI_DEVICE(0x8086, 0x9d70),
1018 .driver_data = (unsigned long)&snd_soc_acpi_intel_skl_machines},
1020 { PCI_DEVICE(0x8086, 0x5a98),
1021 .driver_data = (unsigned long)&snd_soc_acpi_intel_bxt_machines},
1023 { PCI_DEVICE(0x8086, 0x9D71),
1024 .driver_data = (unsigned long)&snd_soc_acpi_intel_kbl_machines},
1026 { PCI_DEVICE(0x8086, 0x3198),
1027 .driver_data = (unsigned long)&snd_soc_acpi_intel_glk_machines},
1029 { PCI_DEVICE(0x8086, 0x9dc8),
1030 .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
1033 MODULE_DEVICE_TABLE(pci, skl_ids);
1035 /* pci_driver definition */
1036 static struct pci_driver skl_driver = {
1037 .name = KBUILD_MODNAME,
1038 .id_table = skl_ids,
1040 .remove = skl_remove,
1041 .shutdown = skl_shutdown,
1046 module_pci_driver(skl_driver);
1048 MODULE_LICENSE("GPL v2");
1049 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver");