2 * skl-ssp-clk.h - Skylake ssp clock information and ipc structure
4 * Copyright (C) 2017 Intel Corp
5 * Author: Jaikrishna Nemallapudi <jaikrishnax.nemallapudi@intel.com>
6 * Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
22 #ifndef SOUND_SOC_SKL_SSP_CLK_H
23 #define SOUND_SOC_SKL_SSP_CLK_H
26 /* xtal/cardinal/pll, parent of ssp clocks and mclk */
27 #define SKL_MAX_CLK_SRC 3
28 #define SKL_MAX_SSP_CLK_TYPES 3 /* mclk, sclk, sclkfs */
30 #define SKL_MAX_CLK_CNT (SKL_MAX_SSP * SKL_MAX_SSP_CLK_TYPES)
32 /* Max number of configurations supported for each clock */
33 #define SKL_MAX_CLK_RATES 10
35 #define SKL_SCLK_OFS SKL_MAX_SSP
36 #define SKL_SCLKFS_OFS (SKL_SCLK_OFS + SKL_MAX_SSP)
44 enum skl_clk_src_type {
50 struct skl_clk_parent_src {
54 const char *parent_name;
62 struct skl_dmactrl_mclk_cfg {
63 struct skl_tlv_hdr hdr;
64 /* DMA Clk TLV params */
69 u32 clk_stop_delay:16;
75 struct skl_dmactrl_sclkfs_cfg {
76 struct skl_tlv_hdr hdr;
77 /* DMA SClk&FS TLV params */
78 u32 sampling_frequency;
82 u32 interleaving_style;
83 u32 number_of_channels : 8;
84 u32 valid_bit_depth : 8;
89 union skl_clk_ctrl_ipc {
90 struct skl_dmactrl_mclk_cfg mclk;
91 struct skl_dmactrl_sclkfs_cfg sclk_fs;
94 struct skl_clk_rate_cfg_table {
96 union skl_clk_ctrl_ipc dma_ctl_ipc;
101 * rate for mclk will be in rates[0]. For sclk and sclkfs, rates[] store
102 * all possible clocks ssp can generate for that platform.
106 const char *parent_name;
107 struct skl_clk_rate_cfg_table rate_cfg[SKL_MAX_CLK_RATES];
110 struct skl_clk_pdata {
111 struct skl_clk_parent_src *parent_clks;
113 struct skl_ssp_clk *ssp_clks;
117 #endif /* SOUND_SOC_SKL_SSP_CLK_H */