1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 SiFive, Inc.
4 * Copyright (C) 2020 Zong Li
7 #include <linux/clkdev.h>
8 #include <linux/delay.h>
10 #include <linux/module.h>
12 #include "sifive-prci.h"
13 #include "fu540-prci.h"
14 #include "fu740-prci.h"
21 * __prci_readl() - read from a PRCI register
23 * @offs: register offset to read from (in bytes, from PRCI base address)
25 * Read the register located at offset @offs from the base virtual
26 * address of the PRCI register target described by @pd, and return
27 * the value to the caller.
29 * Context: Any context.
31 * Return: the contents of the register described by @pd and @offs.
33 static u32 __prci_readl(struct __prci_data *pd, u32 offs)
35 return readl_relaxed(pd->va + offs);
38 static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
40 writel_relaxed(v, pd->va + offs);
43 /* WRPLL-related private functions */
46 * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
47 * @c: ptr to a struct wrpll_cfg record to write config into
48 * @r: value read from the PRCI PLL configuration register
50 * Given a value @r read from an FU740 PRCI PLL configuration register,
51 * split it into fields and populate it into the WRPLL configuration record
54 * The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros
55 * have the same register layout.
57 * Context: Any context.
59 static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r)
63 v = r & PRCI_COREPLLCFG0_DIVR_MASK;
64 v >>= PRCI_COREPLLCFG0_DIVR_SHIFT;
67 v = r & PRCI_COREPLLCFG0_DIVF_MASK;
68 v >>= PRCI_COREPLLCFG0_DIVF_SHIFT;
71 v = r & PRCI_COREPLLCFG0_DIVQ_MASK;
72 v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT;
75 v = r & PRCI_COREPLLCFG0_RANGE_MASK;
76 v >>= PRCI_COREPLLCFG0_RANGE_SHIFT;
80 (WRPLL_FLAGS_INT_FEEDBACK_MASK | WRPLL_FLAGS_EXT_FEEDBACK_MASK);
82 /* external feedback mode not supported */
83 c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;
87 * __prci_wrpll_pack() - pack PLL configuration parameters into a register value
88 * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg
90 * Using a set of WRPLL configuration values pointed to by @c,
91 * assemble a PRCI PLL configuration register value, and return it to
94 * Context: Any context. Caller must ensure that the contents of the
95 * record pointed to by @c do not change during the execution
98 * Returns: a value suitable for writing into a PRCI PLL configuration
101 static u32 __prci_wrpll_pack(const struct wrpll_cfg *c)
105 r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT;
106 r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT;
107 r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;
108 r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT;
110 /* external feedback mode not supported */
111 r |= PRCI_COREPLLCFG0_FSE_MASK;
117 * __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI
119 * @pwd: PRCI WRPLL metadata
121 * Read the current configuration of the PLL identified by @pwd from
122 * the PRCI identified by @pd, and store it into the local configuration
125 * Context: Any context. Caller must prevent the records pointed to by
126 * @pd and @pwd from changing during execution.
128 static void __prci_wrpll_read_cfg0(struct __prci_data *pd,
129 struct __prci_wrpll_data *pwd)
131 __prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));
135 * __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI
137 * @pwd: PRCI WRPLL metadata
138 * @c: WRPLL configuration record to write
140 * Write the WRPLL configuration described by @c into the WRPLL
141 * configuration register identified by @pwd in the PRCI instance
142 * described by @c. Make a cached copy of the WRPLL's current
143 * configuration so it can be used by other code.
145 * Context: Any context. Caller must prevent the records pointed to by
146 * @pd and @pwd from changing during execution.
148 static void __prci_wrpll_write_cfg0(struct __prci_data *pd,
149 struct __prci_wrpll_data *pwd,
152 __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
154 memcpy(&pwd->c, c, sizeof(*c));
158 * __prci_wrpll_write_cfg1() - write Clock enable/disable configuration
161 * @pwd: PRCI WRPLL metadata
162 * @enable: Clock enable or disable value
164 static void __prci_wrpll_write_cfg1(struct __prci_data *pd,
165 struct __prci_wrpll_data *pwd,
168 __prci_writel(enable, pwd->cfg1_offs, pd);
172 * Linux clock framework integration
174 * See the Linux clock framework documentation for more information on
178 unsigned long sifive_prci_wrpll_recalc_rate(struct clk_hw *hw,
179 unsigned long parent_rate)
181 struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
182 struct __prci_wrpll_data *pwd = pc->pwd;
184 return wrpll_calc_output_rate(&pwd->c, parent_rate);
187 long sifive_prci_wrpll_round_rate(struct clk_hw *hw,
189 unsigned long *parent_rate)
191 struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
192 struct __prci_wrpll_data *pwd = pc->pwd;
195 memcpy(&c, &pwd->c, sizeof(c));
197 wrpll_configure_for_rate(&c, rate, *parent_rate);
199 return wrpll_calc_output_rate(&c, *parent_rate);
202 int sifive_prci_wrpll_set_rate(struct clk_hw *hw,
203 unsigned long rate, unsigned long parent_rate)
205 struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
206 struct __prci_wrpll_data *pwd = pc->pwd;
207 struct __prci_data *pd = pc->pd;
210 r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
214 if (pwd->enable_bypass)
215 pwd->enable_bypass(pd);
217 __prci_wrpll_write_cfg0(pd, pwd, &pwd->c);
219 udelay(wrpll_calc_max_lock_us(&pwd->c));
224 int sifive_clk_is_enabled(struct clk_hw *hw)
226 struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
227 struct __prci_wrpll_data *pwd = pc->pwd;
228 struct __prci_data *pd = pc->pd;
231 r = __prci_readl(pd, pwd->cfg1_offs);
233 if (r & PRCI_COREPLLCFG1_CKE_MASK)
239 int sifive_prci_clock_enable(struct clk_hw *hw)
241 struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
242 struct __prci_wrpll_data *pwd = pc->pwd;
243 struct __prci_data *pd = pc->pd;
245 if (sifive_clk_is_enabled(hw))
248 __prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK);
250 if (pwd->disable_bypass)
251 pwd->disable_bypass(pd);
256 void sifive_prci_clock_disable(struct clk_hw *hw)
258 struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
259 struct __prci_wrpll_data *pwd = pc->pwd;
260 struct __prci_data *pd = pc->pd;
263 if (pwd->enable_bypass)
264 pwd->enable_bypass(pd);
266 r = __prci_readl(pd, pwd->cfg1_offs);
267 r &= ~PRCI_COREPLLCFG1_CKE_MASK;
269 __prci_wrpll_write_cfg1(pd, pwd, r);
272 /* TLCLKSEL clock integration */
274 unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw,
275 unsigned long parent_rate)
277 struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
278 struct __prci_data *pd = pc->pd;
282 v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);
283 v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK;
286 return div_u64(parent_rate, div);
289 /* HFPCLK clock integration */
291 unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk_hw *hw,
292 unsigned long parent_rate)
294 struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
295 struct __prci_data *pd = pc->pd;
296 u32 div = __prci_readl(pd, PRCI_HFPCLKPLLDIV_OFFSET);
298 return div_u64(parent_rate, div + 2);
302 * Core clock mux control
306 * sifive_prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
307 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
309 * Switch the CORECLK mux to the HFCLK input source; return once complete.
311 * Context: Any context. Caller must prevent concurrent changes to the
312 * PRCI_CORECLKSEL_OFFSET register.
314 void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd)
318 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
319 r |= PRCI_CORECLKSEL_CORECLKSEL_MASK;
320 __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
322 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
326 * sifive_prci_coreclksel_use_corepll() - switch the CORECLK mux to output
328 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
330 * Switch the CORECLK mux to the COREPLL output clock; return once complete.
332 * Context: Any context. Caller must prevent concurrent changes to the
333 * PRCI_CORECLKSEL_OFFSET register.
335 void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd)
339 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
340 r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;
341 __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
343 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
347 * sifive_prci_coreclksel_use_final_corepll() - switch the CORECLK mux to output
349 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
351 * Switch the CORECLK mux to the final COREPLL output clock; return once
354 * Context: Any context. Caller must prevent concurrent changes to the
355 * PRCI_CORECLKSEL_OFFSET register.
357 void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd)
361 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
362 r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;
363 __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
365 r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
369 * sifive_prci_corepllsel_use_dvfscorepll() - switch the COREPLL mux to
370 * output DVFS_COREPLL
371 * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
373 * Switch the COREPLL mux to the DVFSCOREPLL output clock; return once complete.
375 * Context: Any context. Caller must prevent concurrent changes to the
376 * PRCI_COREPLLSEL_OFFSET register.
378 void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd)
382 r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);
383 r |= PRCI_COREPLLSEL_COREPLLSEL_MASK;
384 __prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd);
386 r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */
390 * sifive_prci_corepllsel_use_corepll() - switch the COREPLL mux to
392 * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
394 * Switch the COREPLL mux to the COREPLL output clock; return once complete.
396 * Context: Any context. Caller must prevent concurrent changes to the
397 * PRCI_COREPLLSEL_OFFSET register.
399 void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd)
403 r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);
404 r &= ~PRCI_COREPLLSEL_COREPLLSEL_MASK;
405 __prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd);
407 r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */
411 * sifive_prci_hfpclkpllsel_use_hfclk() - switch the HFPCLKPLL mux to
413 * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
415 * Switch the HFPCLKPLL mux to the HFCLK input source; return once complete.
417 * Context: Any context. Caller must prevent concurrent changes to the
418 * PRCI_HFPCLKPLLSEL_OFFSET register.
420 void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd)
424 r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);
425 r |= PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK;
426 __prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd);
428 r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */
432 * sifive_prci_hfpclkpllsel_use_hfpclkpll() - switch the HFPCLKPLL mux to
434 * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
436 * Switch the HFPCLKPLL mux to the HFPCLKPLL output clock; return once complete.
438 * Context: Any context. Caller must prevent concurrent changes to the
439 * PRCI_HFPCLKPLLSEL_OFFSET register.
441 void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd)
445 r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);
446 r &= ~PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK;
447 __prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd);
449 r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */
452 /* PCIE AUX clock APIs for enable, disable. */
453 int sifive_prci_pcie_aux_clock_is_enabled(struct clk_hw *hw)
455 struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
456 struct __prci_data *pd = pc->pd;
459 r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET);
461 if (r & PRCI_PCIE_AUX_EN_MASK)
467 int sifive_prci_pcie_aux_clock_enable(struct clk_hw *hw)
469 struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
470 struct __prci_data *pd = pc->pd;
471 u32 r __maybe_unused;
473 if (sifive_prci_pcie_aux_clock_is_enabled(hw))
476 __prci_writel(1, PRCI_PCIE_AUX_OFFSET, pd);
477 r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); /* barrier */
482 void sifive_prci_pcie_aux_clock_disable(struct clk_hw *hw)
484 struct __prci_clock *pc = clk_hw_to_prci_clock(hw);
485 struct __prci_data *pd = pc->pd;
486 u32 r __maybe_unused;
488 __prci_writel(0, PRCI_PCIE_AUX_OFFSET, pd);
489 r = __prci_readl(pd, PRCI_PCIE_AUX_OFFSET); /* barrier */
494 * __prci_register_clocks() - register clock controls in the PRCI
495 * @dev: Linux struct device
496 * @pd: The pointer for PRCI per-device instance data
497 * @desc: The pointer for the information of clocks of each SoCs
499 * Register the list of clock controls described in __prci_init_clocks[] with
500 * the Linux clock framework.
502 * Return: 0 upon success or a negative error code upon failure.
504 static int __prci_register_clocks(struct device *dev, struct __prci_data *pd,
505 const struct prci_clk_desc *desc)
507 struct clk_init_data init = { };
508 struct __prci_clock *pic;
509 int parent_count, i, r;
511 parent_count = of_clk_get_parent_count(dev->of_node);
512 if (parent_count != EXPECTED_CLK_PARENT_COUNT) {
513 dev_err(dev, "expected only two parent clocks, found %d\n",
519 for (i = 0; i < desc->num_clks; ++i) {
520 pic = &(desc->clks[i]);
522 init.name = pic->name;
523 init.parent_names = &pic->parent_name;
524 init.num_parents = 1;
526 pic->hw.init = &init;
531 __prci_wrpll_read_cfg0(pd, pic->pwd);
533 r = devm_clk_hw_register(dev, &pic->hw);
535 dev_warn(dev, "Failed to register clock %s: %d\n",
540 r = clk_hw_register_clkdev(&pic->hw, pic->name, dev_name(dev));
542 dev_warn(dev, "Failed to register clkdev for %s: %d\n",
547 pd->hw_clks.hws[i] = &pic->hw;
552 r = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
555 dev_err(dev, "could not add hw_provider: %d\n", r);
563 * sifive_prci_probe() - initialize prci data and check parent count
564 * @pdev: platform device pointer for the prci
566 * Return: 0 upon success or a negative error code upon failure.
568 static int sifive_prci_probe(struct platform_device *pdev)
570 struct device *dev = &pdev->dev;
571 struct __prci_data *pd;
572 const struct prci_clk_desc *desc;
575 desc = of_device_get_match_data(&pdev->dev);
577 pd = devm_kzalloc(dev, struct_size(pd, hw_clks.hws, desc->num_clks), GFP_KERNEL);
581 pd->va = devm_platform_ioremap_resource(pdev, 0);
583 return PTR_ERR(pd->va);
585 pd->reset.rcdev.owner = THIS_MODULE;
586 pd->reset.rcdev.nr_resets = PRCI_RST_NR;
587 pd->reset.rcdev.ops = &reset_simple_ops;
588 pd->reset.rcdev.of_node = pdev->dev.of_node;
589 pd->reset.active_low = true;
590 pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET;
591 spin_lock_init(&pd->reset.lock);
593 r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev);
595 dev_err(dev, "could not register reset controller: %d\n", r);
598 r = __prci_register_clocks(dev, pd, desc);
600 dev_err(dev, "could not register clocks: %d\n", r);
604 dev_dbg(dev, "SiFive PRCI probed\n");
609 static const struct of_device_id sifive_prci_of_match[] = {
610 {.compatible = "sifive,fu540-c000-prci", .data = &prci_clk_fu540},
611 {.compatible = "sifive,fu740-c000-prci", .data = &prci_clk_fu740},
615 static struct platform_driver sifive_prci_driver = {
617 .name = "sifive-clk-prci",
618 .of_match_table = sifive_prci_of_match,
620 .probe = sifive_prci_probe,
622 module_platform_driver(sifive_prci_driver);
624 MODULE_AUTHOR("Paul Walmsley <paul.walmsley@sifive.com>");
625 MODULE_DESCRIPTION("SiFive Power Reset Clock Interface (PRCI) driver");
626 MODULE_LICENSE("GPL");