4 * Copyright (C) 2009, 2011 Renesas Solutions Corp.
6 * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/platform_device.h>
13 #include <linux/init.h>
14 #include <linux/serial.h>
15 #include <linux/serial_sci.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/sh_timer.h>
20 #include <linux/sh_dma.h>
21 #include <linux/sh_intc.h>
22 #include <linux/usb/ohci_pdriver.h>
23 #include <cpu/dma-register.h>
24 #include <cpu/sh7757.h>
26 static struct plat_sci_port scif2_platform_data = {
31 static struct resource scif2_resources[] = {
32 DEFINE_RES_MEM(0xfe4b0000, 0x100), /* SCIF2 */
33 DEFINE_RES_IRQ(evt2irq(0x700)),
36 static struct platform_device scif2_device = {
39 .resource = scif2_resources,
40 .num_resources = ARRAY_SIZE(scif2_resources),
42 .platform_data = &scif2_platform_data,
46 static struct plat_sci_port scif3_platform_data = {
51 static struct resource scif3_resources[] = {
52 DEFINE_RES_MEM(0xfe4c0000, 0x100), /* SCIF3 */
53 DEFINE_RES_IRQ(evt2irq(0xb80)),
56 static struct platform_device scif3_device = {
59 .resource = scif3_resources,
60 .num_resources = ARRAY_SIZE(scif3_resources),
62 .platform_data = &scif3_platform_data,
66 static struct plat_sci_port scif4_platform_data = {
71 static struct resource scif4_resources[] = {
72 DEFINE_RES_MEM(0xfe4d0000, 0x100), /* SCIF4 */
73 DEFINE_RES_IRQ(evt2irq(0xf00)),
76 static struct platform_device scif4_device = {
79 .resource = scif4_resources,
80 .num_resources = ARRAY_SIZE(scif4_resources),
82 .platform_data = &scif4_platform_data,
86 static struct sh_timer_config tmu0_platform_data = {
90 static struct resource tmu0_resources[] = {
91 DEFINE_RES_MEM(0xfe430000, 0x20),
92 DEFINE_RES_IRQ(evt2irq(0x580)),
93 DEFINE_RES_IRQ(evt2irq(0x5a0)),
96 static struct platform_device tmu0_device = {
100 .platform_data = &tmu0_platform_data,
102 .resource = tmu0_resources,
103 .num_resources = ARRAY_SIZE(tmu0_resources),
106 static struct resource spi0_resources[] = {
110 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
113 .start = evt2irq(0xcc0),
114 .flags = IORESOURCE_IRQ,
119 static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = {
121 .slave_id = SHDMA_SLAVE_SDHI_TX,
123 .chcr = SM_INC | RS_ERS | 0x40000000 |
124 TS_INDEX2VAL(XMIT_SZ_16BIT),
128 .slave_id = SHDMA_SLAVE_SDHI_RX,
130 .chcr = DM_INC | RS_ERS | 0x40000000 |
131 TS_INDEX2VAL(XMIT_SZ_16BIT),
135 .slave_id = SHDMA_SLAVE_MMCIF_TX,
137 .chcr = SM_INC | RS_ERS | 0x40000000 |
138 TS_INDEX2VAL(XMIT_SZ_32BIT),
142 .slave_id = SHDMA_SLAVE_MMCIF_RX,
144 .chcr = DM_INC | RS_ERS | 0x40000000 |
145 TS_INDEX2VAL(XMIT_SZ_32BIT),
150 static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = {
152 .slave_id = SHDMA_SLAVE_SCIF2_TX,
154 .chcr = SM_INC | RS_ERS | 0x40000000 |
155 TS_INDEX2VAL(XMIT_SZ_8BIT),
159 .slave_id = SHDMA_SLAVE_SCIF2_RX,
161 .chcr = DM_INC | RS_ERS | 0x40000000 |
162 TS_INDEX2VAL(XMIT_SZ_8BIT),
166 .slave_id = SHDMA_SLAVE_SCIF3_TX,
168 .chcr = SM_INC | RS_ERS | 0x40000000 |
169 TS_INDEX2VAL(XMIT_SZ_8BIT),
173 .slave_id = SHDMA_SLAVE_SCIF3_RX,
175 .chcr = DM_INC | RS_ERS | 0x40000000 |
176 TS_INDEX2VAL(XMIT_SZ_8BIT),
180 .slave_id = SHDMA_SLAVE_SCIF4_TX,
182 .chcr = SM_INC | RS_ERS | 0x40000000 |
183 TS_INDEX2VAL(XMIT_SZ_8BIT),
187 .slave_id = SHDMA_SLAVE_SCIF4_RX,
189 .chcr = DM_INC | RS_ERS | 0x40000000 |
190 TS_INDEX2VAL(XMIT_SZ_8BIT),
194 .slave_id = SHDMA_SLAVE_RSPI_TX,
196 .chcr = SM_INC | RS_ERS | 0x40000000 |
197 TS_INDEX2VAL(XMIT_SZ_16BIT),
201 .slave_id = SHDMA_SLAVE_RSPI_RX,
203 .chcr = DM_INC | RS_ERS | 0x40000000 |
204 TS_INDEX2VAL(XMIT_SZ_16BIT),
209 static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = {
211 .slave_id = SHDMA_SLAVE_RIIC0_TX,
213 .chcr = SM_INC | RS_ERS | 0x40000000 |
214 TS_INDEX2VAL(XMIT_SZ_8BIT),
218 .slave_id = SHDMA_SLAVE_RIIC0_RX,
220 .chcr = DM_INC | RS_ERS | 0x40000000 |
221 TS_INDEX2VAL(XMIT_SZ_8BIT),
225 .slave_id = SHDMA_SLAVE_RIIC1_TX,
227 .chcr = SM_INC | RS_ERS | 0x40000000 |
228 TS_INDEX2VAL(XMIT_SZ_8BIT),
232 .slave_id = SHDMA_SLAVE_RIIC1_RX,
234 .chcr = DM_INC | RS_ERS | 0x40000000 |
235 TS_INDEX2VAL(XMIT_SZ_8BIT),
239 .slave_id = SHDMA_SLAVE_RIIC2_TX,
241 .chcr = SM_INC | RS_ERS | 0x40000000 |
242 TS_INDEX2VAL(XMIT_SZ_8BIT),
246 .slave_id = SHDMA_SLAVE_RIIC2_RX,
248 .chcr = DM_INC | RS_ERS | 0x40000000 |
249 TS_INDEX2VAL(XMIT_SZ_8BIT),
253 .slave_id = SHDMA_SLAVE_RIIC3_TX,
255 .chcr = SM_INC | RS_ERS | 0x40000000 |
256 TS_INDEX2VAL(XMIT_SZ_8BIT),
260 .slave_id = SHDMA_SLAVE_RIIC3_RX,
262 .chcr = DM_INC | RS_ERS | 0x40000000 |
263 TS_INDEX2VAL(XMIT_SZ_8BIT),
267 .slave_id = SHDMA_SLAVE_RIIC4_TX,
269 .chcr = SM_INC | RS_ERS | 0x40000000 |
270 TS_INDEX2VAL(XMIT_SZ_8BIT),
274 .slave_id = SHDMA_SLAVE_RIIC4_RX,
276 .chcr = DM_INC | RS_ERS | 0x40000000 |
277 TS_INDEX2VAL(XMIT_SZ_8BIT),
282 static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = {
284 .slave_id = SHDMA_SLAVE_RIIC5_TX,
286 .chcr = SM_INC | RS_ERS | 0x40000000 |
287 TS_INDEX2VAL(XMIT_SZ_8BIT),
291 .slave_id = SHDMA_SLAVE_RIIC5_RX,
293 .chcr = DM_INC | RS_ERS | 0x40000000 |
294 TS_INDEX2VAL(XMIT_SZ_8BIT),
298 .slave_id = SHDMA_SLAVE_RIIC6_TX,
300 .chcr = SM_INC | RS_ERS | 0x40000000 |
301 TS_INDEX2VAL(XMIT_SZ_8BIT),
305 .slave_id = SHDMA_SLAVE_RIIC6_RX,
307 .chcr = DM_INC | RS_ERS | 0x40000000 |
308 TS_INDEX2VAL(XMIT_SZ_8BIT),
312 .slave_id = SHDMA_SLAVE_RIIC7_TX,
314 .chcr = SM_INC | RS_ERS | 0x40000000 |
315 TS_INDEX2VAL(XMIT_SZ_8BIT),
319 .slave_id = SHDMA_SLAVE_RIIC7_RX,
321 .chcr = DM_INC | RS_ERS | 0x40000000 |
322 TS_INDEX2VAL(XMIT_SZ_8BIT),
326 .slave_id = SHDMA_SLAVE_RIIC8_TX,
328 .chcr = SM_INC | RS_ERS | 0x40000000 |
329 TS_INDEX2VAL(XMIT_SZ_8BIT),
333 .slave_id = SHDMA_SLAVE_RIIC8_RX,
335 .chcr = DM_INC | RS_ERS | 0x40000000 |
336 TS_INDEX2VAL(XMIT_SZ_8BIT),
340 .slave_id = SHDMA_SLAVE_RIIC9_TX,
342 .chcr = SM_INC | RS_ERS | 0x40000000 |
343 TS_INDEX2VAL(XMIT_SZ_8BIT),
347 .slave_id = SHDMA_SLAVE_RIIC9_RX,
349 .chcr = DM_INC | RS_ERS | 0x40000000 |
350 TS_INDEX2VAL(XMIT_SZ_8BIT),
355 static const struct sh_dmae_channel sh7757_dmae_channels[] = {
383 static const unsigned int ts_shift[] = TS_SHIFT;
385 static struct sh_dmae_pdata dma0_platform_data = {
386 .slave = sh7757_dmae0_slaves,
387 .slave_num = ARRAY_SIZE(sh7757_dmae0_slaves),
388 .channel = sh7757_dmae_channels,
389 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
390 .ts_low_shift = CHCR_TS_LOW_SHIFT,
391 .ts_low_mask = CHCR_TS_LOW_MASK,
392 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
393 .ts_high_mask = CHCR_TS_HIGH_MASK,
394 .ts_shift = ts_shift,
395 .ts_shift_num = ARRAY_SIZE(ts_shift),
396 .dmaor_init = DMAOR_INIT,
399 static struct sh_dmae_pdata dma1_platform_data = {
400 .slave = sh7757_dmae1_slaves,
401 .slave_num = ARRAY_SIZE(sh7757_dmae1_slaves),
402 .channel = sh7757_dmae_channels,
403 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
404 .ts_low_shift = CHCR_TS_LOW_SHIFT,
405 .ts_low_mask = CHCR_TS_LOW_MASK,
406 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
407 .ts_high_mask = CHCR_TS_HIGH_MASK,
408 .ts_shift = ts_shift,
409 .ts_shift_num = ARRAY_SIZE(ts_shift),
410 .dmaor_init = DMAOR_INIT,
413 static struct sh_dmae_pdata dma2_platform_data = {
414 .slave = sh7757_dmae2_slaves,
415 .slave_num = ARRAY_SIZE(sh7757_dmae2_slaves),
416 .channel = sh7757_dmae_channels,
417 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
418 .ts_low_shift = CHCR_TS_LOW_SHIFT,
419 .ts_low_mask = CHCR_TS_LOW_MASK,
420 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
421 .ts_high_mask = CHCR_TS_HIGH_MASK,
422 .ts_shift = ts_shift,
423 .ts_shift_num = ARRAY_SIZE(ts_shift),
424 .dmaor_init = DMAOR_INIT,
427 static struct sh_dmae_pdata dma3_platform_data = {
428 .slave = sh7757_dmae3_slaves,
429 .slave_num = ARRAY_SIZE(sh7757_dmae3_slaves),
430 .channel = sh7757_dmae_channels,
431 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
432 .ts_low_shift = CHCR_TS_LOW_SHIFT,
433 .ts_low_mask = CHCR_TS_LOW_MASK,
434 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
435 .ts_high_mask = CHCR_TS_HIGH_MASK,
436 .ts_shift = ts_shift,
437 .ts_shift_num = ARRAY_SIZE(ts_shift),
438 .dmaor_init = DMAOR_INIT,
442 static struct resource sh7757_dmae0_resources[] = {
444 /* Channel registers and DMAOR */
447 .flags = IORESOURCE_MEM,
453 .flags = IORESOURCE_MEM,
457 .start = evt2irq(0x640),
458 .end = evt2irq(0x640),
459 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
463 /* channel 6 to 11 */
464 static struct resource sh7757_dmae1_resources[] = {
466 /* Channel registers and DMAOR */
469 .flags = IORESOURCE_MEM,
475 .flags = IORESOURCE_MEM,
479 .start = evt2irq(0x640),
480 .end = evt2irq(0x640),
481 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
484 /* IRQ for channels 4 */
485 .start = evt2irq(0x7c0),
486 .end = evt2irq(0x7c0),
487 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
490 /* IRQ for channels 5 */
491 .start = evt2irq(0x7c0),
492 .end = evt2irq(0x7c0),
493 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
496 /* IRQ for channels 6 */
497 .start = evt2irq(0xd00),
498 .end = evt2irq(0xd00),
499 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
502 /* IRQ for channels 7 */
503 .start = evt2irq(0xd00),
504 .end = evt2irq(0xd00),
505 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
508 /* IRQ for channels 8 */
509 .start = evt2irq(0xd00),
510 .end = evt2irq(0xd00),
511 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
514 /* IRQ for channels 9 */
515 .start = evt2irq(0xd00),
516 .end = evt2irq(0xd00),
517 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
520 /* IRQ for channels 10 */
521 .start = evt2irq(0xd00),
522 .end = evt2irq(0xd00),
523 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
526 /* IRQ for channels 11 */
527 .start = evt2irq(0xd00),
528 .end = evt2irq(0xd00),
529 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
533 /* channel 12 to 17 */
534 static struct resource sh7757_dmae2_resources[] = {
536 /* Channel registers and DMAOR */
539 .flags = IORESOURCE_MEM,
545 .flags = IORESOURCE_MEM,
549 .start = evt2irq(0x2a60),
550 .end = evt2irq(0x2a60),
551 .flags = IORESOURCE_IRQ,
554 /* IRQ for channels 12 to 16 */
555 .start = evt2irq(0x2400),
556 .end = evt2irq(0x2480),
557 .flags = IORESOURCE_IRQ,
560 /* IRQ for channel 17 */
561 .start = evt2irq(0x24e0),
562 .end = evt2irq(0x24e0),
563 .flags = IORESOURCE_IRQ,
567 /* channel 18 to 23 */
568 static struct resource sh7757_dmae3_resources[] = {
570 /* Channel registers and DMAOR */
573 .flags = IORESOURCE_MEM,
579 .flags = IORESOURCE_MEM,
583 .start = evt2irq(0x2a80),
584 .end = evt2irq(0x2a80),
585 .flags = IORESOURCE_IRQ,
588 /* IRQ for channels 18 to 22 */
589 .start = evt2irq(0x2500),
590 .end = evt2irq(0x2580),
591 .flags = IORESOURCE_IRQ,
594 /* IRQ for channel 23 */
595 .start = evt2irq(0x2600),
596 .end = evt2irq(0x2600),
597 .flags = IORESOURCE_IRQ,
601 static struct platform_device dma0_device = {
602 .name = "sh-dma-engine",
604 .resource = sh7757_dmae0_resources,
605 .num_resources = ARRAY_SIZE(sh7757_dmae0_resources),
607 .platform_data = &dma0_platform_data,
611 static struct platform_device dma1_device = {
612 .name = "sh-dma-engine",
614 .resource = sh7757_dmae1_resources,
615 .num_resources = ARRAY_SIZE(sh7757_dmae1_resources),
617 .platform_data = &dma1_platform_data,
621 static struct platform_device dma2_device = {
622 .name = "sh-dma-engine",
624 .resource = sh7757_dmae2_resources,
625 .num_resources = ARRAY_SIZE(sh7757_dmae2_resources),
627 .platform_data = &dma2_platform_data,
631 static struct platform_device dma3_device = {
632 .name = "sh-dma-engine",
634 .resource = sh7757_dmae3_resources,
635 .num_resources = ARRAY_SIZE(sh7757_dmae3_resources),
637 .platform_data = &dma3_platform_data,
641 static struct platform_device spi0_device = {
646 .coherent_dma_mask = 0xffffffff,
648 .num_resources = ARRAY_SIZE(spi0_resources),
649 .resource = spi0_resources,
652 static struct resource spi1_resources[] = {
656 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
659 .start = evt2irq(0x8c0),
660 .flags = IORESOURCE_IRQ,
664 static struct platform_device spi1_device = {
667 .num_resources = ARRAY_SIZE(spi1_resources),
668 .resource = spi1_resources,
671 static struct resource rspi_resources[] = {
675 .flags = IORESOURCE_MEM,
678 .start = evt2irq(0x1d80),
679 .flags = IORESOURCE_IRQ,
683 static struct platform_device rspi_device = {
686 .num_resources = ARRAY_SIZE(rspi_resources),
687 .resource = rspi_resources,
690 static struct resource usb_ehci_resources[] = {
694 .flags = IORESOURCE_MEM,
697 .start = evt2irq(0x920),
698 .end = evt2irq(0x920),
699 .flags = IORESOURCE_IRQ,
703 static struct platform_device usb_ehci_device = {
707 .dma_mask = &usb_ehci_device.dev.coherent_dma_mask,
708 .coherent_dma_mask = DMA_BIT_MASK(32),
710 .num_resources = ARRAY_SIZE(usb_ehci_resources),
711 .resource = usb_ehci_resources,
714 static struct resource usb_ohci_resources[] = {
718 .flags = IORESOURCE_MEM,
721 .start = evt2irq(0x920),
722 .end = evt2irq(0x920),
723 .flags = IORESOURCE_IRQ,
727 static struct usb_ohci_pdata usb_ohci_pdata;
729 static struct platform_device usb_ohci_device = {
730 .name = "ohci-platform",
733 .dma_mask = &usb_ohci_device.dev.coherent_dma_mask,
734 .coherent_dma_mask = DMA_BIT_MASK(32),
735 .platform_data = &usb_ohci_pdata,
737 .num_resources = ARRAY_SIZE(usb_ohci_resources),
738 .resource = usb_ohci_resources,
741 static struct platform_device *sh7757_devices[] __initdata = {
757 static int __init sh7757_devices_setup(void)
759 return platform_add_devices(sh7757_devices,
760 ARRAY_SIZE(sh7757_devices));
762 arch_initcall(sh7757_devices_setup);
764 static struct platform_device *sh7757_early_devices[] __initdata = {
771 void __init plat_early_device_setup(void)
773 early_platform_add_devices(sh7757_early_devices,
774 ARRAY_SIZE(sh7757_early_devices));
780 /* interrupt sources */
782 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
783 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
784 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
785 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
787 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
788 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
789 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
790 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
791 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
794 IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15,
795 TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
798 DMAC0_5, DMAC6_7, DMAC8_11,
799 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4,
805 LPC, LPC5, LPC6, LPC7, LPC8,
806 PECI0, PECI1, PECI2, PECI3, PECI4, PECI5,
810 IIC0_0, IIC0_1, IIC0_2, IIC0_3,
811 IIC1_0, IIC1_1, IIC1_2, IIC1_3,
812 IIC2_0, IIC2_1, IIC2_2, IIC2_3,
813 IIC3_0, IIC3_1, IIC3_2, IIC3_3,
814 IIC4_0, IIC4_1, IIC4_2, IIC4_3,
815 IIC5_0, IIC5_1, IIC5_2, IIC5_3,
816 IIC6_0, IIC6_1, IIC6_2, IIC6_3,
817 IIC7_0, IIC7_1, IIC7_2, IIC7_3,
818 IIC8_0, IIC8_1, IIC8_2, IIC8_3,
819 IIC9_0, IIC9_1, IIC9_2, IIC9_3,
827 DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19,
828 DMINT20, DMINT21, DMINT22, DMINT23,
832 WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B,
833 GETHER0, GETHER1, GETHER2,
838 /* interrupt groups */
843 static struct intc_vect vectors[] __initdata = {
844 INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
845 INTC_VECT(SDHI, 0x4c0),
846 INTC_VECT(DVC, 0x4e0),
847 INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
848 INTC_VECT(IRQ10, 0x540),
849 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
850 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
851 INTC_VECT(HUDI, 0x600),
852 INTC_VECT(ARC4, 0x620),
853 INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660),
854 INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0),
855 INTC_VECT(DMAC0_5, 0x6c0),
856 INTC_VECT(IRQ11, 0x6e0),
857 INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
858 INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
859 INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0),
860 INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0),
861 INTC_VECT(USB0, 0x840),
862 INTC_VECT(IRQ12, 0x880),
863 INTC_VECT(JMC, 0x8a0),
864 INTC_VECT(SPI1, 0x8c0),
865 INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900),
866 INTC_VECT(USB1, 0x920),
867 INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
868 INTC_VECT(TMR45, 0xa40),
869 INTC_VECT(FRT, 0xa80),
870 INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
871 INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
872 INTC_VECT(LPC, 0xb20),
873 INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
874 INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
875 INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
876 INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20),
877 INTC_VECT(PECI2, 0xc40),
878 INTC_VECT(IRQ15, 0xc60),
879 INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
880 INTC_VECT(SPI0, 0xcc0),
881 INTC_VECT(ADC1, 0xce0),
882 INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20),
883 INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60),
884 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
885 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
886 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
887 INTC_VECT(TMU5, 0xe40),
888 INTC_VECT(ADC0, 0xe60),
889 INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20),
890 INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60),
891 INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420),
892 INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460),
893 INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0),
894 INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520),
895 INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560),
896 INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600),
897 INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640),
898 INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700),
899 INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800),
900 INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840),
901 INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
902 INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
903 INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
904 INTC_VECT(IIC6_2, 0x1920),
905 INTC_VECT(ONFICTL, 0x1960),
906 INTC_VECT(IIC6_3, 0x1980),
907 INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
908 INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
909 INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
910 INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
911 INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
912 INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
913 INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80),
914 INTC_VECT(ECCU, 0x1cc0),
915 INTC_VECT(PCIC, 0x1ce0),
916 INTC_VECT(G200, 0x1d00),
917 INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0),
918 INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0),
919 INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0),
920 INTC_VECT(PECI5, 0x1f00),
921 INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0),
922 INTC_VECT(SGPIO, 0x1fc0),
923 INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420),
924 INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460),
925 INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0),
926 INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520),
927 INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560),
928 INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600),
929 INTC_VECT(DDRECC, 0x2620),
930 INTC_VECT(TSIP, 0x2640),
931 INTC_VECT(PCIE_BRIDGE, 0x27c0),
932 INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820),
933 INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860),
934 INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0),
935 INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0),
936 INTC_VECT(WDT8B, 0x2900),
937 INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980),
938 INTC_VECT(GETHER2, 0x29a0),
939 INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20),
940 INTC_VECT(PBIC, 0x2a40),
941 INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80),
942 INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40),
943 INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80),
944 INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20),
947 static struct intc_group groups[] __initdata = {
948 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
949 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
952 static struct intc_mask_reg mask_registers[] __initdata = {
953 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
954 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
956 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
957 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
958 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
959 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
960 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
961 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
962 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
963 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
964 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
966 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
967 { 0, 0, 0, 0, 0, 0, 0, 0,
968 0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45,
969 TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5,
970 HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012
973 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
974 { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
975 IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
976 ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1,
977 ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
980 { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
981 { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0,
982 0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
983 IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
984 IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2
987 { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */
988 { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2,
989 IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
990 PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3,
991 IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
994 { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */
995 { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0,
996 0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC,
997 PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP,
998 DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22
1001 { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */
1002 { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0,
1003 DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0,
1004 0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8,
1005 DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17
1009 #define INTPRI 0xffd00010
1010 #define INT2PRI0 0xffd40000
1011 #define INT2PRI1 0xffd40004
1012 #define INT2PRI2 0xffd40008
1013 #define INT2PRI3 0xffd4000c
1014 #define INT2PRI4 0xffd40010
1015 #define INT2PRI5 0xffd40014
1016 #define INT2PRI6 0xffd40018
1017 #define INT2PRI7 0xffd4001c
1018 #define INT2PRI8 0xffd400a0
1019 #define INT2PRI9 0xffd400a4
1020 #define INT2PRI10 0xffd400a8
1021 #define INT2PRI11 0xffd400ac
1022 #define INT2PRI12 0xffd400b0
1023 #define INT2PRI13 0xffd400b4
1024 #define INT2PRI14 0xffd400b8
1025 #define INT2PRI15 0xffd400bc
1026 #define INT2PRI16 0xffd10000
1027 #define INT2PRI17 0xffd10004
1028 #define INT2PRI18 0xffd10008
1029 #define INT2PRI19 0xffd1000c
1030 #define INT2PRI20 0xffd10010
1031 #define INT2PRI21 0xffd10014
1032 #define INT2PRI22 0xffd10018
1033 #define INT2PRI23 0xffd1001c
1034 #define INT2PRI24 0xffd100a0
1035 #define INT2PRI25 0xffd100a4
1036 #define INT2PRI26 0xffd100a8
1037 #define INT2PRI27 0xffd100ac
1038 #define INT2PRI28 0xffd100b0
1039 #define INT2PRI29 0xffd100b4
1040 #define INT2PRI30 0xffd100b8
1041 #define INT2PRI31 0xffd100bc
1042 #define INT2PRI32 0xffd20000
1043 #define INT2PRI33 0xffd20004
1044 #define INT2PRI34 0xffd20008
1045 #define INT2PRI35 0xffd2000c
1046 #define INT2PRI36 0xffd20010
1047 #define INT2PRI37 0xffd20014
1048 #define INT2PRI38 0xffd20018
1049 #define INT2PRI39 0xffd2001c
1050 #define INT2PRI40 0xffd200a0
1051 #define INT2PRI41 0xffd200a4
1052 #define INT2PRI42 0xffd200a8
1053 #define INT2PRI43 0xffd200ac
1054 #define INT2PRI44 0xffd200b0
1055 #define INT2PRI45 0xffd200b4
1056 #define INT2PRI46 0xffd200b8
1057 #define INT2PRI47 0xffd200bc
1059 static struct intc_prio_reg prio_registers[] __initdata = {
1060 { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
1061 IRQ4, IRQ5, IRQ6, IRQ7 } },
1063 { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
1064 { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
1065 { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } },
1066 { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } },
1067 { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
1068 { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } },
1069 { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } },
1070 { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
1071 { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
1072 { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
1073 { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } },
1074 { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } },
1075 { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
1076 { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
1078 { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
1079 { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } },
1080 { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
1081 { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
1082 { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
1083 { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
1084 { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } },
1085 { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } },
1086 { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } },
1087 { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
1088 { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } },
1089 { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } },
1090 { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } },
1091 { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
1092 { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } },
1093 { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
1094 { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } },
1095 { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } },
1096 { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } },
1097 { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } },
1098 { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } },
1099 { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } },
1100 { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } },
1101 { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } },
1102 { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } },
1103 { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } },
1104 { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } },
1105 { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } },
1106 { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } },
1107 { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } },
1108 { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } },
1109 { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } },
1112 static struct intc_sense_reg sense_registers_irq8to15[] __initdata = {
1113 { 0xffd100f8, 32, 2, /* ICR2 */ { IRQ15, IRQ14, IRQ13, IRQ12,
1114 IRQ11, IRQ10, IRQ9, IRQ8 } },
1117 static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
1118 mask_registers, prio_registers,
1119 sense_registers_irq8to15);
1121 /* Support for external interrupt pins in IRQ mode */
1122 static struct intc_vect vectors_irq0123[] __initdata = {
1123 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
1124 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
1127 static struct intc_vect vectors_irq4567[] __initdata = {
1128 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
1129 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
1132 static struct intc_sense_reg sense_registers[] __initdata = {
1133 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
1134 IRQ4, IRQ5, IRQ6, IRQ7 } },
1137 static struct intc_mask_reg ack_registers[] __initdata = {
1138 { 0xffd00024, 0, 32, /* INTREQ */
1139 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1142 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123",
1143 vectors_irq0123, NULL, mask_registers,
1144 prio_registers, sense_registers, ack_registers);
1146 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567",
1147 vectors_irq4567, NULL, mask_registers,
1148 prio_registers, sense_registers, ack_registers);
1150 /* External interrupt pins in IRL mode */
1151 static struct intc_vect vectors_irl0123[] __initdata = {
1152 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
1153 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
1154 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
1155 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
1156 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
1157 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
1158 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
1159 INTC_VECT(IRL0_HHHL, 0x3c0),
1162 static struct intc_vect vectors_irl4567[] __initdata = {
1163 INTC_VECT(IRL4_LLLL, 0x200), INTC_VECT(IRL4_LLLH, 0x220),
1164 INTC_VECT(IRL4_LLHL, 0x240), INTC_VECT(IRL4_LLHH, 0x260),
1165 INTC_VECT(IRL4_LHLL, 0x280), INTC_VECT(IRL4_LHLH, 0x2a0),
1166 INTC_VECT(IRL4_LHHL, 0x2c0), INTC_VECT(IRL4_LHHH, 0x2e0),
1167 INTC_VECT(IRL4_HLLL, 0x300), INTC_VECT(IRL4_HLLH, 0x320),
1168 INTC_VECT(IRL4_HLHL, 0x340), INTC_VECT(IRL4_HLHH, 0x360),
1169 INTC_VECT(IRL4_HHLL, 0x380), INTC_VECT(IRL4_HHLH, 0x3a0),
1170 INTC_VECT(IRL4_HHHL, 0x3c0),
1173 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
1174 NULL, mask_registers, NULL, NULL);
1176 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
1177 NULL, mask_registers, NULL, NULL);
1179 #define INTC_ICR0 0xffd00000
1180 #define INTC_INTMSK0 0xffd00044
1181 #define INTC_INTMSK1 0xffd00048
1182 #define INTC_INTMSK2 0xffd40080
1183 #define INTC_INTMSKCLR1 0xffd00068
1184 #define INTC_INTMSKCLR2 0xffd40084
1186 void __init plat_irq_setup(void)
1188 /* disable IRQ3-0 + IRQ7-4 */
1189 __raw_writel(0xff000000, INTC_INTMSK0);
1191 /* disable IRL3-0 + IRL7-4 */
1192 __raw_writel(0xc0000000, INTC_INTMSK1);
1193 __raw_writel(0xfffefffe, INTC_INTMSK2);
1195 /* select IRL mode for IRL3-0 + IRL7-4 */
1196 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
1198 /* disable holding function, ie enable "SH-4 Mode" */
1199 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
1201 register_intc_controller(&intc_desc);
1204 void __init plat_irq_setup_pins(int mode)
1207 case IRQ_MODE_IRQ7654:
1208 /* select IRQ mode for IRL7-4 */
1209 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
1210 register_intc_controller(&intc_desc_irq4567);
1212 case IRQ_MODE_IRQ3210:
1213 /* select IRQ mode for IRL3-0 */
1214 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
1215 register_intc_controller(&intc_desc_irq0123);
1217 case IRQ_MODE_IRL7654:
1218 /* enable IRL7-4 but don't provide any masking */
1219 __raw_writel(0x40000000, INTC_INTMSKCLR1);
1220 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
1222 case IRQ_MODE_IRL3210:
1223 /* enable IRL0-3 but don't provide any masking */
1224 __raw_writel(0x80000000, INTC_INTMSKCLR1);
1225 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
1227 case IRQ_MODE_IRL7654_MASK:
1228 /* enable IRL7-4 and mask using cpu intc controller */
1229 __raw_writel(0x40000000, INTC_INTMSKCLR1);
1230 register_intc_controller(&intc_desc_irl4567);
1232 case IRQ_MODE_IRL3210_MASK:
1233 /* enable IRL0-3 and mask using cpu intc controller */
1234 __raw_writel(0x80000000, INTC_INTMSKCLR1);
1235 register_intc_controller(&intc_desc_irl0123);
1242 void __init plat_mem_setup(void)