4 * Copyright (C) 2006 Paul Mundt
5 * Copyright (C) 2009 Magnus Damm
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/platform_device.h>
12 #include <linux/init.h>
13 #include <linux/serial.h>
14 #include <linux/serial_sci.h>
15 #include <linux/sh_timer.h>
16 #include <linux/sh_intc.h>
19 static struct plat_sci_port scif0_platform_data = {
24 static struct resource scif0_resources[] = {
25 DEFINE_RES_MEM(0xffe80000, 0x100),
26 DEFINE_RES_IRQ(evt2irq(0x700)),
27 DEFINE_RES_IRQ(evt2irq(0x720)),
28 DEFINE_RES_IRQ(evt2irq(0x760)),
29 DEFINE_RES_IRQ(evt2irq(0x740)),
32 static struct platform_device scif0_device = {
35 .resource = scif0_resources,
36 .num_resources = ARRAY_SIZE(scif0_resources),
38 .platform_data = &scif0_platform_data,
42 static struct sh_timer_config tmu0_platform_data = {
46 static struct resource tmu0_resources[] = {
47 DEFINE_RES_MEM(0xffd80000, 0x30),
48 DEFINE_RES_IRQ(evt2irq(0x400)),
49 DEFINE_RES_IRQ(evt2irq(0x420)),
50 DEFINE_RES_IRQ(evt2irq(0x440)),
53 static struct platform_device tmu0_device = {
57 .platform_data = &tmu0_platform_data,
59 .resource = tmu0_resources,
60 .num_resources = ARRAY_SIZE(tmu0_resources),
63 static struct platform_device *sh4202_devices[] __initdata = {
68 static int __init sh4202_devices_setup(void)
70 return platform_add_devices(sh4202_devices,
71 ARRAY_SIZE(sh4202_devices));
73 arch_initcall(sh4202_devices_setup);
75 static struct platform_device *sh4202_early_devices[] __initdata = {
80 void __init plat_early_device_setup(void)
82 early_platform_add_devices(sh4202_early_devices,
83 ARRAY_SIZE(sh4202_early_devices));
89 /* interrupt sources */
90 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
91 HUDI, TMU0, TMU1, TMU2, RTC, SCIF, WDT,
94 static struct intc_vect vectors[] __initdata = {
95 INTC_VECT(HUDI, 0x600),
96 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
97 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
98 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
99 INTC_VECT(RTC, 0x4c0),
100 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
101 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
102 INTC_VECT(WDT, 0x560),
105 static struct intc_prio_reg prio_registers[] __initdata = {
106 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
107 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, 0, 0, 0 } },
108 { 0xffd0000c, 0, 16, 4, /* IPRC */ { 0, 0, SCIF, HUDI } },
109 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
112 static DECLARE_INTC_DESC(intc_desc, "sh4-202", vectors, NULL,
113 NULL, prio_registers, NULL);
115 static struct intc_vect vectors_irlm[] __initdata = {
116 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
117 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
120 static DECLARE_INTC_DESC(intc_desc_irlm, "sh4-202_irlm", vectors_irlm, NULL,
121 NULL, prio_registers, NULL);
123 void __init plat_irq_setup(void)
125 register_intc_controller(&intc_desc);
128 #define INTC_ICR 0xffd00000UL
129 #define INTC_ICR_IRLM (1<<7)
131 void __init plat_irq_setup_pins(int mode)
134 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
135 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
136 register_intc_controller(&intc_desc_irlm);