2 * arch/xtensa/kernel/setup.c
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1995 Linus Torvalds
9 * Copyright (C) 2001 - 2005 Tensilica Inc.
10 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
12 * Chris Zankel <chris@zankel.net>
13 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
15 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
18 #include <linux/errno.h>
19 #include <linux/init.h>
21 #include <linux/proc_fs.h>
22 #include <linux/screen_info.h>
23 #include <linux/kernel.h>
24 #include <linux/percpu.h>
25 #include <linux/cpu.h>
27 #include <linux/of_fdt.h>
29 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
30 # include <linux/console.h>
34 # include <linux/seq_file.h>
37 #include <asm/bootparam.h>
38 #include <asm/kasan.h>
39 #include <asm/mmu_context.h>
40 #include <asm/pgtable.h>
41 #include <asm/processor.h>
42 #include <asm/timex.h>
43 #include <asm/platform.h>
45 #include <asm/setup.h>
46 #include <asm/param.h>
48 #include <asm/sysmem.h>
50 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
51 struct screen_info screen_info = {
54 .orig_video_cols = 80,
55 .orig_video_lines = 24,
56 .orig_video_isVGA = 1,
57 .orig_video_points = 16,
61 #ifdef CONFIG_BLK_DEV_INITRD
62 extern unsigned long initrd_start;
63 extern unsigned long initrd_end;
64 extern int initrd_below_start_ok;
68 void *dtb_start = __dtb_start;
71 extern unsigned long loops_per_jiffy;
73 /* Command line specified as configuration option. */
75 static char __initdata command_line[COMMAND_LINE_SIZE];
77 #ifdef CONFIG_CMDLINE_BOOL
78 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
81 #ifdef CONFIG_PARSE_BOOTPARAM
83 * Boot parameter parsing.
85 * The Xtensa port uses a list of variable-sized tags to pass data to
86 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
87 * to be recognised. The list is terminated with a zero-sized
91 typedef struct tagtable {
93 int (*parse)(const bp_tag_t*);
96 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
97 __attribute__((used, section(".taglist"))) = { tag, fn }
99 /* parse current tag */
101 static int __init parse_tag_mem(const bp_tag_t *tag)
103 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
105 if (mi->type != MEMORY_TYPE_CONVENTIONAL)
108 return memblock_add(mi->start, mi->end - mi->start);
111 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
113 #ifdef CONFIG_BLK_DEV_INITRD
115 static int __init parse_tag_initrd(const bp_tag_t* tag)
117 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
119 initrd_start = (unsigned long)__va(mi->start);
120 initrd_end = (unsigned long)__va(mi->end);
125 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
127 #endif /* CONFIG_BLK_DEV_INITRD */
131 static int __init parse_tag_fdt(const bp_tag_t *tag)
133 dtb_start = __va(tag->data[0]);
137 __tagtable(BP_TAG_FDT, parse_tag_fdt);
139 #endif /* CONFIG_USE_OF */
141 static int __init parse_tag_cmdline(const bp_tag_t* tag)
143 strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
147 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
149 static int __init parse_bootparam(const bp_tag_t* tag)
151 extern tagtable_t __tagtable_begin, __tagtable_end;
154 /* Boot parameters must start with a BP_TAG_FIRST tag. */
156 if (tag->id != BP_TAG_FIRST) {
157 pr_warn("Invalid boot parameters!\n");
161 tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
163 /* Parse all tags. */
165 while (tag != NULL && tag->id != BP_TAG_LAST) {
166 for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
167 if (tag->id == t->tag) {
172 if (t == &__tagtable_end)
173 pr_warn("Ignoring tag 0x%08x\n", tag->id);
174 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
180 static int __init parse_bootparam(const bp_tag_t *tag)
182 pr_info("Ignoring boot parameters at %p\n", tag);
189 #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
190 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
191 EXPORT_SYMBOL(xtensa_kio_paddr);
193 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
194 int depth, void *data)
196 const __be32 *ranges;
202 if (!of_flat_dt_is_compatible(node, "simple-bus"))
205 ranges = of_get_flat_dt_prop(node, "ranges", &len);
211 xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
212 /* round down to nearest 256MB boundary */
213 xtensa_kio_paddr &= 0xf0000000;
220 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
221 int depth, void *data)
227 void __init early_init_devtree(void *params)
229 early_init_dt_scan(params);
230 of_scan_flat_dt(xtensa_dt_io_area, NULL);
232 if (!command_line[0])
233 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
236 #endif /* CONFIG_USE_OF */
239 * Initialize architecture. (Early stage)
242 void __init init_arch(bp_tag_t *bp_start)
244 /* Initialize MMU. */
248 /* Initialize initial KASAN shadow map */
252 /* Parse boot parameters */
255 parse_bootparam(bp_start);
258 early_init_devtree(dtb_start);
261 #ifdef CONFIG_CMDLINE_BOOL
262 if (!command_line[0])
263 strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
266 /* Early hook for platforms */
268 platform_init(bp_start);
272 * Initialize system. Setup memory and reserve regions.
276 extern char _stext[];
277 extern char _WindowVectors_text_start;
278 extern char _WindowVectors_text_end;
279 extern char _DebugInterruptVector_text_start;
280 extern char _DebugInterruptVector_text_end;
281 extern char _KernelExceptionVector_text_start;
282 extern char _KernelExceptionVector_text_end;
283 extern char _UserExceptionVector_text_start;
284 extern char _UserExceptionVector_text_end;
285 extern char _DoubleExceptionVector_text_start;
286 extern char _DoubleExceptionVector_text_end;
287 #if XCHAL_EXCM_LEVEL >= 2
288 extern char _Level2InterruptVector_text_start;
289 extern char _Level2InterruptVector_text_end;
291 #if XCHAL_EXCM_LEVEL >= 3
292 extern char _Level3InterruptVector_text_start;
293 extern char _Level3InterruptVector_text_end;
295 #if XCHAL_EXCM_LEVEL >= 4
296 extern char _Level4InterruptVector_text_start;
297 extern char _Level4InterruptVector_text_end;
299 #if XCHAL_EXCM_LEVEL >= 5
300 extern char _Level5InterruptVector_text_start;
301 extern char _Level5InterruptVector_text_end;
303 #if XCHAL_EXCM_LEVEL >= 6
304 extern char _Level6InterruptVector_text_start;
305 extern char _Level6InterruptVector_text_end;
308 extern char _SecondaryResetVector_text_start;
309 extern char _SecondaryResetVector_text_end;
312 static inline int __init_memblock mem_reserve(unsigned long start,
315 return memblock_reserve(start, end - start);
318 void __init setup_arch(char **cmdline_p)
320 pr_info("config ID: %08x:%08x\n",
321 xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE));
322 if (xtensa_get_sr(SREG_EPC) != XCHAL_HW_CONFIGID0 ||
323 xtensa_get_sr(SREG_EXCSAVE) != XCHAL_HW_CONFIGID1)
324 pr_info("built for config ID: %08x:%08x\n",
325 XCHAL_HW_CONFIGID0, XCHAL_HW_CONFIGID1);
327 *cmdline_p = command_line;
328 platform_setup(cmdline_p);
329 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
331 /* Reserve some memory regions */
333 #ifdef CONFIG_BLK_DEV_INITRD
334 if (initrd_start < initrd_end &&
335 !mem_reserve(__pa(initrd_start), __pa(initrd_end)))
336 initrd_below_start_ok = 1;
341 mem_reserve(__pa(_stext), __pa(_end));
343 #ifdef CONFIG_VECTORS_OFFSET
344 mem_reserve(__pa(&_WindowVectors_text_start),
345 __pa(&_WindowVectors_text_end));
347 mem_reserve(__pa(&_DebugInterruptVector_text_start),
348 __pa(&_DebugInterruptVector_text_end));
350 mem_reserve(__pa(&_KernelExceptionVector_text_start),
351 __pa(&_KernelExceptionVector_text_end));
353 mem_reserve(__pa(&_UserExceptionVector_text_start),
354 __pa(&_UserExceptionVector_text_end));
356 mem_reserve(__pa(&_DoubleExceptionVector_text_start),
357 __pa(&_DoubleExceptionVector_text_end));
359 #if XCHAL_EXCM_LEVEL >= 2
360 mem_reserve(__pa(&_Level2InterruptVector_text_start),
361 __pa(&_Level2InterruptVector_text_end));
363 #if XCHAL_EXCM_LEVEL >= 3
364 mem_reserve(__pa(&_Level3InterruptVector_text_start),
365 __pa(&_Level3InterruptVector_text_end));
367 #if XCHAL_EXCM_LEVEL >= 4
368 mem_reserve(__pa(&_Level4InterruptVector_text_start),
369 __pa(&_Level4InterruptVector_text_end));
371 #if XCHAL_EXCM_LEVEL >= 5
372 mem_reserve(__pa(&_Level5InterruptVector_text_start),
373 __pa(&_Level5InterruptVector_text_end));
375 #if XCHAL_EXCM_LEVEL >= 6
376 mem_reserve(__pa(&_Level6InterruptVector_text_start),
377 __pa(&_Level6InterruptVector_text_end));
380 #endif /* CONFIG_VECTORS_OFFSET */
383 mem_reserve(__pa(&_SecondaryResetVector_text_start),
384 __pa(&_SecondaryResetVector_text_end));
389 unflatten_and_copy_device_tree();
399 # if defined(CONFIG_VGA_CONSOLE)
400 conswitchp = &vga_con;
401 # elif defined(CONFIG_DUMMY_CONSOLE)
402 conswitchp = &dummy_con;
407 static DEFINE_PER_CPU(struct cpu, cpu_data);
409 static int __init topology_init(void)
413 for_each_possible_cpu(i) {
414 struct cpu *cpu = &per_cpu(cpu_data, i);
415 cpu->hotpluggable = !!i;
416 register_cpu(cpu, i);
421 subsys_initcall(topology_init);
425 #if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU)
428 * We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must
430 * Way 4 is not currently used by linux.
431 * Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired.
432 * Way 5 shall be flushed and way 6 shall be set to identity mapping
435 local_flush_tlb_all();
436 invalidate_page_directory();
437 #if XCHAL_HAVE_SPANNING_WAY
440 unsigned long vaddr = (unsigned long)cpu_reset;
441 unsigned long paddr = __pa(vaddr);
442 unsigned long tmpaddr = vaddr + SZ_512M;
443 unsigned long tmp0, tmp1, tmp2, tmp3;
446 * Find a place for the temporary mapping. It must not be
447 * in the same 512MB region with vaddr or paddr, otherwise
448 * there may be multihit exception either on entry to the
449 * temporary mapping, or on entry to the identity mapping.
450 * (512MB is the biggest page size supported by TLB.)
452 while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
455 /* Invalidate mapping in the selected temporary area */
456 if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT))
457 invalidate_itlb_entry(itlb_probe(tmpaddr));
458 if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT))
459 invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));
462 * Map two consecutive pages starting at the physical address
463 * of this function to the temporary mapping area.
465 write_itlb_entry(__pte((paddr & PAGE_MASK) |
469 tmpaddr & PAGE_MASK);
470 write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) |
474 (tmpaddr & PAGE_MASK) + PAGE_SIZE);
476 /* Reinitialize TLB */
477 __asm__ __volatile__ ("movi %0, 1f\n\t"
483 * No literal, data or stack access
487 /* Initialize *tlbcfg */
489 "wsr %0, itlbcfg\n\t"
490 "wsr %0, dtlbcfg\n\t"
491 /* Invalidate TLB way 5 */
498 "addi %0, %0, -1\n\t"
500 /* Initialize TLB way 6 */
509 "addi %0, %0, -1\n\t"
512 /* Jump to identity mapping */
515 /* Complete way 6 initialization */
518 /* Invalidate temporary mapping */
523 : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
525 : "a"(tmpaddr - vaddr),
527 "a"(SZ_128M), "a"(SZ_512M),
529 "a"((tmpaddr + SZ_512M) & PAGE_MASK)
534 __asm__ __volatile__ ("movi a2, 0\n\t"
535 "wsr a2, icountlevel\n\t"
538 #if XCHAL_NUM_IBREAK > 0
539 "wsr a2, ibreakenable\n\t"
549 : "a" (XCHAL_RESET_VECTOR_VADDR)
555 void machine_restart(char * cmd)
560 void machine_halt(void)
566 void machine_power_off(void)
568 platform_power_off();
571 #ifdef CONFIG_PROC_FS
574 * Display some core information through /proc/cpuinfo.
578 c_show(struct seq_file *f, void *slot)
580 /* high-level stuff */
581 seq_printf(f, "CPU count\t: %u\n"
582 "CPU list\t: %*pbl\n"
583 "vendor_id\t: Tensilica\n"
584 "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
585 "core ID\t\t: " XCHAL_CORE_ID "\n"
587 "config ID\t: %08x:%08x\n"
589 "cpu MHz\t\t: %lu.%02lu\n"
590 "bogomips\t: %lu.%02lu\n",
592 cpumask_pr_args(cpu_online_mask),
593 XCHAL_BUILD_UNIQUE_ID,
594 xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE),
595 XCHAL_HAVE_BE ? "big" : "little",
597 (ccount_freq/10000) % 100,
598 loops_per_jiffy/(500000/HZ),
599 (loops_per_jiffy/(5000/HZ)) % 100);
600 seq_puts(f, "flags\t\t: "
610 #if XCHAL_HAVE_DENSITY
613 #if XCHAL_HAVE_BOOLEANS
622 #if XCHAL_HAVE_MINMAX
628 #if XCHAL_HAVE_CLAMPS
640 #if XCHAL_HAVE_MUL32_HIGH
646 #if XCHAL_HAVE_S32C1I
649 #if XCHAL_HAVE_EXCLUSIVE
655 seq_printf(f,"physical aregs\t: %d\n"
666 seq_printf(f,"num ints\t: %d\n"
670 "debug level\t: %d\n",
671 XCHAL_NUM_INTERRUPTS,
672 XCHAL_NUM_EXTINTERRUPTS,
678 seq_printf(f,"icache line size: %d\n"
679 "icache ways\t: %d\n"
680 "icache size\t: %d\n"
682 #if XCHAL_ICACHE_LINE_LOCKABLE
686 "dcache line size: %d\n"
687 "dcache ways\t: %d\n"
688 "dcache size\t: %d\n"
690 #if XCHAL_DCACHE_IS_WRITEBACK
693 #if XCHAL_DCACHE_LINE_LOCKABLE
697 XCHAL_ICACHE_LINESIZE,
700 XCHAL_DCACHE_LINESIZE,
708 * We show only CPU #0 info.
711 c_start(struct seq_file *f, loff_t *pos)
713 return (*pos == 0) ? (void *)1 : NULL;
717 c_next(struct seq_file *f, void *v, loff_t *pos)
720 return c_start(f, pos);
724 c_stop(struct seq_file *f, void *v)
728 const struct seq_operations cpuinfo_op =
736 #endif /* CONFIG_PROC_FS */