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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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25 #include "../i915_selftest.h"
27 static int intel_fw_table_check(const struct intel_forcewake_range *ranges,
28 unsigned int num_ranges,
34 for (i = 0, prev = -1; i < num_ranges; i++, ranges++) {
35 /* Check that the table is watertight */
36 if (is_watertight && (prev + 1) != (s32)ranges->start) {
37 pr_err("%s: entry[%d]:(%x, %x) is not watertight to previous (%x)\n",
38 __func__, i, ranges->start, ranges->end, prev);
42 /* Check that the table never goes backwards */
43 if (prev >= (s32)ranges->start) {
44 pr_err("%s: entry[%d]:(%x, %x) is less than the previous (%x)\n",
45 __func__, i, ranges->start, ranges->end, prev);
49 /* Check that the entry is valid */
50 if (ranges->start >= ranges->end) {
51 pr_err("%s: entry[%d]:(%x, %x) has negative length\n",
52 __func__, i, ranges->start, ranges->end);
62 static int intel_shadow_table_check(void)
65 const i915_reg_t *regs;
68 { gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) },
69 { gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
70 { gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs) },
72 const i915_reg_t *reg;
76 for (j = 0; j < ARRAY_SIZE(reg_lists); ++j) {
77 reg = reg_lists[j].regs;
78 for (i = 0, prev = -1; i < reg_lists[j].size; i++, reg++) {
79 u32 offset = i915_mmio_reg_offset(*reg);
81 if (prev >= (s32)offset) {
82 pr_err("%s: entry[%d]:(%x) is before previous (%x)\n",
83 __func__, i, offset, prev);
94 int intel_uncore_mock_selftests(void)
97 const struct intel_forcewake_range *ranges;
98 unsigned int num_ranges;
101 { __vlv_fw_ranges, ARRAY_SIZE(__vlv_fw_ranges), false },
102 { __chv_fw_ranges, ARRAY_SIZE(__chv_fw_ranges), false },
103 { __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
104 { __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
105 { __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true },
109 for (i = 0; i < ARRAY_SIZE(fw); i++) {
110 err = intel_fw_table_check(fw[i].ranges,
112 fw[i].is_watertight);
117 err = intel_shadow_table_check();
124 static int live_forcewake_ops(void *arg)
126 static const struct reg {
128 unsigned long platforms;
133 INTEL_GEN_MASK(6, 7),
138 INTEL_GEN_MASK(8, BITS_PER_LONG),
143 struct intel_gt *gt = arg;
144 struct intel_uncore_forcewake_domain *domain;
145 struct intel_uncore *uncore = gt->uncore;
146 struct intel_engine_cs *engine;
147 enum intel_engine_id id;
148 intel_wakeref_t wakeref;
152 GEM_BUG_ON(gt->awake);
154 /* vlv/chv with their pcu behave differently wrt reads */
155 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) {
156 pr_debug("PCU fakes forcewake badly; skipping\n");
161 * Not quite as reliable across the gen as one would hope.
163 * Either our theory of operation is incorrect, or there remain
164 * external parties interfering with the powerwells.
166 * https://bugs.freedesktop.org/show_bug.cgi?id=110210
168 if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN))
171 /* We have to pick carefully to get the exact behaviour we need */
172 for (r = registers; r->name; r++)
173 if (r->platforms & INTEL_INFO(gt->i915)->gen_mask)
176 pr_debug("Forcewaked register not known for %s; skipping\n",
177 intel_platform_name(INTEL_INFO(gt->i915)->platform));
181 wakeref = intel_runtime_pm_get(uncore->rpm);
183 for_each_fw_domain(domain, uncore, tmp) {
184 smp_store_mb(domain->active, false);
185 if (!hrtimer_cancel(&domain->timer))
188 intel_uncore_fw_release_timer(&domain->timer);
191 for_each_engine(engine, gt, id) {
192 i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset);
193 u32 __iomem *reg = uncore->regs + engine->mmio_base + r->offset;
194 enum forcewake_domains fw_domains;
197 if (!engine->default_state)
200 fw_domains = intel_uncore_forcewake_for_reg(uncore, mmio,
205 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
206 if (!domain->wake_count)
209 pr_err("fw_domain %s still active, aborting test!\n",
210 intel_uncore_forcewake_domain_to_str(domain->id));
215 intel_uncore_forcewake_get(uncore, fw_domains);
217 intel_uncore_forcewake_put(uncore, fw_domains);
219 /* Flush the forcewake release (delayed onto a timer) */
220 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
221 smp_store_mb(domain->active, false);
222 if (hrtimer_cancel(&domain->timer))
223 intel_uncore_fw_release_timer(&domain->timer);
226 err = wait_ack_clear(domain, FORCEWAKE_KERNEL);
229 pr_err("Failed to clear fw_domain %s\n",
230 intel_uncore_forcewake_domain_to_str(domain->id));
236 pr_err("%s:%s was zero while fw was held!\n",
237 engine->name, r->name);
242 /* We then expect the read to return 0 outside of the fw */
243 if (wait_for(readl(reg) == 0, 100)) {
244 pr_err("%s:%s=%0x, fw_domains 0x%x still up after 100ms!\n",
245 engine->name, r->name, readl(reg), fw_domains);
252 intel_runtime_pm_put(uncore->rpm, wakeref);
256 static int live_forcewake_domains(void *arg)
258 #define FW_RANGE 0x40000
259 struct intel_gt *gt = arg;
260 struct intel_uncore *uncore = gt->uncore;
261 unsigned long *valid;
265 if (!HAS_FPGA_DBG_UNCLAIMED(gt->i915) &&
266 !IS_VALLEYVIEW(gt->i915) &&
267 !IS_CHERRYVIEW(gt->i915))
271 * This test may lockup the machine or cause GPU hangs afterwards.
273 if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN))
276 valid = bitmap_zalloc(FW_RANGE, GFP_KERNEL);
280 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
282 check_for_unclaimed_mmio(uncore);
283 for (offset = 0; offset < FW_RANGE; offset += 4) {
284 i915_reg_t reg = { offset };
286 intel_uncore_posting_read_fw(uncore, reg);
287 if (!check_for_unclaimed_mmio(uncore))
288 set_bit(offset, valid);
291 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
294 for_each_set_bit(offset, valid, FW_RANGE) {
295 i915_reg_t reg = { offset };
297 iosf_mbi_punit_acquire();
298 intel_uncore_forcewake_reset(uncore);
299 iosf_mbi_punit_release();
301 check_for_unclaimed_mmio(uncore);
303 intel_uncore_posting_read_fw(uncore, reg);
304 if (check_for_unclaimed_mmio(uncore)) {
305 pr_err("Unclaimed mmio read to register 0x%04x\n",
315 static int live_fw_table(void *arg)
317 struct intel_gt *gt = arg;
319 /* Confirm the table we load is still valid */
320 return intel_fw_table_check(gt->uncore->fw_domains_table,
321 gt->uncore->fw_domains_table_entries,
322 INTEL_GEN(gt->i915) >= 9);
325 int intel_uncore_live_selftests(struct drm_i915_private *i915)
327 static const struct i915_subtest tests[] = {
328 SUBTEST(live_fw_table),
329 SUBTEST(live_forcewake_ops),
330 SUBTEST(live_forcewake_domains),
333 return intel_gt_live_subtests(tests, &i915->gt);