sdhci-xenon.c

   1 /*
   2  * Driver for Marvell Xenon SDHC as a platform device
   3  *
   4  * Copyright (C) 2016 Marvell, All Rights Reserved.
   5  *
   6  * Author:      Hu Ziji <huziji@marvell.com>
   7  * Date:        2016-8-24
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation version 2.
  12  *
  13  * Inspired by Jisheng Zhang <jszhang@marvell.com>
  14  * Special thanks to Video BG4 project team.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/ktime.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/pm.h>
  22 #include <linux/pm_runtime.h>
  23
  24 #include "sdhci-pltfm.h"
  25 #include "sdhci-xenon.h"
  26
  27 static int xenon_enable_internal_clk(struct sdhci_host *host)
  28 {
  29         u32 reg;
  30         ktime_t timeout;
  31
  32         reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
  33         reg |= SDHCI_CLOCK_INT_EN;
  34         sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL);
  35         /* Wait max 20 ms */
  36         timeout = ktime_add_ms(ktime_get(), 20);
  37         while (1) {
  38                 bool timedout = ktime_after(ktime_get(), timeout);
  39
  40                 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  41                 if (reg & SDHCI_CLOCK_INT_STABLE)
  42                         break;
  43                 if (timedout) {
  44                         dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n");
  45                         return -ETIMEDOUT;
  46                 }
  47                 usleep_range(900, 1100);
  48         }
  49
  50         return 0;
  51 }
  52
  53 /* Set SDCLK-off-while-idle */
  54 static void xenon_set_sdclk_off_idle(struct sdhci_host *host,
  55                                      unsigned char sdhc_id, bool enable)
  56 {
  57         u32 reg;
  58         u32 mask;
  59
  60         reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
  61         /* Get the bit shift basing on the SDHC index */
  62         mask = (0x1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sdhc_id));
  63         if (enable)
  64                 reg |= mask;
  65         else
  66                 reg &= ~mask;
  67
  68         sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
  69 }
  70
  71 /* Enable/Disable the Auto Clock Gating function */
  72 static void xenon_set_acg(struct sdhci_host *host, bool enable)
  73 {
  74         u32 reg;
  75
  76         reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
  77         if (enable)
  78                 reg &= ~XENON_AUTO_CLKGATE_DISABLE_MASK;
  79         else
  80                 reg |= XENON_AUTO_CLKGATE_DISABLE_MASK;
  81         sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
  82 }
  83
  84 /* Enable this SDHC */
  85 static void xenon_enable_sdhc(struct sdhci_host *host,
  86                               unsigned char sdhc_id)
  87 {
  88         u32 reg;
  89
  90         reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
  91         reg |= (BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
  92         sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
  93
  94         host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
  95         /*
  96          * Force to clear BUS_TEST to
  97          * skip bus_test_pre and bus_test_post
  98          */
  99         host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST;
 100 }
 101
 102 /* Disable this SDHC */
 103 static void xenon_disable_sdhc(struct sdhci_host *host,
 104                                unsigned char sdhc_id)
 105 {
 106         u32 reg;
 107
 108         reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
 109         reg &= ~(BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
 110         sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
 111 }
 112
 113 /* Enable Parallel Transfer Mode */
 114 static void xenon_enable_sdhc_parallel_tran(struct sdhci_host *host,
 115                                             unsigned char sdhc_id)
 116 {
 117         u32 reg;
 118
 119         reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
 120         reg |= BIT(sdhc_id);
 121         sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
 122 }
 123
 124 /* Mask command conflict error */
 125 static void xenon_mask_cmd_conflict_err(struct sdhci_host *host)
 126 {
 127         u32  reg;
 128
 129         reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
 130         reg |= XENON_MASK_CMD_CONFLICT_ERR;
 131         sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
 132 }
 133
 134 static void xenon_retune_setup(struct sdhci_host *host)
 135 {
 136         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 137         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 138         u32 reg;
 139
 140         /* Disable the Re-Tuning Request functionality */
 141         reg = sdhci_readl(host, XENON_SLOT_RETUNING_REQ_CTRL);
 142         reg &= ~XENON_RETUNING_COMPATIBLE;
 143         sdhci_writel(host, reg, XENON_SLOT_RETUNING_REQ_CTRL);
 144
 145         /* Disable the Re-tuning Interrupt */
 146         reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
 147         reg &= ~SDHCI_INT_RETUNE;
 148         sdhci_writel(host, reg, SDHCI_SIGNAL_ENABLE);
 149         reg = sdhci_readl(host, SDHCI_INT_ENABLE);
 150         reg &= ~SDHCI_INT_RETUNE;
 151         sdhci_writel(host, reg, SDHCI_INT_ENABLE);
 152
 153         /* Force to use Tuning Mode 1 */
 154         host->tuning_mode = SDHCI_TUNING_MODE_1;
 155         /* Set re-tuning period */
 156         host->tuning_count = 1 << (priv->tuning_count - 1);
 157 }
 158
 159 /*
 160  * Operations inside struct sdhci_ops
 161  */
 162 /* Recover the Register Setting cleared during SOFTWARE_RESET_ALL */
 163 static void xenon_reset_exit(struct sdhci_host *host,
 164                              unsigned char sdhc_id, u8 mask)
 165 {
 166         /* Only SOFTWARE RESET ALL will clear the register setting */
 167         if (!(mask & SDHCI_RESET_ALL))
 168                 return;
 169
 170         /* Disable tuning request and auto-retuning again */
 171         xenon_retune_setup(host);
 172
 173         /*
 174          * The ACG should be turned off at the early init time, in order
 175          * to solve a possible issues with the 1.8V regulator stabilization.
 176          * The feature is enabled in later stage.
 177          */
 178         xenon_set_acg(host, false);
 179
 180         xenon_set_sdclk_off_idle(host, sdhc_id, false);
 181
 182         xenon_mask_cmd_conflict_err(host);
 183 }
 184
 185 static void xenon_reset(struct sdhci_host *host, u8 mask)
 186 {
 187         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 188         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 189
 190         sdhci_reset(host, mask);
 191         xenon_reset_exit(host, priv->sdhc_id, mask);
 192 }
 193
 194 /*
 195  * Xenon defines different values for HS200 and HS400
 196  * in Host_Control_2
 197  */
 198 static void xenon_set_uhs_signaling(struct sdhci_host *host,
 199                                     unsigned int timing)
 200 {
 201         u16 ctrl_2;
 202
 203         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 204         /* Select Bus Speed Mode for host */
 205         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 206         if (timing == MMC_TIMING_MMC_HS200)
 207                 ctrl_2 |= XENON_CTRL_HS200;
 208         else if (timing == MMC_TIMING_UHS_SDR104)
 209                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
 210         else if (timing == MMC_TIMING_UHS_SDR12)
 211                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
 212         else if (timing == MMC_TIMING_UHS_SDR25)
 213                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 214         else if (timing == MMC_TIMING_UHS_SDR50)
 215                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
 216         else if ((timing == MMC_TIMING_UHS_DDR50) ||
 217                  (timing == MMC_TIMING_MMC_DDR52))
 218                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
 219         else if (timing == MMC_TIMING_MMC_HS400)
 220                 ctrl_2 |= XENON_CTRL_HS400;
 221         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 222 }
 223
 224 static void xenon_set_power(struct sdhci_host *host, unsigned char mode,
 225                 unsigned short vdd)
 226 {
 227         struct mmc_host *mmc = host->mmc;
 228         u8 pwr = host->pwr;
 229
 230         sdhci_set_power_noreg(host, mode, vdd);
 231
 232         if (host->pwr == pwr)
 233                 return;
 234
 235         if (host->pwr == 0)
 236                 vdd = 0;
 237
 238         if (!IS_ERR(mmc->supply.vmmc))
 239                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
 240 }
 241
 242 static void xenon_voltage_switch(struct sdhci_host *host)
 243 {
 244         /* Wait for 5ms after set 1.8V signal enable bit */
 245         usleep_range(5000, 5500);
 246
 247         /*
 248          * For some reason the controller's Host Control2 register reports
 249          * the bit representing 1.8V signaling as 0 when read after it was
 250          * written as 1. Subsequent read reports 1.
 251          *
 252          * Since this may cause some issues, do an empty read of the Host
 253          * Control2 register here to circumvent this.
 254          */
 255         sdhci_readw(host, SDHCI_HOST_CONTROL2);
 256 }
 257
 258 static const struct sdhci_ops sdhci_xenon_ops = {
 259         .voltage_switch         = xenon_voltage_switch,
 260         .set_clock              = sdhci_set_clock,
 261         .set_power              = xenon_set_power,
 262         .set_bus_width          = sdhci_set_bus_width,
 263         .reset                  = xenon_reset,
 264         .set_uhs_signaling      = xenon_set_uhs_signaling,
 265         .get_max_clock          = sdhci_pltfm_clk_get_max_clock,
 266 };
 267
 268 static const struct sdhci_pltfm_data sdhci_xenon_pdata = {
 269         .ops = &sdhci_xenon_ops,
 270         .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
 271                   SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
 272                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 273 };
 274
 275 /*
 276  * Xenon Specific Operations in mmc_host_ops
 277  */
 278 static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 279 {
 280         struct sdhci_host *host = mmc_priv(mmc);
 281         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 282         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 283         u32 reg;
 284
 285         /*
 286          * HS400/HS200/eMMC HS doesn't have Preset Value register.
 287          * However, sdhci_set_ios will read HS400/HS200 Preset register.
 288          * Disable Preset Value register for HS400/HS200.
 289          * eMMC HS with preset_enabled set will trigger a bug in
 290          * get_preset_value().
 291          */
 292         if ((ios->timing == MMC_TIMING_MMC_HS400) ||
 293             (ios->timing == MMC_TIMING_MMC_HS200) ||
 294             (ios->timing == MMC_TIMING_MMC_HS)) {
 295                 host->preset_enabled = false;
 296                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
 297                 host->flags &= ~SDHCI_PV_ENABLED;
 298
 299                 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 300                 reg &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
 301                 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 302         } else {
 303                 host->quirks2 &= ~SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
 304         }
 305
 306         sdhci_set_ios(mmc, ios);
 307         xenon_phy_adj(host, ios);
 308
 309         if (host->clock > XENON_DEFAULT_SDCLK_FREQ)
 310                 xenon_set_sdclk_off_idle(host, priv->sdhc_id, true);
 311 }
 312
 313 static int xenon_start_signal_voltage_switch(struct mmc_host *mmc,
 314                                              struct mmc_ios *ios)
 315 {
 316         struct sdhci_host *host = mmc_priv(mmc);
 317
 318         /*
 319          * Before SD/SDIO set signal voltage, SD bus clock should be
 320          * disabled. However, sdhci_set_clock will also disable the Internal
 321          * clock in mmc_set_signal_voltage().
 322          * If Internal clock is disabled, the 3.3V/1.8V bit can not be updated.
 323          * Thus here manually enable internal clock.
 324          *
 325          * After switch completes, it is unnecessary to disable internal clock,
 326          * since keeping internal clock active obeys SD spec.
 327          */
 328         xenon_enable_internal_clk(host);
 329
 330         xenon_soc_pad_ctrl(host, ios->signal_voltage);
 331
 332         /*
 333          * If Vqmmc is fixed on platform, vqmmc regulator should be unavailable.
 334          * Thus SDHCI_CTRL_VDD_180 bit might not work then.
 335          * Skip the standard voltage switch to avoid any issue.
 336          */
 337         if (PTR_ERR(mmc->supply.vqmmc) == -ENODEV)
 338                 return 0;
 339
 340         return sdhci_start_signal_voltage_switch(mmc, ios);
 341 }
 342
 343 /*
 344  * Update card type.
 345  * priv->init_card_type will be used in PHY timing adjustment.
 346  */
 347 static void xenon_init_card(struct mmc_host *mmc, struct mmc_card *card)
 348 {
 349         struct sdhci_host *host = mmc_priv(mmc);
 350         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 351         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 352
 353         /* Update card type*/
 354         priv->init_card_type = card->type;
 355 }
 356
 357 static int xenon_execute_tuning(struct mmc_host *mmc, u32 opcode)
 358 {
 359         struct sdhci_host *host = mmc_priv(mmc);
 360
 361         if (host->timing == MMC_TIMING_UHS_DDR50 ||
 362                 host->timing == MMC_TIMING_MMC_DDR52)
 363                 return 0;
 364
 365         /*
 366          * Currently force Xenon driver back to support mode 1 only,
 367          * even though Xenon might claim to support mode 2 or mode 3.
 368          * It requires more time to test mode 2/mode 3 on more platforms.
 369          */
 370         if (host->tuning_mode != SDHCI_TUNING_MODE_1)
 371                 xenon_retune_setup(host);
 372
 373         return sdhci_execute_tuning(mmc, opcode);
 374 }
 375
 376 static void xenon_enable_sdio_irq(struct mmc_host *mmc, int enable)
 377 {
 378         struct sdhci_host *host = mmc_priv(mmc);
 379         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 380         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 381         u32 reg;
 382         u8 sdhc_id = priv->sdhc_id;
 383
 384         sdhci_enable_sdio_irq(mmc, enable);
 385
 386         if (enable) {
 387                 /*
 388                  * Set SDIO Card Inserted indication
 389                  * to enable detecting SDIO async irq.
 390                  */
 391                 reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
 392                 reg |= (1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
 393                 sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
 394         } else {
 395                 /* Clear SDIO Card Inserted indication */
 396                 reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
 397                 reg &= ~(1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
 398                 sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
 399         }
 400 }
 401
 402 static void xenon_replace_mmc_host_ops(struct sdhci_host *host)
 403 {
 404         host->mmc_host_ops.set_ios = xenon_set_ios;
 405         host->mmc_host_ops.start_signal_voltage_switch =
 406                         xenon_start_signal_voltage_switch;
 407         host->mmc_host_ops.init_card = xenon_init_card;
 408         host->mmc_host_ops.execute_tuning = xenon_execute_tuning;
 409         host->mmc_host_ops.enable_sdio_irq = xenon_enable_sdio_irq;
 410 }
 411
 412 /*
 413  * Parse Xenon specific DT properties:
 414  * sdhc-id: the index of current SDHC.
 415  *          Refer to XENON_SYS_CFG_INFO register
 416  * tun-count: the interval between re-tuning
 417  */
 418 static int xenon_probe_dt(struct platform_device *pdev)
 419 {
 420         struct device_node *np = pdev->dev.of_node;
 421         struct sdhci_host *host = platform_get_drvdata(pdev);
 422         struct mmc_host *mmc = host->mmc;
 423         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 424         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 425         u32 sdhc_id, nr_sdhc;
 426         u32 tuning_count;
 427
 428         /* Disable HS200 on Armada AP806 */
 429         if (of_device_is_compatible(np, "marvell,armada-ap806-sdhci"))
 430                 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
 431
 432         sdhc_id = 0x0;
 433         if (!of_property_read_u32(np, "marvell,xenon-sdhc-id", &sdhc_id)) {
 434                 nr_sdhc = sdhci_readl(host, XENON_SYS_CFG_INFO);
 435                 nr_sdhc &= XENON_NR_SUPPORTED_SLOT_MASK;
 436                 if (unlikely(sdhc_id > nr_sdhc)) {
 437                         dev_err(mmc_dev(mmc), "SDHC Index %d exceeds Number of SDHCs %d\n",
 438                                 sdhc_id, nr_sdhc);
 439                         return -EINVAL;
 440                 }
 441         }
 442         priv->sdhc_id = sdhc_id;
 443
 444         tuning_count = XENON_DEF_TUNING_COUNT;
 445         if (!of_property_read_u32(np, "marvell,xenon-tun-count",
 446                                   &tuning_count)) {
 447                 if (unlikely(tuning_count >= XENON_TMR_RETUN_NO_PRESENT)) {
 448                         dev_err(mmc_dev(mmc), "Wrong Re-tuning Count. Set default value %d\n",
 449                                 XENON_DEF_TUNING_COUNT);
 450                         tuning_count = XENON_DEF_TUNING_COUNT;
 451                 }
 452         }
 453         priv->tuning_count = tuning_count;
 454
 455         return xenon_phy_parse_dt(np, host);
 456 }
 457
 458 static int xenon_sdhc_prepare(struct sdhci_host *host)
 459 {
 460         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 461         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 462         u8 sdhc_id = priv->sdhc_id;
 463
 464         /* Enable SDHC */
 465         xenon_enable_sdhc(host, sdhc_id);
 466
 467         /* Enable ACG */
 468         xenon_set_acg(host, true);
 469
 470         /* Enable Parallel Transfer Mode */
 471         xenon_enable_sdhc_parallel_tran(host, sdhc_id);
 472
 473         /* Disable SDCLK-Off-While-Idle before card init */
 474         xenon_set_sdclk_off_idle(host, sdhc_id, false);
 475
 476         xenon_mask_cmd_conflict_err(host);
 477
 478         return 0;
 479 }
 480
 481 static void xenon_sdhc_unprepare(struct sdhci_host *host)
 482 {
 483         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 484         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 485         u8 sdhc_id = priv->sdhc_id;
 486
 487         /* disable SDHC */
 488         xenon_disable_sdhc(host, sdhc_id);
 489 }
 490
 491 static int xenon_probe(struct platform_device *pdev)
 492 {
 493         struct sdhci_pltfm_host *pltfm_host;
 494         struct sdhci_host *host;
 495         struct xenon_priv *priv;
 496         int err;
 497
 498         host = sdhci_pltfm_init(pdev, &sdhci_xenon_pdata,
 499                                 sizeof(struct xenon_priv));
 500         if (IS_ERR(host))
 501                 return PTR_ERR(host);
 502
 503         pltfm_host = sdhci_priv(host);
 504         priv = sdhci_pltfm_priv(pltfm_host);
 505
 506         /*
 507          * Link Xenon specific mmc_host_ops function,
 508          * to replace standard ones in sdhci_ops.
 509          */
 510         xenon_replace_mmc_host_ops(host);
 511
 512         pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
 513         if (IS_ERR(pltfm_host->clk)) {
 514                 err = PTR_ERR(pltfm_host->clk);
 515                 dev_err(&pdev->dev, "Failed to setup input clk: %d\n", err);
 516                 goto free_pltfm;
 517         }
 518         err = clk_prepare_enable(pltfm_host->clk);
 519         if (err)
 520                 goto free_pltfm;
 521
 522         priv->axi_clk = devm_clk_get(&pdev->dev, "axi");
 523         if (IS_ERR(priv->axi_clk)) {
 524                 err = PTR_ERR(priv->axi_clk);
 525                 if (err == -EPROBE_DEFER)
 526                         goto err_clk;
 527         } else {
 528                 err = clk_prepare_enable(priv->axi_clk);
 529                 if (err)
 530                         goto err_clk;
 531         }
 532
 533         err = mmc_of_parse(host->mmc);
 534         if (err)
 535                 goto err_clk_axi;
 536
 537         sdhci_get_of_property(pdev);
 538
 539         xenon_set_acg(host, false);
 540
 541         /* Xenon specific dt parse */
 542         err = xenon_probe_dt(pdev);
 543         if (err)
 544                 goto err_clk_axi;
 545
 546         err = xenon_sdhc_prepare(host);
 547         if (err)
 548                 goto err_clk_axi;
 549
 550         pm_runtime_get_noresume(&pdev->dev);
 551         pm_runtime_set_active(&pdev->dev);
 552         pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
 553         pm_runtime_use_autosuspend(&pdev->dev);
 554         pm_runtime_enable(&pdev->dev);
 555         pm_suspend_ignore_children(&pdev->dev, 1);
 556
 557         err = sdhci_add_host(host);
 558         if (err)
 559                 goto remove_sdhc;
 560
 561         pm_runtime_put_autosuspend(&pdev->dev);
 562
 563         return 0;
 564
 565 remove_sdhc:
 566         pm_runtime_disable(&pdev->dev);
 567         pm_runtime_put_noidle(&pdev->dev);
 568         xenon_sdhc_unprepare(host);
 569 err_clk_axi:
 570         clk_disable_unprepare(priv->axi_clk);
 571 err_clk:
 572         clk_disable_unprepare(pltfm_host->clk);
 573 free_pltfm:
 574         sdhci_pltfm_free(pdev);
 575         return err;
 576 }
 577
 578 static int xenon_remove(struct platform_device *pdev)
 579 {
 580         struct sdhci_host *host = platform_get_drvdata(pdev);
 581         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 582         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 583
 584         pm_runtime_get_sync(&pdev->dev);
 585         pm_runtime_disable(&pdev->dev);
 586         pm_runtime_put_noidle(&pdev->dev);
 587
 588         sdhci_remove_host(host, 0);
 589
 590         xenon_sdhc_unprepare(host);
 591         clk_disable_unprepare(priv->axi_clk);
 592         clk_disable_unprepare(pltfm_host->clk);
 593
 594         sdhci_pltfm_free(pdev);
 595
 596         return 0;
 597 }
 598
 599 #ifdef CONFIG_PM_SLEEP
 600 static int xenon_suspend(struct device *dev)
 601 {
 602         struct sdhci_host *host = dev_get_drvdata(dev);
 603         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 604         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 605         int ret;
 606
 607         ret = pm_runtime_force_suspend(dev);
 608
 609         priv->restore_needed = true;
 610         return ret;
 611 }
 612 #endif
 613
 614 #ifdef CONFIG_PM
 615 static int xenon_runtime_suspend(struct device *dev)
 616 {
 617         struct sdhci_host *host = dev_get_drvdata(dev);
 618         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 619         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 620         int ret;
 621
 622         ret = sdhci_runtime_suspend_host(host);
 623         if (ret)
 624                 return ret;
 625
 626         if (host->tuning_mode != SDHCI_TUNING_MODE_3)
 627                 mmc_retune_needed(host->mmc);
 628
 629         clk_disable_unprepare(pltfm_host->clk);
 630         /*
 631          * Need to update the priv->clock here, or when runtime resume
 632          * back, phy don't aware the clock change and won't adjust phy
 633          * which will cause cmd err
 634          */
 635         priv->clock = 0;
 636         return 0;
 637 }
 638
 639 static int xenon_runtime_resume(struct device *dev)
 640 {
 641         struct sdhci_host *host = dev_get_drvdata(dev);
 642         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 643         struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
 644         int ret;
 645
 646         ret = clk_prepare_enable(pltfm_host->clk);
 647         if (ret) {
 648                 dev_err(dev, "can't enable mainck\n");
 649                 return ret;
 650         }
 651
 652         if (priv->restore_needed) {
 653                 ret = xenon_sdhc_prepare(host);
 654                 if (ret)
 655                         goto out;
 656                 priv->restore_needed = false;
 657         }
 658
 659         ret = sdhci_runtime_resume_host(host);
 660         if (ret)
 661                 goto out;
 662         return 0;
 663 out:
 664         clk_disable_unprepare(pltfm_host->clk);
 665         return ret;
 666 }
 667 #endif /* CONFIG_PM */
 668
 669 static const struct dev_pm_ops sdhci_xenon_dev_pm_ops = {
 670         SET_SYSTEM_SLEEP_PM_OPS(xenon_suspend,
 671                                 pm_runtime_force_resume)
 672         SET_RUNTIME_PM_OPS(xenon_runtime_suspend,
 673                            xenon_runtime_resume,
 674                            NULL)
 675 };
 676
 677 static const struct of_device_id sdhci_xenon_dt_ids[] = {
 678         { .compatible = "marvell,armada-ap806-sdhci",},
 679         { .compatible = "marvell,armada-cp110-sdhci",},
 680         { .compatible = "marvell,armada-3700-sdhci",},
 681         {}
 682 };
 683 MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids);
 684
 685 static struct platform_driver sdhci_xenon_driver = {
 686         .driver = {
 687                 .name   = "xenon-sdhci",
 688                 .of_match_table = sdhci_xenon_dt_ids,
 689                 .pm = &sdhci_xenon_dev_pm_ops,
 690         },
 691         .probe  = xenon_probe,
 692         .remove = xenon_remove,
 693 };
 694
 695 module_platform_driver(sdhci_xenon_driver);
 696
 697 MODULE_DESCRIPTION("SDHCI platform driver for Marvell Xenon SDHC");
 698 MODULE_AUTHOR("Hu Ziji <huziji@marvell.com>");
 699 MODULE_LICENSE("GPL v2");