1 // SPDX-License-Identifier: GPL-2.0+
3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
4 * Author: Jon Ringle <jringle@gridpoint.com>
6 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/i2c.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/module.h>
19 #include <linux/property.h>
20 #include <linux/regmap.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/spi/spi.h>
26 #include <linux/uaccess.h>
27 #include <linux/units.h>
28 #include <uapi/linux/sched/types.h>
30 #define SC16IS7XX_NAME "sc16is7xx"
31 #define SC16IS7XX_MAX_DEVS 8
33 /* SC16IS7XX register definitions */
34 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
35 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
36 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
37 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
38 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
39 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */
40 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
41 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */
42 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
43 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
44 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
45 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
46 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
49 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
52 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
55 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
58 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
60 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
61 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
62 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
64 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
65 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
66 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
68 /* Enhanced Register set: Only if (LCR == 0xBF) */
69 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
70 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
71 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
72 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
73 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
75 /* IER register bits */
76 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
77 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
79 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
81 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
84 /* IER register bits - write only if (EFR[4] == 1) */
85 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
86 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
87 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
88 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
90 /* FCR register bits */
91 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
92 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
93 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
94 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
95 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
97 /* FCR register bits - write only if (EFR[4] == 1) */
98 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
99 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
101 /* IIR register bits */
102 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
103 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
104 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
105 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
106 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
107 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
108 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
111 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
114 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
115 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
119 /* LCR register bits */
120 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
121 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
123 * Word length bits table:
129 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
131 * STOP length bit table:
133 * 1 -> 1-1.5 stop bits if
135 * 2 stop bits otherwise
137 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
138 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
139 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
140 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
141 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
142 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
143 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
144 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
145 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
146 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
148 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
151 /* MCR register bits */
152 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
155 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
156 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
157 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
158 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
162 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
166 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
171 /* LSR register bits */
172 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
173 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
174 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
175 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
176 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
177 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
178 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
179 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
180 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
182 /* MSR register bits */
183 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
184 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
188 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
192 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
196 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */
197 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4)
200 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7)
203 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6)
206 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
210 * TCR trigger levels are available from 0 to 60 characters with a granularity
212 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
213 * no built-in hardware check to make sure this condition is met. Also, the TCR
214 * must be programmed with this condition before auto RTS or software flow
215 * control is enabled to avoid spurious operation of the device.
217 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
218 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
222 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
223 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
224 * trigger levels. Trigger levels from 4 characters to 60 characters are
225 * available with a granularity of four.
227 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
228 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
229 * the trigger level defined in FCR is discarded. This applies to both transmit
230 * FIFO and receive FIFO trigger level setting.
232 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
233 * default state, that is, '00'.
235 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
236 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
238 /* IOControl register bits (Only 750/760) */
239 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
240 #define SC16IS7XX_IOCONTROL_MODEM_BIT (1 << 1) /* Enable GPIO[7:4] as modem pins */
241 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
243 /* EFCR register bits */
244 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
246 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
247 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
248 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
249 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
250 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
251 * 0 = rate upto 115.2 kbit/s
253 * 1 = rate upto 1.152 Mbit/s
257 /* EFR register bits */
258 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
259 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
260 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
261 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
262 * and writing to IER[7:4],
265 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
266 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
268 * SWFLOW bits 3 & 2 table:
269 * 00 -> no transmitter flow
271 * 01 -> transmitter generates
273 * 10 -> transmitter generates
275 * 11 -> transmitter generates
276 * XON1, XON2, XOFF1 and
279 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
280 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
282 * SWFLOW bits 3 & 2 table:
283 * 00 -> no received flow
285 * 01 -> receiver compares
287 * 10 -> receiver compares
289 * 11 -> receiver compares
290 * XON1, XON2, XOFF1 and
294 /* Misc definitions */
295 #define SC16IS7XX_FIFO_SIZE (64)
296 #define SC16IS7XX_REG_SHIFT 2
298 struct sc16is7xx_devtype {
304 #define SC16IS7XX_RECONF_MD (1 << 0)
305 #define SC16IS7XX_RECONF_IER (1 << 1)
306 #define SC16IS7XX_RECONF_RS485 (1 << 2)
308 struct sc16is7xx_one_config {
313 struct sc16is7xx_one {
314 struct uart_port port;
316 struct kthread_work tx_work;
317 struct kthread_work reg_work;
318 struct sc16is7xx_one_config config;
322 struct sc16is7xx_port {
323 const struct sc16is7xx_devtype *devtype;
324 struct regmap *regmap;
326 #ifdef CONFIG_GPIOLIB
327 struct gpio_chip gpio;
329 unsigned char buf[SC16IS7XX_FIFO_SIZE];
330 struct kthread_worker kworker;
331 struct task_struct *kworker_task;
332 struct mutex efr_lock;
333 struct sc16is7xx_one p[];
336 static unsigned long sc16is7xx_lines;
338 static struct uart_driver sc16is7xx_uart = {
339 .owner = THIS_MODULE,
341 .nr = SC16IS7XX_MAX_DEVS,
344 #define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e)))
345 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
347 static int sc16is7xx_line(struct uart_port *port)
349 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
354 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
356 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
357 unsigned int val = 0;
358 const u8 line = sc16is7xx_line(port);
360 regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val);
365 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
367 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
368 const u8 line = sc16is7xx_line(port);
370 regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val);
373 static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen)
375 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
376 const u8 line = sc16is7xx_line(port);
377 u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line;
379 regmap_noinc_read(s->regmap, addr, s->buf, rxlen);
382 static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send)
384 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
385 const u8 line = sc16is7xx_line(port);
386 u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | line;
389 * Don't send zero-length data, at least on SPI it confuses the chip
390 * delivering wrong TXLVL data.
392 if (unlikely(!to_send))
395 regmap_noinc_write(s->regmap, addr, s->buf, to_send);
398 static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
401 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
402 const u8 line = sc16is7xx_line(port);
404 regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line,
408 static int sc16is7xx_alloc_line(void)
412 BUILD_BUG_ON(SC16IS7XX_MAX_DEVS > BITS_PER_LONG);
414 for (i = 0; i < SC16IS7XX_MAX_DEVS; i++)
415 if (!test_and_set_bit(i, &sc16is7xx_lines))
421 static void sc16is7xx_power(struct uart_port *port, int on)
423 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
424 SC16IS7XX_IER_SLEEP_BIT,
425 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
428 static const struct sc16is7xx_devtype sc16is74x_devtype = {
434 static const struct sc16is7xx_devtype sc16is750_devtype = {
440 static const struct sc16is7xx_devtype sc16is752_devtype = {
446 static const struct sc16is7xx_devtype sc16is760_devtype = {
452 static const struct sc16is7xx_devtype sc16is762_devtype = {
458 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
460 switch (reg >> SC16IS7XX_REG_SHIFT) {
461 case SC16IS7XX_RHR_REG:
462 case SC16IS7XX_IIR_REG:
463 case SC16IS7XX_LSR_REG:
464 case SC16IS7XX_MSR_REG:
465 case SC16IS7XX_TXLVL_REG:
466 case SC16IS7XX_RXLVL_REG:
467 case SC16IS7XX_IOSTATE_REG:
476 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
478 switch (reg >> SC16IS7XX_REG_SHIFT) {
479 case SC16IS7XX_RHR_REG:
488 static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg)
490 return reg == SC16IS7XX_RHR_REG;
493 static int sc16is7xx_set_baud(struct uart_port *port, int baud)
495 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
498 unsigned long clk = port->uartclk, div = clk / 16 / baud;
501 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
505 /* In an amazing feat of design, the Enhanced Features Register shares
506 * the address of the Interrupt Identification Register, and is
507 * switched in by writing a magic value (0xbf) to the Line Control
508 * Register. Any interrupt firing during this time will see the EFR
509 * where it expects the IIR to be, leading to "Unexpected interrupt"
512 * Prevent this possibility by claiming a mutex while accessing the
513 * EFR, and claiming the same mutex from within the interrupt handler.
514 * This is similar to disabling the interrupt, but that doesn't work
515 * because the bulk of the interrupt processing is run as a workqueue
516 * job in thread context.
518 mutex_lock(&s->efr_lock);
520 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
522 /* Open the LCR divisors for configuration */
523 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
524 SC16IS7XX_LCR_CONF_MODE_B);
526 /* Enable enhanced features */
527 regcache_cache_bypass(s->regmap, true);
528 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
529 SC16IS7XX_EFR_ENABLE_BIT);
530 regcache_cache_bypass(s->regmap, false);
532 /* Put LCR back to the normal mode */
533 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
535 mutex_unlock(&s->efr_lock);
537 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
538 SC16IS7XX_MCR_CLKSEL_BIT,
541 /* Open the LCR divisors for configuration */
542 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
543 SC16IS7XX_LCR_CONF_MODE_A);
545 /* Write the new divisor */
546 regcache_cache_bypass(s->regmap, true);
547 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
548 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
549 regcache_cache_bypass(s->regmap, false);
551 /* Put LCR back to the normal mode */
552 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
554 return DIV_ROUND_CLOSEST(clk / 16, div);
557 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
560 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
561 unsigned int lsr = 0, ch, flag, bytes_read, i;
562 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
564 if (unlikely(rxlen >= sizeof(s->buf))) {
565 dev_warn_ratelimited(port->dev,
566 "ttySC%i: Possible RX FIFO overrun: %d\n",
568 port->icount.buf_overrun++;
569 /* Ensure sanity of RX level */
570 rxlen = sizeof(s->buf);
574 /* Only read lsr if there are possible errors in FIFO */
576 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
577 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
578 read_lsr = false; /* No errors left in FIFO */
583 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
586 sc16is7xx_fifo_read(port, rxlen);
590 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
596 if (lsr & SC16IS7XX_LSR_BI_BIT) {
598 if (uart_handle_break(port))
600 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
601 port->icount.parity++;
602 else if (lsr & SC16IS7XX_LSR_FE_BIT)
603 port->icount.frame++;
604 else if (lsr & SC16IS7XX_LSR_OE_BIT)
605 port->icount.overrun++;
607 lsr &= port->read_status_mask;
608 if (lsr & SC16IS7XX_LSR_BI_BIT)
610 else if (lsr & SC16IS7XX_LSR_PE_BIT)
612 else if (lsr & SC16IS7XX_LSR_FE_BIT)
614 else if (lsr & SC16IS7XX_LSR_OE_BIT)
618 for (i = 0; i < bytes_read; ++i) {
620 if (uart_handle_sysrq_char(port, ch))
623 if (lsr & port->ignore_status_mask)
626 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
632 tty_flip_buffer_push(&port->state->port);
635 static void sc16is7xx_handle_tx(struct uart_port *port)
637 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
638 struct circ_buf *xmit = &port->state->xmit;
639 unsigned int txlen, to_send, i;
641 if (unlikely(port->x_char)) {
642 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
648 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
651 /* Get length of data pending in circular buffer */
652 to_send = uart_circ_chars_pending(xmit);
653 if (likely(to_send)) {
654 /* Limit to size of TX FIFO */
655 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
656 if (txlen > SC16IS7XX_FIFO_SIZE) {
657 dev_err_ratelimited(port->dev,
658 "chip reports %d free bytes in TX fifo, but it only has %d",
659 txlen, SC16IS7XX_FIFO_SIZE);
662 to_send = (to_send > txlen) ? txlen : to_send;
664 /* Add data to send */
665 port->icount.tx += to_send;
667 /* Convert to linear buffer */
668 for (i = 0; i < to_send; ++i) {
669 s->buf[i] = xmit->buf[xmit->tail];
670 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
673 sc16is7xx_fifo_write(port, to_send);
676 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
677 uart_write_wakeup(port);
680 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
682 struct uart_port *port = &s->p[portno].port;
685 unsigned int iir, rxlen;
687 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
688 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
691 iir &= SC16IS7XX_IIR_ID_MASK;
694 case SC16IS7XX_IIR_RDI_SRC:
695 case SC16IS7XX_IIR_RLSE_SRC:
696 case SC16IS7XX_IIR_RTOI_SRC:
697 case SC16IS7XX_IIR_XOFFI_SRC:
698 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
701 * There is a silicon bug that makes the chip report a
702 * time-out interrupt but no data in the FIFO. This is
703 * described in errata section 18.1.4.
705 * When this happens, read one byte from the FIFO to
706 * clear the interrupt.
708 if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen)
712 sc16is7xx_handle_rx(port, rxlen, iir);
714 case SC16IS7XX_IIR_THRI_SRC:
715 sc16is7xx_handle_tx(port);
718 dev_err_ratelimited(port->dev,
719 "ttySC%i: Unexpected interrupt: %x",
727 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
729 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
731 mutex_lock(&s->efr_lock);
734 bool keep_polling = false;
737 for (i = 0; i < s->devtype->nr_uart; ++i)
738 keep_polling |= sc16is7xx_port_irq(s, i);
743 mutex_unlock(&s->efr_lock);
748 static void sc16is7xx_tx_proc(struct kthread_work *ws)
750 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
751 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
753 if ((port->rs485.flags & SER_RS485_ENABLED) &&
754 (port->rs485.delay_rts_before_send > 0))
755 msleep(port->rs485.delay_rts_before_send);
757 mutex_lock(&s->efr_lock);
758 sc16is7xx_handle_tx(port);
759 mutex_unlock(&s->efr_lock);
762 static void sc16is7xx_reconf_rs485(struct uart_port *port)
764 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
765 SC16IS7XX_EFCR_RTS_INVERT_BIT;
767 struct serial_rs485 *rs485 = &port->rs485;
768 unsigned long irqflags;
770 spin_lock_irqsave(&port->lock, irqflags);
771 if (rs485->flags & SER_RS485_ENABLED) {
772 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
774 if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
775 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
777 spin_unlock_irqrestore(&port->lock, irqflags);
779 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
782 static void sc16is7xx_reg_proc(struct kthread_work *ws)
784 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
785 struct sc16is7xx_one_config config;
786 unsigned long irqflags;
788 spin_lock_irqsave(&one->port.lock, irqflags);
789 config = one->config;
790 memset(&one->config, 0, sizeof(one->config));
791 spin_unlock_irqrestore(&one->port.lock, irqflags);
793 if (config.flags & SC16IS7XX_RECONF_MD) {
794 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
795 SC16IS7XX_MCR_LOOP_BIT,
796 (one->port.mctrl & TIOCM_LOOP) ?
797 SC16IS7XX_MCR_LOOP_BIT : 0);
798 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
799 SC16IS7XX_MCR_RTS_BIT,
800 (one->port.mctrl & TIOCM_RTS) ?
801 SC16IS7XX_MCR_RTS_BIT : 0);
802 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
803 SC16IS7XX_MCR_DTR_BIT,
804 (one->port.mctrl & TIOCM_DTR) ?
805 SC16IS7XX_MCR_DTR_BIT : 0);
807 if (config.flags & SC16IS7XX_RECONF_IER)
808 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
809 config.ier_clear, 0);
811 if (config.flags & SC16IS7XX_RECONF_RS485)
812 sc16is7xx_reconf_rs485(&one->port);
815 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
817 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
818 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
820 one->config.flags |= SC16IS7XX_RECONF_IER;
821 one->config.ier_clear |= bit;
822 kthread_queue_work(&s->kworker, &one->reg_work);
825 static void sc16is7xx_stop_tx(struct uart_port *port)
827 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
830 static void sc16is7xx_stop_rx(struct uart_port *port)
832 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
835 static void sc16is7xx_start_tx(struct uart_port *port)
837 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
838 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
840 kthread_queue_work(&s->kworker, &one->tx_work);
843 static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
847 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
849 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
852 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
854 /* DCD and DSR are not wired and CTS/RTS is handled automatically
855 * so just indicate DSR and CAR asserted
857 return TIOCM_DSR | TIOCM_CAR;
860 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
862 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
863 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
865 one->config.flags |= SC16IS7XX_RECONF_MD;
866 kthread_queue_work(&s->kworker, &one->reg_work);
869 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
871 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
872 SC16IS7XX_LCR_TXBREAK_BIT,
873 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
876 static void sc16is7xx_set_termios(struct uart_port *port,
877 struct ktermios *termios,
878 struct ktermios *old)
880 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
881 unsigned int lcr, flow = 0;
884 /* Mask termios capabilities we don't support */
885 termios->c_cflag &= ~CMSPAR;
888 switch (termios->c_cflag & CSIZE) {
890 lcr = SC16IS7XX_LCR_WORD_LEN_5;
893 lcr = SC16IS7XX_LCR_WORD_LEN_6;
896 lcr = SC16IS7XX_LCR_WORD_LEN_7;
899 lcr = SC16IS7XX_LCR_WORD_LEN_8;
902 lcr = SC16IS7XX_LCR_WORD_LEN_8;
903 termios->c_cflag &= ~CSIZE;
904 termios->c_cflag |= CS8;
909 if (termios->c_cflag & PARENB) {
910 lcr |= SC16IS7XX_LCR_PARITY_BIT;
911 if (!(termios->c_cflag & PARODD))
912 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
916 if (termios->c_cflag & CSTOPB)
917 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
919 /* Set read status mask */
920 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
921 if (termios->c_iflag & INPCK)
922 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
923 SC16IS7XX_LSR_FE_BIT;
924 if (termios->c_iflag & (BRKINT | PARMRK))
925 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
927 /* Set status ignore mask */
928 port->ignore_status_mask = 0;
929 if (termios->c_iflag & IGNBRK)
930 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
931 if (!(termios->c_cflag & CREAD))
932 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
934 /* As above, claim the mutex while accessing the EFR. */
935 mutex_lock(&s->efr_lock);
937 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
938 SC16IS7XX_LCR_CONF_MODE_B);
940 /* Configure flow control */
941 regcache_cache_bypass(s->regmap, true);
942 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
943 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
944 if (termios->c_cflag & CRTSCTS)
945 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
946 SC16IS7XX_EFR_AUTORTS_BIT;
947 if (termios->c_iflag & IXON)
948 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
949 if (termios->c_iflag & IXOFF)
950 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
952 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
953 regcache_cache_bypass(s->regmap, false);
955 /* Update LCR register */
956 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
958 mutex_unlock(&s->efr_lock);
960 /* Get baud rate generator configuration */
961 baud = uart_get_baud_rate(port, termios, old,
962 port->uartclk / 16 / 4 / 0xffff,
965 /* Setup baudrate generator */
966 baud = sc16is7xx_set_baud(port, baud);
968 /* Update timeout according to new baud rate */
969 uart_update_timeout(port, termios->c_cflag, baud);
972 static int sc16is7xx_config_rs485(struct uart_port *port,
973 struct serial_rs485 *rs485)
975 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
976 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
978 if (rs485->flags & SER_RS485_ENABLED) {
979 bool rts_during_rx, rts_during_tx;
981 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND;
982 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND;
984 if (rts_during_rx == rts_during_tx)
986 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
987 rts_during_tx, rts_during_rx);
990 * RTS signal is handled by HW, it's timing can't be influenced.
991 * However, it's sometimes useful to delay TX even without RTS
992 * control therefore we try to handle .delay_rts_before_send.
994 if (rs485->delay_rts_after_send)
998 port->rs485 = *rs485;
999 one->config.flags |= SC16IS7XX_RECONF_RS485;
1000 kthread_queue_work(&s->kworker, &one->reg_work);
1005 static int sc16is7xx_startup(struct uart_port *port)
1007 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1008 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1011 sc16is7xx_power(port, 1);
1014 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
1015 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
1017 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
1018 SC16IS7XX_FCR_FIFO_BIT);
1021 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
1022 SC16IS7XX_LCR_CONF_MODE_B);
1024 regcache_cache_bypass(s->regmap, true);
1026 /* Enable write access to enhanced features and internal clock div */
1027 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
1028 SC16IS7XX_EFR_ENABLE_BIT);
1030 /* Enable TCR/TLR */
1031 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1032 SC16IS7XX_MCR_TCRTLR_BIT,
1033 SC16IS7XX_MCR_TCRTLR_BIT);
1035 /* Configure flow control levels */
1036 /* Flow control halt level 48, resume level 24 */
1037 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
1038 SC16IS7XX_TCR_RX_RESUME(24) |
1039 SC16IS7XX_TCR_RX_HALT(48));
1041 regcache_cache_bypass(s->regmap, false);
1043 /* Now, initialize the UART */
1044 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
1046 /* Enable IrDA mode if requested in DT */
1047 /* This bit must be written with LCR[7] = 0 */
1048 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1049 SC16IS7XX_MCR_IRDA_BIT,
1051 SC16IS7XX_MCR_IRDA_BIT : 0);
1053 /* Enable the Rx and Tx FIFO */
1054 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1055 SC16IS7XX_EFCR_RXDISABLE_BIT |
1056 SC16IS7XX_EFCR_TXDISABLE_BIT,
1059 /* Enable RX, TX interrupts */
1060 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT;
1061 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
1066 static void sc16is7xx_shutdown(struct uart_port *port)
1068 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1070 /* Disable all interrupts */
1071 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1073 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1074 SC16IS7XX_EFCR_RXDISABLE_BIT |
1075 SC16IS7XX_EFCR_TXDISABLE_BIT,
1076 SC16IS7XX_EFCR_RXDISABLE_BIT |
1077 SC16IS7XX_EFCR_TXDISABLE_BIT);
1079 sc16is7xx_power(port, 0);
1081 kthread_flush_worker(&s->kworker);
1084 static const char *sc16is7xx_type(struct uart_port *port)
1086 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1088 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1091 static int sc16is7xx_request_port(struct uart_port *port)
1097 static void sc16is7xx_config_port(struct uart_port *port, int flags)
1099 if (flags & UART_CONFIG_TYPE)
1100 port->type = PORT_SC16IS7XX;
1103 static int sc16is7xx_verify_port(struct uart_port *port,
1104 struct serial_struct *s)
1106 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1108 if (s->irq != port->irq)
1114 static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1115 unsigned int oldstate)
1117 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1120 static void sc16is7xx_null_void(struct uart_port *port)
1125 static const struct uart_ops sc16is7xx_ops = {
1126 .tx_empty = sc16is7xx_tx_empty,
1127 .set_mctrl = sc16is7xx_set_mctrl,
1128 .get_mctrl = sc16is7xx_get_mctrl,
1129 .stop_tx = sc16is7xx_stop_tx,
1130 .start_tx = sc16is7xx_start_tx,
1131 .stop_rx = sc16is7xx_stop_rx,
1132 .break_ctl = sc16is7xx_break_ctl,
1133 .startup = sc16is7xx_startup,
1134 .shutdown = sc16is7xx_shutdown,
1135 .set_termios = sc16is7xx_set_termios,
1136 .type = sc16is7xx_type,
1137 .request_port = sc16is7xx_request_port,
1138 .release_port = sc16is7xx_null_void,
1139 .config_port = sc16is7xx_config_port,
1140 .verify_port = sc16is7xx_verify_port,
1144 #ifdef CONFIG_GPIOLIB
1145 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1148 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1149 struct uart_port *port = &s->p[0].port;
1151 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1153 return !!(val & BIT(offset));
1156 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1158 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1159 struct uart_port *port = &s->p[0].port;
1161 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1162 val ? BIT(offset) : 0);
1165 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1168 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1169 struct uart_port *port = &s->p[0].port;
1171 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1176 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1177 unsigned offset, int val)
1179 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1180 struct uart_port *port = &s->p[0].port;
1181 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1184 state |= BIT(offset);
1186 state &= ~BIT(offset);
1189 * If we write IOSTATE first, and then IODIR, the output value is not
1190 * transferred to the corresponding I/O pin.
1191 * The datasheet states that each register bit will be transferred to
1192 * the corresponding I/O pin programmed as output when writing to
1193 * IOSTATE. Therefore, configure direction first with IODIR, and then
1194 * set value after with IOSTATE.
1196 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1198 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
1204 static int sc16is7xx_probe(struct device *dev,
1205 const struct sc16is7xx_devtype *devtype,
1206 struct regmap *regmap, int irq)
1208 unsigned long freq = 0, *pfreq = dev_get_platdata(dev);
1212 struct sc16is7xx_port *s;
1215 return PTR_ERR(regmap);
1218 * This device does not have an identification register that would
1219 * tell us if we are really connected to the correct device.
1220 * The best we can do is to check if communication is at all possible.
1222 ret = regmap_read(regmap,
1223 SC16IS7XX_LSR_REG << SC16IS7XX_REG_SHIFT, &val);
1225 return -EPROBE_DEFER;
1227 /* Alloc port structure */
1228 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL);
1230 dev_err(dev, "Error allocating port structure\n");
1234 /* Always ask for fixed clock rate from a property. */
1235 device_property_read_u32(dev, "clock-frequency", &uartclk);
1237 s->clk = devm_clk_get(dev, NULL);
1238 if (IS_ERR(s->clk)) {
1244 dev_dbg(dev, "Clock frequency: %luHz\n", freq);
1246 return PTR_ERR(s->clk);
1248 ret = clk_prepare_enable(s->clk);
1252 freq = clk_get_rate(s->clk);
1256 s->devtype = devtype;
1257 dev_set_drvdata(dev, s);
1258 mutex_init(&s->efr_lock);
1260 kthread_init_worker(&s->kworker);
1261 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1263 if (IS_ERR(s->kworker_task)) {
1264 ret = PTR_ERR(s->kworker_task);
1267 sched_set_fifo(s->kworker_task);
1269 /* reset device, purging any pending irq / data */
1270 regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT,
1271 SC16IS7XX_IOCONTROL_SRESET_BIT);
1273 for (i = 0; i < devtype->nr_uart; ++i) {
1275 /* Initialize port data */
1276 s->p[i].port.dev = dev;
1277 s->p[i].port.irq = irq;
1278 s->p[i].port.type = PORT_SC16IS7XX;
1279 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1280 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1281 s->p[i].port.iobase = i;
1283 * Use all ones as membase to make sure uart_configure_port() in
1284 * serial_core.c does not abort for SPI/I2C devices where the
1285 * membase address is not applicable.
1287 s->p[i].port.membase = (void __iomem *)~0;
1288 s->p[i].port.iotype = UPIO_PORT;
1289 s->p[i].port.uartclk = freq;
1290 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
1291 s->p[i].port.ops = &sc16is7xx_ops;
1292 s->p[i].port.line = sc16is7xx_alloc_line();
1293 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) {
1298 /* Disable all interrupts */
1299 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1301 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1302 SC16IS7XX_EFCR_RXDISABLE_BIT |
1303 SC16IS7XX_EFCR_TXDISABLE_BIT);
1304 /* Initialize kthread work structs */
1305 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
1306 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
1308 uart_add_one_port(&sc16is7xx_uart, &s->p[i].port);
1311 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG,
1312 SC16IS7XX_LCR_CONF_MODE_B);
1314 regcache_cache_bypass(s->regmap, true);
1316 /* Enable write access to enhanced features */
1317 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG,
1318 SC16IS7XX_EFR_ENABLE_BIT);
1320 regcache_cache_bypass(s->regmap, false);
1322 /* Restore access to general registers */
1323 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00);
1325 /* Go to suspend mode */
1326 sc16is7xx_power(&s->p[i].port, 0);
1330 struct property *prop;
1334 of_property_for_each_u32(dev->of_node, "irda-mode-ports",
1336 if (u < devtype->nr_uart)
1337 s->p[u].irda_mode = true;
1340 #ifdef CONFIG_GPIOLIB
1341 if (devtype->nr_gpio) {
1342 /* Setup GPIO cotroller */
1343 s->gpio.owner = THIS_MODULE;
1344 s->gpio.parent = dev;
1345 s->gpio.label = dev_name(dev);
1346 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1347 s->gpio.get = sc16is7xx_gpio_get;
1348 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1349 s->gpio.set = sc16is7xx_gpio_set;
1351 s->gpio.ngpio = devtype->nr_gpio;
1352 s->gpio.can_sleep = 1;
1353 ret = gpiochip_add_data(&s->gpio, s);
1360 * Setup interrupt. We first try to acquire the IRQ line as level IRQ.
1361 * If that succeeds, we can allow sharing the interrupt as well.
1362 * In case the interrupt controller doesn't support that, we fall
1363 * back to a non-shared falling-edge trigger.
1365 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1366 IRQF_TRIGGER_LOW | IRQF_SHARED |
1372 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1373 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1378 #ifdef CONFIG_GPIOLIB
1379 if (devtype->nr_gpio)
1380 gpiochip_remove(&s->gpio);
1386 for (i--; i >= 0; i--) {
1387 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1388 clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1391 kthread_stop(s->kworker_task);
1394 if (!IS_ERR(s->clk))
1395 clk_disable_unprepare(s->clk);
1400 static int sc16is7xx_remove(struct device *dev)
1402 struct sc16is7xx_port *s = dev_get_drvdata(dev);
1405 #ifdef CONFIG_GPIOLIB
1406 if (s->devtype->nr_gpio)
1407 gpiochip_remove(&s->gpio);
1410 for (i = 0; i < s->devtype->nr_uart; i++) {
1411 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1412 clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1413 sc16is7xx_power(&s->p[i].port, 0);
1416 kthread_flush_worker(&s->kworker);
1417 kthread_stop(s->kworker_task);
1419 if (!IS_ERR(s->clk))
1420 clk_disable_unprepare(s->clk);
1425 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1426 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1427 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1428 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1429 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1430 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1431 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1434 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1436 static struct regmap_config regcfg = {
1440 .cache_type = REGCACHE_RBTREE,
1441 .volatile_reg = sc16is7xx_regmap_volatile,
1442 .precious_reg = sc16is7xx_regmap_precious,
1443 .writeable_noinc_reg = sc16is7xx_regmap_noinc,
1444 .readable_noinc_reg = sc16is7xx_regmap_noinc,
1447 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1448 static int sc16is7xx_spi_probe(struct spi_device *spi)
1450 const struct sc16is7xx_devtype *devtype;
1451 struct regmap *regmap;
1455 spi->bits_per_word = 8;
1456 /* For all variants, only mode 0 is supported */
1457 if ((spi->mode & SPI_MODE_X_MASK) != SPI_MODE_0)
1458 return dev_err_probe(&spi->dev, -EINVAL, "Unsupported SPI mode\n");
1460 spi->mode = spi->mode ? : SPI_MODE_0;
1461 spi->max_speed_hz = spi->max_speed_hz ? : 4 * HZ_PER_MHZ;
1462 ret = spi_setup(spi);
1466 if (spi->dev.of_node) {
1467 devtype = device_get_match_data(&spi->dev);
1471 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1473 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1476 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1477 (devtype->nr_uart - 1);
1478 regmap = devm_regmap_init_spi(spi, ®cfg);
1480 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq);
1483 static int sc16is7xx_spi_remove(struct spi_device *spi)
1485 return sc16is7xx_remove(&spi->dev);
1488 static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1489 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1490 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1491 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1492 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1493 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1494 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1495 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1499 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1501 static struct spi_driver sc16is7xx_spi_uart_driver = {
1503 .name = SC16IS7XX_NAME,
1504 .of_match_table = sc16is7xx_dt_ids,
1506 .probe = sc16is7xx_spi_probe,
1507 .remove = sc16is7xx_spi_remove,
1508 .id_table = sc16is7xx_spi_id_table,
1511 MODULE_ALIAS("spi:sc16is7xx");
1514 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1515 static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1516 const struct i2c_device_id *id)
1518 const struct sc16is7xx_devtype *devtype;
1519 struct regmap *regmap;
1521 if (i2c->dev.of_node) {
1522 devtype = device_get_match_data(&i2c->dev);
1526 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1529 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1530 (devtype->nr_uart - 1);
1531 regmap = devm_regmap_init_i2c(i2c, ®cfg);
1533 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq);
1536 static int sc16is7xx_i2c_remove(struct i2c_client *client)
1538 return sc16is7xx_remove(&client->dev);
1541 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1542 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1543 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1544 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1545 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1546 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1547 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1548 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1551 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1553 static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1555 .name = SC16IS7XX_NAME,
1556 .of_match_table = sc16is7xx_dt_ids,
1558 .probe = sc16is7xx_i2c_probe,
1559 .remove = sc16is7xx_i2c_remove,
1560 .id_table = sc16is7xx_i2c_id_table,
1565 static int __init sc16is7xx_init(void)
1569 ret = uart_register_driver(&sc16is7xx_uart);
1571 pr_err("Registering UART driver failed\n");
1575 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1576 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1578 pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1583 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1584 ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1586 pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1592 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1595 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1596 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1599 uart_unregister_driver(&sc16is7xx_uart);
1602 module_init(sc16is7xx_init);
1604 static void __exit sc16is7xx_exit(void)
1606 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1607 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1610 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1611 spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1613 uart_unregister_driver(&sc16is7xx_uart);
1615 module_exit(sc16is7xx_exit);
1617 MODULE_LICENSE("GPL");
1618 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1619 MODULE_DESCRIPTION("SC16IS7XX serial driver");