1 /*************************************************************************/
2 /* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */
4 /* Module Name : rom_cfg.h */
7 /* This file contains definition of platform and sysmte config . */
12 /*************************************************************************/
17 /************************** FPGA version **************************/
18 #define MAGPIE_FPGA_RAM_256K 1
20 /************************** SYSTEM WIDE ***************************/
22 * D : Daily build (Development)
23 * R : Official Release
25 #define ATH_VER_RELEASE_CODE "D"
26 #define ATH_VER_PLATFORM_NUMBER "0"
27 #define ATH_VER_MAJOR_NUMBER "0"
28 #define ATH_VER_MINOR_NUMBER "0"
29 #define ATH_VER_BUILD_NUMBER "3"
31 #define ATH_VER_DATES __DATE__" "__TIME__
33 #define ATH_VERSION_STR "["ATH_VER_RELEASE_CODE "." \
34 ATH_VER_PLATFORM_NUMBER "." \
35 ATH_VER_MAJOR_NUMBER "." \
36 ATH_VER_MINOR_NUMBER "." \
37 ATH_VER_BUILD_NUMBER "] " \
40 /* ROM Code Version (16 bit)
41 * Bit 15 : 0 means ASIC, 1 means FPGA
42 * Bit 14 : 0 means ROM, 1 means FLASH
43 * Bit 13-8 : Major Version Number
44 * Bit 7-0 : Minor Version Number
46 #if defined(MAGPIE_FPGA)
47 #define ROM_PLATFORM (1)
49 #define ROM_PLATFORM (0)
52 /* Define ROM Code Version Number here */
53 #define ROM_MAJOR_VER_NUM (1)
54 #define ROM_MINOR_VER_NUM (11)
56 #define BOOTROM_VER ( (ROM_PLATFORM<<15) | (ROM_MAJOR_VER_NUM<<8) | ROM_MINOR_VER_NUM )
59 #define SYSTEM_FREQ 40
61 #define SYSTEM_CLK SYSTEM_FREQ*1000*1000 //40mhz
63 #define ONE_MSEC (SYSTEM_FREQ*1000)
65 /////////////////////////////////////////////////////////////////
67 * Supported reference clock speeds.
69 * Note: MAC HAL code has multiple tables indexed by these values,
70 * so do not rearrange them. Add any new refclk values at the end.
73 SYS_CFG_REFCLK_UNKNOWN = -1, /* Unsupported ref clock -- use PLL Bypass */
74 SYS_CFG_REFCLK_10_MHZ = 0,
75 SYS_CFG_REFCLK_20_MHZ = 1,
76 SYS_CFG_REFCLK_40_MHZ = 2,
79 /////////////////////////////////////////////////////////////////
82 /////////////////////////////////////////////////////////////////
85 #define SYSTEM_MODULE_MEM 1
87 #define SYSTEM_MODULE_MISC 1
89 #define SYSTEM_MODULE_USB 1
92 #define SYSTEM_MODULE_HP_EP1 1
93 #define SYSTEM_MODULE_HP_EP5 1
94 #define SYSTEM_MODULE_HP_EP6 1
97 #define SYSTEM_MODULE_INTR 1
99 #define SYSTEM_MODULE_CLOCK 1
101 #define SYSTEM_MODULE_DESC 0
103 #define SYSTEM_MODULE_ALLOCRAM 1
105 #define SYSTEM_MODULE_UART 1 //uart module to dump the dbg message
107 #define SYSTEM_MODULE_TIMER 1 // a virtual timer, before we don't have the real timer
109 #define SYSTEM_MODULE_WDT 1 // a watchdog timer
111 #define SYSTEM_MODULE_EEPROM 1 // a eeprom interface (pcie_rc's eeprom not apb eeprom)
113 #if SYSTEM_MODULE_UART
114 #define SYSTEM_MODULE_PRINT 1 // dependency on UART module
115 #define SYSTEM_MODULE_DBG 0 // dependency on PRINT & UART module
118 #define SYSTEM_MODULE_ROM_PATCH 1 // patch install module
120 #define SYSTEM_MODULE_PCI 1
122 #define SYSTEM_MODULE_GMAC 0
124 #define SYSTEM_MODULE_SFLASH 1
126 #define SYSTEM_MODULE_TESTING 0 // backdoor test module
128 #if SYSTEM_MODULE_TESTING
129 #define SYSTEM_MODULE_MEMORY_TEST 0
130 #define SYSTEM_MODULE_DHRYSTONE_TEST 0
132 #define SYSTEM_MODULE_SYS_MONITOR 0
133 #define SYSTEM_MODULE_IDLE_TASK 0
135 #endif /* SYSTEM_MODULE_TESTING */
137 /****************************** UART ******************************/
138 #define UART_INPUT_CLK SYSTEM_CLK
139 #define UART_DEFAULT_BAUD 115200
140 #define UART_RETRY_COUNT 10000
142 /****************************** USB *******************************/
144 /* Firmware Loopback */
145 #define ZM_FM_LOOPBACK 0
146 #define ZM_SELF_TEST_MODE 1 // USB-IF Eye Pattern Test
148 #define ENABLE_SWAP_DATA_MODE 1 // byte swap function
149 #define ENABLE_SW_SWAP_DATA_MODE 1
151 #define ENABLE_STREAM_MODE 0 // stream mode
153 #define USB_STREAM_MODE_AGG_CNT 0 // 2 packets, 2: 3packets, 3: 4packets etc...
154 #define USB_STREAM_MODE_TIMEOUT_CTRL 0x0 // the unit is 32 USB (30Mhz) clock cycles
155 #define USB_STREAM_MODE_HOST_BUF_SZ (BIT4) // define the host dma buffer size (bit5,bit4)- 4096(0,0) 8192 (0,1) 16384(1,0) 32768(1,1) bytes
157 /************************* MEMORY DEFS ***************************/
159 #if defined(PROJECT_MAGPIE)
160 #include "magpie_mem.h"
161 #elif defined(PROJECT_K2)
166 // the end of 16 bytes are used to record some debug state and watchdog event and counter
167 #define WATCH_DOG_MAGIC_PATTERN_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0x4) // 0x53fffc,magic pattern address
168 #define WATCH_DOG_RESET_COUNTER_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0x8) // 0x53fff8,record the reset counter
169 #define DEBUG_SYSTEM_STATE_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0xc) // 0x53fff4,record the state of system
170 #define CURRENT_PROGRAM_ADDR (SYS_D_RAM_REGION_0_BASE+SYS_RAM_SZIE-0x10) // 0x53fff0,reserved
172 #define WATCH_DOG_MAGIC_PATTERN (*((volatile u32_t*)(WATCH_DOG_MAGIC_PATTERN_ADDR)))
173 #define WATCH_DOG_RESET_COUNTER (*((volatile u32_t*)(WATCH_DOG_RESET_COUNTER_ADDR)))
174 #define DEBUG_SYSTEM_STATE (*((volatile u32_t*)(DEBUG_SYSTEM_STATE_ADDR)))
175 #define CURRENT_PROGRAM (*((volatile u32_t*)(CURRENT_PROGRAM_ADDR)))
177 #define WDT_MAGIC_PATTERN 0x5F574454 //_WDT
178 #define SUS_MAGIC_PATTERN 0x5F535553 //_SUS
181 /************************* WLAN DEFS ***************************/
182 //#define MAGPIE_ENABLE_WLAN 1
183 //#define MAGPIE_ENABLE_PCIE 1
184 //#define MAGPIE_ENABLE_WLAN_IN_TARGET 0
185 //#define MAGPIE_ENABLE_WLAN_SELF_TX 0
187 /****************************** WATCH DOG *******************************/
188 #define WDT_DEFAULT_TIMEOUT_VALUE 3*ONE_MSEC*1000 // Initial value is 3 seconds, firmware changes it to 65 milliseconds
190 #endif /* _ROM_CFG_H_ */