samsung_tty.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver core for Samsung SoC onboard UARTs.
   4  *
   5  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   6  *      http://armlinux.simtec.co.uk/
   7  */
   8
   9 /* Note on 2410 error handling
  10  *
  11  * The s3c2410 manual has a love/hate affair with the contents of the
  12  * UERSTAT register in the UART blocks, and keeps marking some of the
  13  * error bits as reserved. Having checked with the s3c2410x01,
  14  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  15  * feature from the latter versions of the manual.
  16  *
  17  * If it becomes aparrent that latter versions of the 2410 remove these
  18  * bits, then action will have to be taken to differentiate the versions
  19  * and change the policy on BREAK
  20  *
  21  * BJD, 04-Nov-2004
  22  */
  23
  24 #include <linux/dmaengine.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include <linux/ioport.h>
  29 #include <linux/io.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/init.h>
  32 #include <linux/sysrq.h>
  33 #include <linux/console.h>
  34 #include <linux/tty.h>
  35 #include <linux/tty_flip.h>
  36 #include <linux/serial_core.h>
  37 #include <linux/serial.h>
  38 #include <linux/serial_s3c.h>
  39 #include <linux/delay.h>
  40 #include <linux/clk.h>
  41 #include <linux/cpufreq.h>
  42 #include <linux/of.h>
  43 #include <asm/irq.h>
  44
  45 /* UART name and device definitions */
  46
  47 #define S3C24XX_SERIAL_NAME     "ttySAC"
  48 #define S3C24XX_SERIAL_MAJOR    204
  49 #define S3C24XX_SERIAL_MINOR    64
  50
  51 #define S3C24XX_TX_PIO                  1
  52 #define S3C24XX_TX_DMA                  2
  53 #define S3C24XX_RX_PIO                  1
  54 #define S3C24XX_RX_DMA                  2
  55
  56 /* flag to ignore all characters coming in */
  57 #define RXSTAT_DUMMY_READ (0x10000000)
  58
  59 struct s3c24xx_uart_info {
  60         char                    *name;
  61         unsigned int            type;
  62         unsigned int            fifosize;
  63         unsigned long           rx_fifomask;
  64         unsigned long           rx_fifoshift;
  65         unsigned long           rx_fifofull;
  66         unsigned long           tx_fifomask;
  67         unsigned long           tx_fifoshift;
  68         unsigned long           tx_fifofull;
  69         unsigned int            def_clk_sel;
  70         unsigned long           num_clks;
  71         unsigned long           clksel_mask;
  72         unsigned long           clksel_shift;
  73
  74         /* uart port features */
  75
  76         unsigned int            has_divslot:1;
  77 };
  78
  79 struct s3c24xx_serial_drv_data {
  80         struct s3c24xx_uart_info        *info;
  81         struct s3c2410_uartcfg          *def_cfg;
  82         unsigned int                    fifosize[CONFIG_SERIAL_SAMSUNG_UARTS];
  83 };
  84
  85 struct s3c24xx_uart_dma {
  86         unsigned int                    rx_chan_id;
  87         unsigned int                    tx_chan_id;
  88
  89         struct dma_slave_config         rx_conf;
  90         struct dma_slave_config         tx_conf;
  91
  92         struct dma_chan                 *rx_chan;
  93         struct dma_chan                 *tx_chan;
  94
  95         dma_addr_t                      rx_addr;
  96         dma_addr_t                      tx_addr;
  97
  98         dma_cookie_t                    rx_cookie;
  99         dma_cookie_t                    tx_cookie;
 100
 101         char                            *rx_buf;
 102
 103         dma_addr_t                      tx_transfer_addr;
 104
 105         size_t                          rx_size;
 106         size_t                          tx_size;
 107
 108         struct dma_async_tx_descriptor  *tx_desc;
 109         struct dma_async_tx_descriptor  *rx_desc;
 110
 111         int                             tx_bytes_requested;
 112         int                             rx_bytes_requested;
 113 };
 114
 115 struct s3c24xx_uart_port {
 116         unsigned char                   rx_claimed;
 117         unsigned char                   tx_claimed;
 118         unsigned char                   rx_enabled;
 119         unsigned char                   tx_enabled;
 120         unsigned int                    pm_level;
 121         unsigned long                   baudclk_rate;
 122         unsigned int                    min_dma_size;
 123
 124         unsigned int                    rx_irq;
 125         unsigned int                    tx_irq;
 126
 127         unsigned int                    tx_in_progress;
 128         unsigned int                    tx_mode;
 129         unsigned int                    rx_mode;
 130
 131         struct s3c24xx_uart_info        *info;
 132         struct clk                      *clk;
 133         struct clk                      *baudclk;
 134         struct uart_port                port;
 135         struct s3c24xx_serial_drv_data  *drv_data;
 136
 137         /* reference to platform data */
 138         struct s3c2410_uartcfg          *cfg;
 139
 140         struct s3c24xx_uart_dma         *dma;
 141
 142 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
 143         struct notifier_block           freq_transition;
 144 #endif
 145 };
 146
 147 /* conversion functions */
 148
 149 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
 150
 151 /* register access controls */
 152
 153 #define portaddr(port, reg) ((port)->membase + (reg))
 154 #define portaddrl(port, reg) \
 155         ((unsigned long *)(unsigned long)((port)->membase + (reg)))
 156
 157 static u32 rd_reg(struct uart_port *port, u32 reg)
 158 {
 159         switch (port->iotype) {
 160         case UPIO_MEM:
 161                 return readb_relaxed(portaddr(port, reg));
 162         case UPIO_MEM32:
 163                 return readl_relaxed(portaddr(port, reg));
 164         default:
 165                 return 0;
 166         }
 167         return 0;
 168 }
 169
 170 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
 171
 172 static void wr_reg(struct uart_port *port, u32 reg, u32 val)
 173 {
 174         switch (port->iotype) {
 175         case UPIO_MEM:
 176                 writeb_relaxed(val, portaddr(port, reg));
 177                 break;
 178         case UPIO_MEM32:
 179                 writel_relaxed(val, portaddr(port, reg));
 180                 break;
 181         }
 182 }
 183
 184 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
 185
 186 /* Byte-order aware bit setting/clearing functions. */
 187
 188 static inline void s3c24xx_set_bit(struct uart_port *port, int idx,
 189                                    unsigned int reg)
 190 {
 191         unsigned long flags;
 192         u32 val;
 193
 194         local_irq_save(flags);
 195         val = rd_regl(port, reg);
 196         val |= (1 << idx);
 197         wr_regl(port, reg, val);
 198         local_irq_restore(flags);
 199 }
 200
 201 static inline void s3c24xx_clear_bit(struct uart_port *port, int idx,
 202                                      unsigned int reg)
 203 {
 204         unsigned long flags;
 205         u32 val;
 206
 207         local_irq_save(flags);
 208         val = rd_regl(port, reg);
 209         val &= ~(1 << idx);
 210         wr_regl(port, reg, val);
 211         local_irq_restore(flags);
 212 }
 213
 214 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
 215 {
 216         return container_of(port, struct s3c24xx_uart_port, port);
 217 }
 218
 219 /* translate a port to the device name */
 220
 221 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
 222 {
 223         return to_platform_device(port->dev)->name;
 224 }
 225
 226 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
 227 {
 228         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 229 }
 230
 231 /*
 232  * s3c64xx and later SoC's include the interrupt mask and status registers in
 233  * the controller itself, unlike the s3c24xx SoC's which have these registers
 234  * in the interrupt controller. Check if the port type is s3c64xx or higher.
 235  */
 236 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
 237 {
 238         return to_ourport(port)->info->type == PORT_S3C6400;
 239 }
 240
 241 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 242 {
 243         struct s3c24xx_uart_port *ourport = to_ourport(port);
 244         unsigned long flags;
 245         unsigned int ucon, ufcon;
 246         int count = 10000;
 247
 248         spin_lock_irqsave(&port->lock, flags);
 249
 250         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 251                 udelay(100);
 252
 253         ufcon = rd_regl(port, S3C2410_UFCON);
 254         ufcon |= S3C2410_UFCON_RESETRX;
 255         wr_regl(port, S3C2410_UFCON, ufcon);
 256
 257         ucon = rd_regl(port, S3C2410_UCON);
 258         ucon |= S3C2410_UCON_RXIRQMODE;
 259         wr_regl(port, S3C2410_UCON, ucon);
 260
 261         ourport->rx_enabled = 1;
 262         spin_unlock_irqrestore(&port->lock, flags);
 263 }
 264
 265 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 266 {
 267         struct s3c24xx_uart_port *ourport = to_ourport(port);
 268         unsigned long flags;
 269         unsigned int ucon;
 270
 271         spin_lock_irqsave(&port->lock, flags);
 272
 273         ucon = rd_regl(port, S3C2410_UCON);
 274         ucon &= ~S3C2410_UCON_RXIRQMODE;
 275         wr_regl(port, S3C2410_UCON, ucon);
 276
 277         ourport->rx_enabled = 0;
 278         spin_unlock_irqrestore(&port->lock, flags);
 279 }
 280
 281 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 282 {
 283         struct s3c24xx_uart_port *ourport = to_ourport(port);
 284         struct s3c24xx_uart_dma *dma = ourport->dma;
 285         struct circ_buf *xmit = &port->state->xmit;
 286         struct dma_tx_state state;
 287         int count;
 288
 289         if (!ourport->tx_enabled)
 290                 return;
 291
 292         if (s3c24xx_serial_has_interrupt_mask(port))
 293                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 294         else
 295                 disable_irq_nosync(ourport->tx_irq);
 296
 297         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 298                 dmaengine_pause(dma->tx_chan);
 299                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 300                 dmaengine_terminate_all(dma->tx_chan);
 301                 dma_sync_single_for_cpu(ourport->port.dev,
 302                         dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
 303                 async_tx_ack(dma->tx_desc);
 304                 count = dma->tx_bytes_requested - state.residue;
 305                 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 306                 port->icount.tx += count;
 307         }
 308
 309         ourport->tx_enabled = 0;
 310         ourport->tx_in_progress = 0;
 311
 312         if (port->flags & UPF_CONS_FLOW)
 313                 s3c24xx_serial_rx_enable(port);
 314
 315         ourport->tx_mode = 0;
 316 }
 317
 318 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 319
 320 static void s3c24xx_serial_tx_dma_complete(void *args)
 321 {
 322         struct s3c24xx_uart_port *ourport = args;
 323         struct uart_port *port = &ourport->port;
 324         struct circ_buf *xmit = &port->state->xmit;
 325         struct s3c24xx_uart_dma *dma = ourport->dma;
 326         struct dma_tx_state state;
 327         unsigned long flags;
 328         int count;
 329
 330         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 331         count = dma->tx_bytes_requested - state.residue;
 332         async_tx_ack(dma->tx_desc);
 333
 334         dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
 335                                 dma->tx_size, DMA_TO_DEVICE);
 336
 337         spin_lock_irqsave(&port->lock, flags);
 338
 339         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 340         port->icount.tx += count;
 341         ourport->tx_in_progress = 0;
 342
 343         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 344                 uart_write_wakeup(port);
 345
 346         s3c24xx_serial_start_next_tx(ourport);
 347         spin_unlock_irqrestore(&port->lock, flags);
 348 }
 349
 350 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 351 {
 352         struct uart_port *port = &ourport->port;
 353         u32 ucon;
 354
 355         /* Mask Tx interrupt */
 356         if (s3c24xx_serial_has_interrupt_mask(port))
 357                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 358         else
 359                 disable_irq_nosync(ourport->tx_irq);
 360
 361         /* Enable tx dma mode */
 362         ucon = rd_regl(port, S3C2410_UCON);
 363         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 364         ucon |= S3C64XX_UCON_TXBURST_1;
 365         ucon |= S3C64XX_UCON_TXMODE_DMA;
 366         wr_regl(port,  S3C2410_UCON, ucon);
 367
 368         ourport->tx_mode = S3C24XX_TX_DMA;
 369 }
 370
 371 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 372 {
 373         struct uart_port *port = &ourport->port;
 374         u32 ucon, ufcon;
 375
 376         /* Set ufcon txtrig */
 377         ourport->tx_in_progress = S3C24XX_TX_PIO;
 378         ufcon = rd_regl(port, S3C2410_UFCON);
 379         wr_regl(port,  S3C2410_UFCON, ufcon);
 380
 381         /* Enable tx pio mode */
 382         ucon = rd_regl(port, S3C2410_UCON);
 383         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 384         ucon |= S3C64XX_UCON_TXMODE_CPU;
 385         wr_regl(port,  S3C2410_UCON, ucon);
 386
 387         /* Unmask Tx interrupt */
 388         if (s3c24xx_serial_has_interrupt_mask(port))
 389                 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 390                                   S3C64XX_UINTM);
 391         else
 392                 enable_irq(ourport->tx_irq);
 393
 394         ourport->tx_mode = S3C24XX_TX_PIO;
 395 }
 396
 397 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 398 {
 399         if (ourport->tx_mode != S3C24XX_TX_PIO)
 400                 enable_tx_pio(ourport);
 401 }
 402
 403 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 404                                       unsigned int count)
 405 {
 406         struct uart_port *port = &ourport->port;
 407         struct circ_buf *xmit = &port->state->xmit;
 408         struct s3c24xx_uart_dma *dma = ourport->dma;
 409
 410         if (ourport->tx_mode != S3C24XX_TX_DMA)
 411                 enable_tx_dma(ourport);
 412
 413         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 414         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 415
 416         dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
 417                                 dma->tx_size, DMA_TO_DEVICE);
 418
 419         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 420                                 dma->tx_transfer_addr, dma->tx_size,
 421                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 422         if (!dma->tx_desc) {
 423                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 424                 return -EIO;
 425         }
 426
 427         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 428         dma->tx_desc->callback_param = ourport;
 429         dma->tx_bytes_requested = dma->tx_size;
 430
 431         ourport->tx_in_progress = S3C24XX_TX_DMA;
 432         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 433         dma_async_issue_pending(dma->tx_chan);
 434         return 0;
 435 }
 436
 437 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 438 {
 439         struct uart_port *port = &ourport->port;
 440         struct circ_buf *xmit = &port->state->xmit;
 441         unsigned long count;
 442
 443         /* Get data size up to the end of buffer */
 444         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 445
 446         if (!count) {
 447                 s3c24xx_serial_stop_tx(port);
 448                 return;
 449         }
 450
 451         if (!ourport->dma || !ourport->dma->tx_chan ||
 452             count < ourport->min_dma_size ||
 453             xmit->tail & (dma_get_cache_alignment() - 1))
 454                 s3c24xx_serial_start_tx_pio(ourport);
 455         else
 456                 s3c24xx_serial_start_tx_dma(ourport, count);
 457 }
 458
 459 static void s3c24xx_serial_start_tx(struct uart_port *port)
 460 {
 461         struct s3c24xx_uart_port *ourport = to_ourport(port);
 462         struct circ_buf *xmit = &port->state->xmit;
 463
 464         if (!ourport->tx_enabled) {
 465                 if (port->flags & UPF_CONS_FLOW)
 466                         s3c24xx_serial_rx_disable(port);
 467
 468                 ourport->tx_enabled = 1;
 469                 if (!ourport->dma || !ourport->dma->tx_chan)
 470                         s3c24xx_serial_start_tx_pio(ourport);
 471         }
 472
 473         if (ourport->dma && ourport->dma->tx_chan) {
 474                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 475                         s3c24xx_serial_start_next_tx(ourport);
 476         }
 477 }
 478
 479 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 480                 struct tty_port *tty, int count)
 481 {
 482         struct s3c24xx_uart_dma *dma = ourport->dma;
 483         int copied;
 484
 485         if (!count)
 486                 return;
 487
 488         dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
 489                                 dma->rx_size, DMA_FROM_DEVICE);
 490
 491         ourport->port.icount.rx += count;
 492         if (!tty) {
 493                 dev_err(ourport->port.dev, "No tty port\n");
 494                 return;
 495         }
 496         copied = tty_insert_flip_string(tty,
 497                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 498         if (copied != count) {
 499                 WARN_ON(1);
 500                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 501         }
 502 }
 503
 504 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 505 {
 506         struct s3c24xx_uart_port *ourport = to_ourport(port);
 507         struct s3c24xx_uart_dma *dma = ourport->dma;
 508         struct tty_port *t = &port->state->port;
 509         struct dma_tx_state state;
 510         enum dma_status dma_status;
 511         unsigned int received;
 512
 513         if (ourport->rx_enabled) {
 514                 dev_dbg(port->dev, "stopping rx\n");
 515                 if (s3c24xx_serial_has_interrupt_mask(port))
 516                         s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 517                                         S3C64XX_UINTM);
 518                 else
 519                         disable_irq_nosync(ourport->rx_irq);
 520                 ourport->rx_enabled = 0;
 521         }
 522         if (dma && dma->rx_chan) {
 523                 dmaengine_pause(dma->tx_chan);
 524                 dma_status = dmaengine_tx_status(dma->rx_chan,
 525                                 dma->rx_cookie, &state);
 526                 if (dma_status == DMA_IN_PROGRESS ||
 527                         dma_status == DMA_PAUSED) {
 528                         received = dma->rx_bytes_requested - state.residue;
 529                         dmaengine_terminate_all(dma->rx_chan);
 530                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 531                 }
 532         }
 533 }
 534
 535 static inline struct s3c24xx_uart_info
 536         *s3c24xx_port_to_info(struct uart_port *port)
 537 {
 538         return to_ourport(port)->info;
 539 }
 540
 541 static inline struct s3c2410_uartcfg
 542         *s3c24xx_port_to_cfg(struct uart_port *port)
 543 {
 544         struct s3c24xx_uart_port *ourport;
 545
 546         if (port->dev == NULL)
 547                 return NULL;
 548
 549         ourport = container_of(port, struct s3c24xx_uart_port, port);
 550         return ourport->cfg;
 551 }
 552
 553 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
 554                                      unsigned long ufstat)
 555 {
 556         struct s3c24xx_uart_info *info = ourport->info;
 557
 558         if (ufstat & info->rx_fifofull)
 559                 return ourport->port.fifosize;
 560
 561         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 562 }
 563
 564 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 565 static void s3c24xx_serial_rx_dma_complete(void *args)
 566 {
 567         struct s3c24xx_uart_port *ourport = args;
 568         struct uart_port *port = &ourport->port;
 569
 570         struct s3c24xx_uart_dma *dma = ourport->dma;
 571         struct tty_port *t = &port->state->port;
 572         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 573
 574         struct dma_tx_state state;
 575         unsigned long flags;
 576         int received;
 577
 578         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 579         received  = dma->rx_bytes_requested - state.residue;
 580         async_tx_ack(dma->rx_desc);
 581
 582         spin_lock_irqsave(&port->lock, flags);
 583
 584         if (received)
 585                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 586
 587         if (tty) {
 588                 tty_flip_buffer_push(t);
 589                 tty_kref_put(tty);
 590         }
 591
 592         s3c64xx_start_rx_dma(ourport);
 593
 594         spin_unlock_irqrestore(&port->lock, flags);
 595 }
 596
 597 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 598 {
 599         struct s3c24xx_uart_dma *dma = ourport->dma;
 600
 601         dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
 602                                 dma->rx_size, DMA_FROM_DEVICE);
 603
 604         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 605                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 606                                 DMA_PREP_INTERRUPT);
 607         if (!dma->rx_desc) {
 608                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 609                 return;
 610         }
 611
 612         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 613         dma->rx_desc->callback_param = ourport;
 614         dma->rx_bytes_requested = dma->rx_size;
 615
 616         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 617         dma_async_issue_pending(dma->rx_chan);
 618 }
 619
 620 /* ? - where has parity gone?? */
 621 #define S3C2410_UERSTAT_PARITY (0x1000)
 622
 623 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 624 {
 625         struct uart_port *port = &ourport->port;
 626         unsigned int ucon;
 627
 628         /* set Rx mode to DMA mode */
 629         ucon = rd_regl(port, S3C2410_UCON);
 630         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 631                         S3C64XX_UCON_TIMEOUT_MASK |
 632                         S3C64XX_UCON_EMPTYINT_EN |
 633                         S3C64XX_UCON_DMASUS_EN |
 634                         S3C64XX_UCON_TIMEOUT_EN |
 635                         S3C64XX_UCON_RXMODE_MASK);
 636         ucon |= S3C64XX_UCON_RXBURST_1 |
 637                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 638                         S3C64XX_UCON_EMPTYINT_EN |
 639                         S3C64XX_UCON_TIMEOUT_EN |
 640                         S3C64XX_UCON_RXMODE_DMA;
 641         wr_regl(port, S3C2410_UCON, ucon);
 642
 643         ourport->rx_mode = S3C24XX_RX_DMA;
 644 }
 645
 646 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 647 {
 648         struct uart_port *port = &ourport->port;
 649         unsigned int ucon;
 650
 651         /* set Rx mode to DMA mode */
 652         ucon = rd_regl(port, S3C2410_UCON);
 653         ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 654                         S3C64XX_UCON_EMPTYINT_EN |
 655                         S3C64XX_UCON_DMASUS_EN |
 656                         S3C64XX_UCON_TIMEOUT_EN |
 657                         S3C64XX_UCON_RXMODE_MASK);
 658         ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 659                         S3C64XX_UCON_TIMEOUT_EN |
 660                         S3C64XX_UCON_RXMODE_CPU;
 661         wr_regl(port, S3C2410_UCON, ucon);
 662
 663         ourport->rx_mode = S3C24XX_RX_PIO;
 664 }
 665
 666 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 667
 668 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 669 {
 670         unsigned int utrstat, received;
 671         struct s3c24xx_uart_port *ourport = dev_id;
 672         struct uart_port *port = &ourport->port;
 673         struct s3c24xx_uart_dma *dma = ourport->dma;
 674         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 675         struct tty_port *t = &port->state->port;
 676         unsigned long flags;
 677         struct dma_tx_state state;
 678
 679         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 680         rd_regl(port, S3C2410_UFSTAT);
 681
 682         spin_lock_irqsave(&port->lock, flags);
 683
 684         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 685                 s3c64xx_start_rx_dma(ourport);
 686                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 687                         enable_rx_dma(ourport);
 688                 goto finish;
 689         }
 690
 691         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 692                 dmaengine_pause(dma->rx_chan);
 693                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 694                 dmaengine_terminate_all(dma->rx_chan);
 695                 received = dma->rx_bytes_requested - state.residue;
 696                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 697
 698                 enable_rx_pio(ourport);
 699         }
 700
 701         s3c24xx_serial_rx_drain_fifo(ourport);
 702
 703         if (tty) {
 704                 tty_flip_buffer_push(t);
 705                 tty_kref_put(tty);
 706         }
 707
 708         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 709
 710 finish:
 711         spin_unlock_irqrestore(&port->lock, flags);
 712
 713         return IRQ_HANDLED;
 714 }
 715
 716 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 717 {
 718         struct uart_port *port = &ourport->port;
 719         unsigned int ufcon, ch, flag, ufstat, uerstat;
 720         unsigned int fifocnt = 0;
 721         int max_count = port->fifosize;
 722
 723         while (max_count-- > 0) {
 724                 /*
 725                  * Receive all characters known to be in FIFO
 726                  * before reading FIFO level again
 727                  */
 728                 if (fifocnt == 0) {
 729                         ufstat = rd_regl(port, S3C2410_UFSTAT);
 730                         fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 731                         if (fifocnt == 0)
 732                                 break;
 733                 }
 734                 fifocnt--;
 735
 736                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 737                 ch = rd_reg(port, S3C2410_URXH);
 738
 739                 if (port->flags & UPF_CONS_FLOW) {
 740                         int txe = s3c24xx_serial_txempty_nofifo(port);
 741
 742                         if (ourport->rx_enabled) {
 743                                 if (!txe) {
 744                                         ourport->rx_enabled = 0;
 745                                         continue;
 746                                 }
 747                         } else {
 748                                 if (txe) {
 749                                         ufcon = rd_regl(port, S3C2410_UFCON);
 750                                         ufcon |= S3C2410_UFCON_RESETRX;
 751                                         wr_regl(port, S3C2410_UFCON, ufcon);
 752                                         ourport->rx_enabled = 1;
 753                                         return;
 754                                 }
 755                                 continue;
 756                         }
 757                 }
 758
 759                 /* insert the character into the buffer */
 760
 761                 flag = TTY_NORMAL;
 762                 port->icount.rx++;
 763
 764                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 765                         dev_dbg(port->dev,
 766                                 "rxerr: port ch=0x%02x, rxs=0x%08x\n",
 767                                 ch, uerstat);
 768
 769                         /* check for break */
 770                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 771                                 dev_dbg(port->dev, "break!\n");
 772                                 port->icount.brk++;
 773                                 if (uart_handle_break(port))
 774                                         continue; /* Ignore character */
 775                         }
 776
 777                         if (uerstat & S3C2410_UERSTAT_FRAME)
 778                                 port->icount.frame++;
 779                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 780                                 port->icount.overrun++;
 781
 782                         uerstat &= port->read_status_mask;
 783
 784                         if (uerstat & S3C2410_UERSTAT_BREAK)
 785                                 flag = TTY_BREAK;
 786                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 787                                 flag = TTY_PARITY;
 788                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 789                                             S3C2410_UERSTAT_OVERRUN))
 790                                 flag = TTY_FRAME;
 791                 }
 792
 793                 if (uart_handle_sysrq_char(port, ch))
 794                         continue; /* Ignore character */
 795
 796                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 797                                  ch, flag);
 798         }
 799
 800         tty_flip_buffer_push(&port->state->port);
 801 }
 802
 803 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 804 {
 805         struct s3c24xx_uart_port *ourport = dev_id;
 806         struct uart_port *port = &ourport->port;
 807         unsigned long flags;
 808
 809         spin_lock_irqsave(&port->lock, flags);
 810         s3c24xx_serial_rx_drain_fifo(ourport);
 811         spin_unlock_irqrestore(&port->lock, flags);
 812
 813         return IRQ_HANDLED;
 814 }
 815
 816 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
 817 {
 818         struct s3c24xx_uart_port *ourport = dev_id;
 819
 820         if (ourport->dma && ourport->dma->rx_chan)
 821                 return s3c24xx_serial_rx_chars_dma(dev_id);
 822         return s3c24xx_serial_rx_chars_pio(dev_id);
 823 }
 824
 825 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
 826 {
 827         struct s3c24xx_uart_port *ourport = id;
 828         struct uart_port *port = &ourport->port;
 829         struct circ_buf *xmit = &port->state->xmit;
 830         unsigned long flags;
 831         int count, dma_count = 0;
 832
 833         spin_lock_irqsave(&port->lock, flags);
 834
 835         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 836
 837         if (ourport->dma && ourport->dma->tx_chan &&
 838             count >= ourport->min_dma_size) {
 839                 int align = dma_get_cache_alignment() -
 840                         (xmit->tail & (dma_get_cache_alignment() - 1));
 841                 if (count - align >= ourport->min_dma_size) {
 842                         dma_count = count - align;
 843                         count = align;
 844                 }
 845         }
 846
 847         if (port->x_char) {
 848                 wr_reg(port, S3C2410_UTXH, port->x_char);
 849                 port->icount.tx++;
 850                 port->x_char = 0;
 851                 goto out;
 852         }
 853
 854         /* if there isn't anything more to transmit, or the uart is now
 855          * stopped, disable the uart and exit
 856          */
 857
 858         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 859                 s3c24xx_serial_stop_tx(port);
 860                 goto out;
 861         }
 862
 863         /* try and drain the buffer... */
 864
 865         if (count > port->fifosize) {
 866                 count = port->fifosize;
 867                 dma_count = 0;
 868         }
 869
 870         while (!uart_circ_empty(xmit) && count > 0) {
 871                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 872                         break;
 873
 874                 wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 875                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 876                 port->icount.tx++;
 877                 count--;
 878         }
 879
 880         if (!count && dma_count) {
 881                 s3c24xx_serial_start_tx_dma(ourport, dma_count);
 882                 goto out;
 883         }
 884
 885         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 886                 uart_write_wakeup(port);
 887
 888         if (uart_circ_empty(xmit))
 889                 s3c24xx_serial_stop_tx(port);
 890
 891 out:
 892         spin_unlock_irqrestore(&port->lock, flags);
 893         return IRQ_HANDLED;
 894 }
 895
 896 /* interrupt handler for s3c64xx and later SoC's.*/
 897 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 898 {
 899         struct s3c24xx_uart_port *ourport = id;
 900         struct uart_port *port = &ourport->port;
 901         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 902         irqreturn_t ret = IRQ_HANDLED;
 903
 904         if (pend & S3C64XX_UINTM_RXD_MSK) {
 905                 ret = s3c24xx_serial_rx_chars(irq, id);
 906                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 907         }
 908         if (pend & S3C64XX_UINTM_TXD_MSK) {
 909                 ret = s3c24xx_serial_tx_chars(irq, id);
 910                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 911         }
 912         return ret;
 913 }
 914
 915 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 916 {
 917         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 918         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 919         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 920
 921         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 922                 if ((ufstat & info->tx_fifomask) != 0 ||
 923                     (ufstat & info->tx_fifofull))
 924                         return 0;
 925                 return TIOCSER_TEMT;
 926         }
 927
 928         return s3c24xx_serial_txempty_nofifo(port) ? TIOCSER_TEMT : 0;
 929 }
 930
 931 /* no modem control lines */
 932 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
 933 {
 934         unsigned int umstat = rd_reg(port, S3C2410_UMSTAT);
 935
 936         if (umstat & S3C2410_UMSTAT_CTS)
 937                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 938         else
 939                 return TIOCM_CAR | TIOCM_DSR;
 940 }
 941
 942 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
 943 {
 944         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
 945
 946         if (mctrl & TIOCM_RTS)
 947                 umcon |= S3C2410_UMCOM_RTS_LOW;
 948         else
 949                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
 950
 951         wr_regl(port, S3C2410_UMCON, umcon);
 952 }
 953
 954 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
 955 {
 956         unsigned long flags;
 957         unsigned int ucon;
 958
 959         spin_lock_irqsave(&port->lock, flags);
 960
 961         ucon = rd_regl(port, S3C2410_UCON);
 962
 963         if (break_state)
 964                 ucon |= S3C2410_UCON_SBREAK;
 965         else
 966                 ucon &= ~S3C2410_UCON_SBREAK;
 967
 968         wr_regl(port, S3C2410_UCON, ucon);
 969
 970         spin_unlock_irqrestore(&port->lock, flags);
 971 }
 972
 973 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
 974 {
 975         struct s3c24xx_uart_dma *dma = p->dma;
 976         struct dma_slave_caps dma_caps;
 977         const char *reason = NULL;
 978         int ret;
 979
 980         /* Default slave configuration parameters */
 981         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
 982         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 983         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
 984         dma->rx_conf.src_maxburst       = 1;
 985
 986         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
 987         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 988         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
 989         dma->tx_conf.dst_maxburst       = 1;
 990
 991         dma->rx_chan = dma_request_chan(p->port.dev, "rx");
 992
 993         if (IS_ERR(dma->rx_chan)) {
 994                 reason = "DMA RX channel request failed";
 995                 ret = PTR_ERR(dma->rx_chan);
 996                 goto err_warn;
 997         }
 998
 999         ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
1000         if (ret < 0 ||
1001             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1002                 reason = "insufficient DMA RX engine capabilities";
1003                 ret = -EOPNOTSUPP;
1004                 goto err_release_rx;
1005         }
1006
1007         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
1008
1009         dma->tx_chan = dma_request_chan(p->port.dev, "tx");
1010         if (IS_ERR(dma->tx_chan)) {
1011                 reason = "DMA TX channel request failed";
1012                 ret = PTR_ERR(dma->tx_chan);
1013                 goto err_release_rx;
1014         }
1015
1016         ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
1017         if (ret < 0 ||
1018             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1019                 reason = "insufficient DMA TX engine capabilities";
1020                 ret = -EOPNOTSUPP;
1021                 goto err_release_tx;
1022         }
1023
1024         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
1025
1026         /* RX buffer */
1027         dma->rx_size = PAGE_SIZE;
1028
1029         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
1030         if (!dma->rx_buf) {
1031                 ret = -ENOMEM;
1032                 goto err_release_tx;
1033         }
1034
1035         dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
1036                                 dma->rx_size, DMA_FROM_DEVICE);
1037         if (dma_mapping_error(p->port.dev, dma->rx_addr)) {
1038                 reason = "DMA mapping error for RX buffer";
1039                 ret = -EIO;
1040                 goto err_free_rx;
1041         }
1042
1043         /* TX buffer */
1044         dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
1045                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
1046         if (dma_mapping_error(p->port.dev, dma->tx_addr)) {
1047                 reason = "DMA mapping error for TX buffer";
1048                 ret = -EIO;
1049                 goto err_unmap_rx;
1050         }
1051
1052         return 0;
1053
1054 err_unmap_rx:
1055         dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size,
1056                          DMA_FROM_DEVICE);
1057 err_free_rx:
1058         kfree(dma->rx_buf);
1059 err_release_tx:
1060         dma_release_channel(dma->tx_chan);
1061 err_release_rx:
1062         dma_release_channel(dma->rx_chan);
1063 err_warn:
1064         if (reason)
1065                 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
1066         return ret;
1067 }
1068
1069 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
1070 {
1071         struct s3c24xx_uart_dma *dma = p->dma;
1072
1073         if (dma->rx_chan) {
1074                 dmaengine_terminate_all(dma->rx_chan);
1075                 dma_unmap_single(p->port.dev, dma->rx_addr,
1076                                 dma->rx_size, DMA_FROM_DEVICE);
1077                 kfree(dma->rx_buf);
1078                 dma_release_channel(dma->rx_chan);
1079                 dma->rx_chan = NULL;
1080         }
1081
1082         if (dma->tx_chan) {
1083                 dmaengine_terminate_all(dma->tx_chan);
1084                 dma_unmap_single(p->port.dev, dma->tx_addr,
1085                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
1086                 dma_release_channel(dma->tx_chan);
1087                 dma->tx_chan = NULL;
1088         }
1089 }
1090
1091 static void s3c24xx_serial_shutdown(struct uart_port *port)
1092 {
1093         struct s3c24xx_uart_port *ourport = to_ourport(port);
1094
1095         if (ourport->tx_claimed) {
1096                 if (!s3c24xx_serial_has_interrupt_mask(port))
1097                         free_irq(ourport->tx_irq, ourport);
1098                 ourport->tx_enabled = 0;
1099                 ourport->tx_claimed = 0;
1100                 ourport->tx_mode = 0;
1101         }
1102
1103         if (ourport->rx_claimed) {
1104                 if (!s3c24xx_serial_has_interrupt_mask(port))
1105                         free_irq(ourport->rx_irq, ourport);
1106                 ourport->rx_claimed = 0;
1107                 ourport->rx_enabled = 0;
1108         }
1109
1110         /* Clear pending interrupts and mask all interrupts */
1111         if (s3c24xx_serial_has_interrupt_mask(port)) {
1112                 free_irq(port->irq, ourport);
1113
1114                 wr_regl(port, S3C64XX_UINTP, 0xf);
1115                 wr_regl(port, S3C64XX_UINTM, 0xf);
1116         }
1117
1118         if (ourport->dma)
1119                 s3c24xx_serial_release_dma(ourport);
1120
1121         ourport->tx_in_progress = 0;
1122 }
1123
1124 static int s3c24xx_serial_startup(struct uart_port *port)
1125 {
1126         struct s3c24xx_uart_port *ourport = to_ourport(port);
1127         int ret;
1128
1129         ourport->rx_enabled = 1;
1130
1131         ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
1132                           s3c24xx_serial_portname(port), ourport);
1133
1134         if (ret != 0) {
1135                 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1136                 return ret;
1137         }
1138
1139         ourport->rx_claimed = 1;
1140
1141         dev_dbg(port->dev, "requesting tx irq...\n");
1142
1143         ourport->tx_enabled = 1;
1144
1145         ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1146                           s3c24xx_serial_portname(port), ourport);
1147
1148         if (ret) {
1149                 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1150                 goto err;
1151         }
1152
1153         ourport->tx_claimed = 1;
1154
1155         /* the port reset code should have done the correct
1156          * register setup for the port controls
1157          */
1158
1159         return ret;
1160
1161 err:
1162         s3c24xx_serial_shutdown(port);
1163         return ret;
1164 }
1165
1166 static int s3c64xx_serial_startup(struct uart_port *port)
1167 {
1168         struct s3c24xx_uart_port *ourport = to_ourport(port);
1169         unsigned long flags;
1170         unsigned int ufcon;
1171         int ret;
1172
1173         wr_regl(port, S3C64XX_UINTM, 0xf);
1174         if (ourport->dma) {
1175                 ret = s3c24xx_serial_request_dma(ourport);
1176                 if (ret < 0) {
1177                         devm_kfree(port->dev, ourport->dma);
1178                         ourport->dma = NULL;
1179                 }
1180         }
1181
1182         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1183                           s3c24xx_serial_portname(port), ourport);
1184         if (ret) {
1185                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1186                 return ret;
1187         }
1188
1189         /* For compatibility with s3c24xx Soc's */
1190         ourport->rx_enabled = 1;
1191         ourport->rx_claimed = 1;
1192         ourport->tx_enabled = 0;
1193         ourport->tx_claimed = 1;
1194
1195         spin_lock_irqsave(&port->lock, flags);
1196
1197         ufcon = rd_regl(port, S3C2410_UFCON);
1198         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1199         if (!uart_console(port))
1200                 ufcon |= S3C2410_UFCON_RESETTX;
1201         wr_regl(port, S3C2410_UFCON, ufcon);
1202
1203         enable_rx_pio(ourport);
1204
1205         spin_unlock_irqrestore(&port->lock, flags);
1206
1207         /* Enable Rx Interrupt */
1208         s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1209
1210         return ret;
1211 }
1212
1213 /* power power management control */
1214
1215 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1216                               unsigned int old)
1217 {
1218         struct s3c24xx_uart_port *ourport = to_ourport(port);
1219         int timeout = 10000;
1220
1221         ourport->pm_level = level;
1222
1223         switch (level) {
1224         case 3:
1225                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1226                         udelay(100);
1227
1228                 if (!IS_ERR(ourport->baudclk))
1229                         clk_disable_unprepare(ourport->baudclk);
1230
1231                 clk_disable_unprepare(ourport->clk);
1232                 break;
1233
1234         case 0:
1235                 clk_prepare_enable(ourport->clk);
1236
1237                 if (!IS_ERR(ourport->baudclk))
1238                         clk_prepare_enable(ourport->baudclk);
1239
1240                 break;
1241         default:
1242                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1243         }
1244 }
1245
1246 /* baud rate calculation
1247  *
1248  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1249  * of different sources, including the peripheral clock ("pclk") and an
1250  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1251  * with a programmable extra divisor.
1252  *
1253  * The following code goes through the clock sources, and calculates the
1254  * baud clocks (and the resultant actual baud rates) and then tries to
1255  * pick the closest one and select that.
1256  *
1257  */
1258
1259 #define MAX_CLK_NAME_LENGTH 15
1260
1261 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1262 {
1263         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1264         unsigned int ucon;
1265
1266         if (info->num_clks == 1)
1267                 return 0;
1268
1269         ucon = rd_regl(port, S3C2410_UCON);
1270         ucon &= info->clksel_mask;
1271         return ucon >> info->clksel_shift;
1272 }
1273
1274 static void s3c24xx_serial_setsource(struct uart_port *port,
1275                         unsigned int clk_sel)
1276 {
1277         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1278         unsigned int ucon;
1279
1280         if (info->num_clks == 1)
1281                 return;
1282
1283         ucon = rd_regl(port, S3C2410_UCON);
1284         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1285                 return;
1286
1287         ucon &= ~info->clksel_mask;
1288         ucon |= clk_sel << info->clksel_shift;
1289         wr_regl(port, S3C2410_UCON, ucon);
1290 }
1291
1292 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1293                         unsigned int req_baud, struct clk **best_clk,
1294                         unsigned int *clk_num)
1295 {
1296         struct s3c24xx_uart_info *info = ourport->info;
1297         struct clk *clk;
1298         unsigned long rate;
1299         unsigned int cnt, baud, quot, best_quot = 0;
1300         char clkname[MAX_CLK_NAME_LENGTH];
1301         int calc_deviation, deviation = (1 << 30) - 1;
1302
1303         for (cnt = 0; cnt < info->num_clks; cnt++) {
1304                 /* Keep selected clock if provided */
1305                 if (ourport->cfg->clk_sel &&
1306                         !(ourport->cfg->clk_sel & (1 << cnt)))
1307                         continue;
1308
1309                 sprintf(clkname, "clk_uart_baud%d", cnt);
1310                 clk = clk_get(ourport->port.dev, clkname);
1311                 if (IS_ERR(clk))
1312                         continue;
1313
1314                 rate = clk_get_rate(clk);
1315                 if (!rate) {
1316                         dev_err(ourport->port.dev,
1317                                 "Failed to get clock rate for %s.\n", clkname);
1318                         clk_put(clk);
1319                         continue;
1320                 }
1321
1322                 if (ourport->info->has_divslot) {
1323                         unsigned long div = rate / req_baud;
1324
1325                         /* The UDIVSLOT register on the newer UARTs allows us to
1326                          * get a divisor adjustment of 1/16th on the baud clock.
1327                          *
1328                          * We don't keep the UDIVSLOT value (the 16ths we
1329                          * calculated by not multiplying the baud by 16) as it
1330                          * is easy enough to recalculate.
1331                          */
1332
1333                         quot = div / 16;
1334                         baud = rate / div;
1335                 } else {
1336                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1337                         baud = rate / (quot * 16);
1338                 }
1339                 quot--;
1340
1341                 calc_deviation = req_baud - baud;
1342                 if (calc_deviation < 0)
1343                         calc_deviation = -calc_deviation;
1344
1345                 if (calc_deviation < deviation) {
1346                         /*
1347                          * If we find a better clk, release the previous one, if
1348                          * any.
1349                          */
1350                         if (!IS_ERR(*best_clk))
1351                                 clk_put(*best_clk);
1352                         *best_clk = clk;
1353                         best_quot = quot;
1354                         *clk_num = cnt;
1355                         deviation = calc_deviation;
1356                 } else {
1357                         clk_put(clk);
1358                 }
1359         }
1360
1361         return best_quot;
1362 }
1363
1364 /* udivslot_table[]
1365  *
1366  * This table takes the fractional value of the baud divisor and gives
1367  * the recommended setting for the UDIVSLOT register.
1368  */
1369 static u16 udivslot_table[16] = {
1370         [0] = 0x0000,
1371         [1] = 0x0080,
1372         [2] = 0x0808,
1373         [3] = 0x0888,
1374         [4] = 0x2222,
1375         [5] = 0x4924,
1376         [6] = 0x4A52,
1377         [7] = 0x54AA,
1378         [8] = 0x5555,
1379         [9] = 0xD555,
1380         [10] = 0xD5D5,
1381         [11] = 0xDDD5,
1382         [12] = 0xDDDD,
1383         [13] = 0xDFDD,
1384         [14] = 0xDFDF,
1385         [15] = 0xFFDF,
1386 };
1387
1388 static void s3c24xx_serial_set_termios(struct uart_port *port,
1389                                        struct ktermios *termios,
1390                                        struct ktermios *old)
1391 {
1392         struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1393         struct s3c24xx_uart_port *ourport = to_ourport(port);
1394         struct clk *clk = ERR_PTR(-EINVAL);
1395         unsigned long flags;
1396         unsigned int baud, quot, clk_sel = 0;
1397         unsigned int ulcon;
1398         unsigned int umcon;
1399         unsigned int udivslot = 0;
1400
1401         /*
1402          * We don't support modem control lines.
1403          */
1404         termios->c_cflag &= ~(HUPCL | CMSPAR);
1405         termios->c_cflag |= CLOCAL;
1406
1407         /*
1408          * Ask the core to calculate the divisor for us.
1409          */
1410
1411         baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
1412         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1413         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1414                 quot = port->custom_divisor;
1415         if (IS_ERR(clk))
1416                 return;
1417
1418         /* check to see if we need  to change clock source */
1419
1420         if (ourport->baudclk != clk) {
1421                 clk_prepare_enable(clk);
1422
1423                 s3c24xx_serial_setsource(port, clk_sel);
1424
1425                 if (!IS_ERR(ourport->baudclk)) {
1426                         clk_disable_unprepare(ourport->baudclk);
1427                         ourport->baudclk = ERR_PTR(-EINVAL);
1428                 }
1429
1430                 ourport->baudclk = clk;
1431                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1432         }
1433
1434         if (ourport->info->has_divslot) {
1435                 unsigned int div = ourport->baudclk_rate / baud;
1436
1437                 if (cfg->has_fracval) {
1438                         udivslot = (div & 15);
1439                         dev_dbg(port->dev, "fracval = %04x\n", udivslot);
1440                 } else {
1441                         udivslot = udivslot_table[div & 15];
1442                         dev_dbg(port->dev, "udivslot = %04x (div %d)\n",
1443                                 udivslot, div & 15);
1444                 }
1445         }
1446
1447         switch (termios->c_cflag & CSIZE) {
1448         case CS5:
1449                 dev_dbg(port->dev, "config: 5bits/char\n");
1450                 ulcon = S3C2410_LCON_CS5;
1451                 break;
1452         case CS6:
1453                 dev_dbg(port->dev, "config: 6bits/char\n");
1454                 ulcon = S3C2410_LCON_CS6;
1455                 break;
1456         case CS7:
1457                 dev_dbg(port->dev, "config: 7bits/char\n");
1458                 ulcon = S3C2410_LCON_CS7;
1459                 break;
1460         case CS8:
1461         default:
1462                 dev_dbg(port->dev, "config: 8bits/char\n");
1463                 ulcon = S3C2410_LCON_CS8;
1464                 break;
1465         }
1466
1467         /* preserve original lcon IR settings */
1468         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1469
1470         if (termios->c_cflag & CSTOPB)
1471                 ulcon |= S3C2410_LCON_STOPB;
1472
1473         if (termios->c_cflag & PARENB) {
1474                 if (termios->c_cflag & PARODD)
1475                         ulcon |= S3C2410_LCON_PODD;
1476                 else
1477                         ulcon |= S3C2410_LCON_PEVEN;
1478         } else {
1479                 ulcon |= S3C2410_LCON_PNONE;
1480         }
1481
1482         spin_lock_irqsave(&port->lock, flags);
1483
1484         dev_dbg(port->dev,
1485                 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1486                 ulcon, quot, udivslot);
1487
1488         wr_regl(port, S3C2410_ULCON, ulcon);
1489         wr_regl(port, S3C2410_UBRDIV, quot);
1490
1491         port->status &= ~UPSTAT_AUTOCTS;
1492
1493         umcon = rd_regl(port, S3C2410_UMCON);
1494         if (termios->c_cflag & CRTSCTS) {
1495                 umcon |= S3C2410_UMCOM_AFC;
1496                 /* Disable RTS when RX FIFO contains 63 bytes */
1497                 umcon &= ~S3C2412_UMCON_AFC_8;
1498                 port->status = UPSTAT_AUTOCTS;
1499         } else {
1500                 umcon &= ~S3C2410_UMCOM_AFC;
1501         }
1502         wr_regl(port, S3C2410_UMCON, umcon);
1503
1504         if (ourport->info->has_divslot)
1505                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1506
1507         dev_dbg(port->dev,
1508                 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1509                 rd_regl(port, S3C2410_ULCON),
1510                 rd_regl(port, S3C2410_UCON),
1511                 rd_regl(port, S3C2410_UFCON));
1512
1513         /*
1514          * Update the per-port timeout.
1515          */
1516         uart_update_timeout(port, termios->c_cflag, baud);
1517
1518         /*
1519          * Which character status flags are we interested in?
1520          */
1521         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1522         if (termios->c_iflag & INPCK)
1523                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1524                         S3C2410_UERSTAT_PARITY;
1525         /*
1526          * Which character status flags should we ignore?
1527          */
1528         port->ignore_status_mask = 0;
1529         if (termios->c_iflag & IGNPAR)
1530                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1531         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1532                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1533
1534         /*
1535          * Ignore all characters if CREAD is not set.
1536          */
1537         if ((termios->c_cflag & CREAD) == 0)
1538                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1539
1540         spin_unlock_irqrestore(&port->lock, flags);
1541 }
1542
1543 static const char *s3c24xx_serial_type(struct uart_port *port)
1544 {
1545         switch (port->type) {
1546         case PORT_S3C2410:
1547                 return "S3C2410";
1548         case PORT_S3C2440:
1549                 return "S3C2440";
1550         case PORT_S3C2412:
1551                 return "S3C2412";
1552         case PORT_S3C6400:
1553                 return "S3C6400/10";
1554         default:
1555                 return NULL;
1556         }
1557 }
1558
1559 #define MAP_SIZE (0x100)
1560
1561 static void s3c24xx_serial_release_port(struct uart_port *port)
1562 {
1563         release_mem_region(port->mapbase, MAP_SIZE);
1564 }
1565
1566 static int s3c24xx_serial_request_port(struct uart_port *port)
1567 {
1568         const char *name = s3c24xx_serial_portname(port);
1569
1570         return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1571 }
1572
1573 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1574 {
1575         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1576
1577         if (flags & UART_CONFIG_TYPE &&
1578             s3c24xx_serial_request_port(port) == 0)
1579                 port->type = info->type;
1580 }
1581
1582 /*
1583  * verify the new serial_struct (for TIOCSSERIAL).
1584  */
1585 static int
1586 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1587 {
1588         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1589
1590         if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1591                 return -EINVAL;
1592
1593         return 0;
1594 }
1595
1596 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1597
1598 static struct console s3c24xx_serial_console;
1599
1600 static int __init s3c24xx_serial_console_init(void)
1601 {
1602         register_console(&s3c24xx_serial_console);
1603         return 0;
1604 }
1605 console_initcall(s3c24xx_serial_console_init);
1606
1607 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1608 #else
1609 #define S3C24XX_SERIAL_CONSOLE NULL
1610 #endif
1611
1612 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1613 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1614 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1615                          unsigned char c);
1616 #endif
1617
1618 static struct uart_ops s3c24xx_serial_ops = {
1619         .pm             = s3c24xx_serial_pm,
1620         .tx_empty       = s3c24xx_serial_tx_empty,
1621         .get_mctrl      = s3c24xx_serial_get_mctrl,
1622         .set_mctrl      = s3c24xx_serial_set_mctrl,
1623         .stop_tx        = s3c24xx_serial_stop_tx,
1624         .start_tx       = s3c24xx_serial_start_tx,
1625         .stop_rx        = s3c24xx_serial_stop_rx,
1626         .break_ctl      = s3c24xx_serial_break_ctl,
1627         .startup        = s3c24xx_serial_startup,
1628         .shutdown       = s3c24xx_serial_shutdown,
1629         .set_termios    = s3c24xx_serial_set_termios,
1630         .type           = s3c24xx_serial_type,
1631         .release_port   = s3c24xx_serial_release_port,
1632         .request_port   = s3c24xx_serial_request_port,
1633         .config_port    = s3c24xx_serial_config_port,
1634         .verify_port    = s3c24xx_serial_verify_port,
1635 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1636         .poll_get_char = s3c24xx_serial_get_poll_char,
1637         .poll_put_char = s3c24xx_serial_put_poll_char,
1638 #endif
1639 };
1640
1641 static struct uart_driver s3c24xx_uart_drv = {
1642         .owner          = THIS_MODULE,
1643         .driver_name    = "s3c2410_serial",
1644         .nr             = CONFIG_SERIAL_SAMSUNG_UARTS,
1645         .cons           = S3C24XX_SERIAL_CONSOLE,
1646         .dev_name       = S3C24XX_SERIAL_NAME,
1647         .major          = S3C24XX_SERIAL_MAJOR,
1648         .minor          = S3C24XX_SERIAL_MINOR,
1649 };
1650
1651 #define __PORT_LOCK_UNLOCKED(i) \
1652         __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1653 static struct s3c24xx_uart_port
1654 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1655         [0] = {
1656                 .port = {
1657                         .lock           = __PORT_LOCK_UNLOCKED(0),
1658                         .iotype         = UPIO_MEM,
1659                         .uartclk        = 0,
1660                         .fifosize       = 16,
1661                         .ops            = &s3c24xx_serial_ops,
1662                         .flags          = UPF_BOOT_AUTOCONF,
1663                         .line           = 0,
1664                 }
1665         },
1666         [1] = {
1667                 .port = {
1668                         .lock           = __PORT_LOCK_UNLOCKED(1),
1669                         .iotype         = UPIO_MEM,
1670                         .uartclk        = 0,
1671                         .fifosize       = 16,
1672                         .ops            = &s3c24xx_serial_ops,
1673                         .flags          = UPF_BOOT_AUTOCONF,
1674                         .line           = 1,
1675                 }
1676         },
1677 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1678         [2] = {
1679                 .port = {
1680                         .lock           = __PORT_LOCK_UNLOCKED(2),
1681                         .iotype         = UPIO_MEM,
1682                         .uartclk        = 0,
1683                         .fifosize       = 16,
1684                         .ops            = &s3c24xx_serial_ops,
1685                         .flags          = UPF_BOOT_AUTOCONF,
1686                         .line           = 2,
1687                 }
1688         },
1689 #endif
1690 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1691         [3] = {
1692                 .port = {
1693                         .lock           = __PORT_LOCK_UNLOCKED(3),
1694                         .iotype         = UPIO_MEM,
1695                         .uartclk        = 0,
1696                         .fifosize       = 16,
1697                         .ops            = &s3c24xx_serial_ops,
1698                         .flags          = UPF_BOOT_AUTOCONF,
1699                         .line           = 3,
1700                 }
1701         }
1702 #endif
1703 };
1704 #undef __PORT_LOCK_UNLOCKED
1705
1706 /* s3c24xx_serial_resetport
1707  *
1708  * reset the fifos and other the settings.
1709  */
1710
1711 static void s3c24xx_serial_resetport(struct uart_port *port,
1712                                    struct s3c2410_uartcfg *cfg)
1713 {
1714         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1715         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1716         unsigned int ucon_mask;
1717
1718         ucon_mask = info->clksel_mask;
1719         if (info->type == PORT_S3C2440)
1720                 ucon_mask |= S3C2440_UCON0_DIVMASK;
1721
1722         ucon &= ucon_mask;
1723         wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
1724
1725         /* reset both fifos */
1726         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1727         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1728
1729         /* some delay is required after fifo reset */
1730         udelay(1);
1731 }
1732
1733 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1734
1735 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1736                                              unsigned long val, void *data)
1737 {
1738         struct s3c24xx_uart_port *port;
1739         struct uart_port *uport;
1740
1741         port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1742         uport = &port->port;
1743
1744         /* check to see if port is enabled */
1745
1746         if (port->pm_level != 0)
1747                 return 0;
1748
1749         /* try and work out if the baudrate is changing, we can detect
1750          * a change in rate, but we do not have support for detecting
1751          * a disturbance in the clock-rate over the change.
1752          */
1753
1754         if (IS_ERR(port->baudclk))
1755                 goto exit;
1756
1757         if (port->baudclk_rate == clk_get_rate(port->baudclk))
1758                 goto exit;
1759
1760         if (val == CPUFREQ_PRECHANGE) {
1761                 /* we should really shut the port down whilst the
1762                  * frequency change is in progress.
1763                  */
1764
1765         } else if (val == CPUFREQ_POSTCHANGE) {
1766                 struct ktermios *termios;
1767                 struct tty_struct *tty;
1768
1769                 if (uport->state == NULL)
1770                         goto exit;
1771
1772                 tty = uport->state->port.tty;
1773
1774                 if (tty == NULL)
1775                         goto exit;
1776
1777                 termios = &tty->termios;
1778
1779                 if (termios == NULL) {
1780                         dev_warn(uport->dev, "%s: no termios?\n", __func__);
1781                         goto exit;
1782                 }
1783
1784                 s3c24xx_serial_set_termios(uport, termios, NULL);
1785         }
1786
1787 exit:
1788         return 0;
1789 }
1790
1791 static inline int
1792 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1793 {
1794         port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1795
1796         return cpufreq_register_notifier(&port->freq_transition,
1797                                          CPUFREQ_TRANSITION_NOTIFIER);
1798 }
1799
1800 static inline void
1801 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1802 {
1803         cpufreq_unregister_notifier(&port->freq_transition,
1804                                     CPUFREQ_TRANSITION_NOTIFIER);
1805 }
1806
1807 #else
1808 static inline int
1809 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1810 {
1811         return 0;
1812 }
1813
1814 static inline void
1815 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1816 {
1817 }
1818 #endif
1819
1820 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
1821 {
1822         struct device *dev = ourport->port.dev;
1823         struct s3c24xx_uart_info *info = ourport->info;
1824         char clk_name[MAX_CLK_NAME_LENGTH];
1825         unsigned int clk_sel;
1826         struct clk *clk;
1827         int clk_num;
1828         int ret;
1829
1830         clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
1831         for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
1832                 if (!(clk_sel & (1 << clk_num)))
1833                         continue;
1834
1835                 sprintf(clk_name, "clk_uart_baud%d", clk_num);
1836                 clk = clk_get(dev, clk_name);
1837                 if (IS_ERR(clk))
1838                         continue;
1839
1840                 ret = clk_prepare_enable(clk);
1841                 if (ret) {
1842                         clk_put(clk);
1843                         continue;
1844                 }
1845
1846                 ourport->baudclk = clk;
1847                 ourport->baudclk_rate = clk_get_rate(clk);
1848                 s3c24xx_serial_setsource(&ourport->port, clk_num);
1849
1850                 return 0;
1851         }
1852
1853         return -EINVAL;
1854 }
1855
1856 /* s3c24xx_serial_init_port
1857  *
1858  * initialise a single serial port from the platform device given
1859  */
1860
1861 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1862                                     struct platform_device *platdev)
1863 {
1864         struct uart_port *port = &ourport->port;
1865         struct s3c2410_uartcfg *cfg = ourport->cfg;
1866         struct resource *res;
1867         int ret;
1868
1869         if (platdev == NULL)
1870                 return -ENODEV;
1871
1872         if (port->mapbase != 0)
1873                 return -EINVAL;
1874
1875         /* setup info for port */
1876         port->dev       = &platdev->dev;
1877
1878         /* Startup sequence is different for s3c64xx and higher SoC's */
1879         if (s3c24xx_serial_has_interrupt_mask(port))
1880                 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1881
1882         port->uartclk = 1;
1883
1884         if (cfg->uart_flags & UPF_CONS_FLOW) {
1885                 dev_dbg(port->dev, "enabling flow control\n");
1886                 port->flags |= UPF_CONS_FLOW;
1887         }
1888
1889         /* sort our the physical and virtual addresses for each UART */
1890
1891         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1892         if (res == NULL) {
1893                 dev_err(port->dev, "failed to find memory resource for uart\n");
1894                 return -EINVAL;
1895         }
1896
1897         dev_dbg(port->dev, "resource %pR)\n", res);
1898
1899         port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1900         if (!port->membase) {
1901                 dev_err(port->dev, "failed to remap controller address\n");
1902                 return -EBUSY;
1903         }
1904
1905         port->mapbase = res->start;
1906         ret = platform_get_irq(platdev, 0);
1907         if (ret < 0) {
1908                 port->irq = 0;
1909         } else {
1910                 port->irq = ret;
1911                 ourport->rx_irq = ret;
1912                 ourport->tx_irq = ret + 1;
1913         }
1914
1915         if (!s3c24xx_serial_has_interrupt_mask(port)) {
1916                 ret = platform_get_irq(platdev, 1);
1917                 if (ret > 0)
1918                         ourport->tx_irq = ret;
1919         }
1920         /*
1921          * DMA is currently supported only on DT platforms, if DMA properties
1922          * are specified.
1923          */
1924         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1925                                                      "dmas", NULL)) {
1926                 ourport->dma = devm_kzalloc(port->dev,
1927                                             sizeof(*ourport->dma),
1928                                             GFP_KERNEL);
1929                 if (!ourport->dma) {
1930                         ret = -ENOMEM;
1931                         goto err;
1932                 }
1933         }
1934
1935         ourport->clk    = clk_get(&platdev->dev, "uart");
1936         if (IS_ERR(ourport->clk)) {
1937                 pr_err("%s: Controller clock not found\n",
1938                                 dev_name(&platdev->dev));
1939                 ret = PTR_ERR(ourport->clk);
1940                 goto err;
1941         }
1942
1943         ret = clk_prepare_enable(ourport->clk);
1944         if (ret) {
1945                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1946                 clk_put(ourport->clk);
1947                 goto err;
1948         }
1949
1950         ret = s3c24xx_serial_enable_baudclk(ourport);
1951         if (ret)
1952                 pr_warn("uart: failed to enable baudclk\n");
1953
1954         /* Keep all interrupts masked and cleared */
1955         if (s3c24xx_serial_has_interrupt_mask(port)) {
1956                 wr_regl(port, S3C64XX_UINTM, 0xf);
1957                 wr_regl(port, S3C64XX_UINTP, 0xf);
1958                 wr_regl(port, S3C64XX_UINTSP, 0xf);
1959         }
1960
1961         dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1962                 &port->mapbase, port->membase, port->irq,
1963                 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1964
1965         /* reset the fifos (and setup the uart) */
1966         s3c24xx_serial_resetport(port, cfg);
1967
1968         return 0;
1969
1970 err:
1971         port->mapbase = 0;
1972         return ret;
1973 }
1974
1975 /* Device driver serial port probe */
1976
1977 #ifdef CONFIG_OF
1978 static const struct of_device_id s3c24xx_uart_dt_match[];
1979 #endif
1980
1981 static int probe_index;
1982
1983 static inline struct s3c24xx_serial_drv_data *
1984 s3c24xx_get_driver_data(struct platform_device *pdev)
1985 {
1986 #ifdef CONFIG_OF
1987         if (pdev->dev.of_node) {
1988                 const struct of_device_id *match;
1989
1990                 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1991                 return (struct s3c24xx_serial_drv_data *)match->data;
1992         }
1993 #endif
1994         return (struct s3c24xx_serial_drv_data *)
1995                         platform_get_device_id(pdev)->driver_data;
1996 }
1997
1998 static int s3c24xx_serial_probe(struct platform_device *pdev)
1999 {
2000         struct device_node *np = pdev->dev.of_node;
2001         struct s3c24xx_uart_port *ourport;
2002         int index = probe_index;
2003         int ret, prop = 0;
2004
2005         if (np) {
2006                 ret = of_alias_get_id(np, "serial");
2007                 if (ret >= 0)
2008                         index = ret;
2009         }
2010
2011         if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
2012                 dev_err(&pdev->dev, "serial%d out of range\n", index);
2013                 return -EINVAL;
2014         }
2015         ourport = &s3c24xx_serial_ports[index];
2016
2017         ourport->drv_data = s3c24xx_get_driver_data(pdev);
2018         if (!ourport->drv_data) {
2019                 dev_err(&pdev->dev, "could not find driver data\n");
2020                 return -ENODEV;
2021         }
2022
2023         ourport->baudclk = ERR_PTR(-EINVAL);
2024         ourport->info = ourport->drv_data->info;
2025         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
2026                         dev_get_platdata(&pdev->dev) :
2027                         ourport->drv_data->def_cfg;
2028
2029         if (np) {
2030                 of_property_read_u32(np,
2031                         "samsung,uart-fifosize", &ourport->port.fifosize);
2032
2033                 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
2034                         switch (prop) {
2035                         case 1:
2036                                 ourport->port.iotype = UPIO_MEM;
2037                                 break;
2038                         case 4:
2039                                 ourport->port.iotype = UPIO_MEM32;
2040                                 break;
2041                         default:
2042                                 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
2043                                                 prop);
2044                                 ret = -EINVAL;
2045                                 break;
2046                         }
2047                 }
2048         }
2049
2050         if (ourport->drv_data->fifosize[index])
2051                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
2052         else if (ourport->info->fifosize)
2053                 ourport->port.fifosize = ourport->info->fifosize;
2054         ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE);
2055
2056         /*
2057          * DMA transfers must be aligned at least to cache line size,
2058          * so find minimal transfer size suitable for DMA mode
2059          */
2060         ourport->min_dma_size = max_t(int, ourport->port.fifosize,
2061                                     dma_get_cache_alignment());
2062
2063         dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport);
2064
2065         ret = s3c24xx_serial_init_port(ourport, pdev);
2066         if (ret < 0)
2067                 return ret;
2068
2069         if (!s3c24xx_uart_drv.state) {
2070                 ret = uart_register_driver(&s3c24xx_uart_drv);
2071                 if (ret < 0) {
2072                         pr_err("Failed to register Samsung UART driver\n");
2073                         return ret;
2074                 }
2075         }
2076
2077         dev_dbg(&pdev->dev, "%s: adding port\n", __func__);
2078         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
2079         platform_set_drvdata(pdev, &ourport->port);
2080
2081         /*
2082          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
2083          * so that a potential re-enablement through the pm-callback overlaps
2084          * and keeps the clock enabled in this case.
2085          */
2086         clk_disable_unprepare(ourport->clk);
2087         if (!IS_ERR(ourport->baudclk))
2088                 clk_disable_unprepare(ourport->baudclk);
2089
2090         ret = s3c24xx_serial_cpufreq_register(ourport);
2091         if (ret < 0)
2092                 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
2093
2094         probe_index++;
2095
2096         return 0;
2097 }
2098
2099 static int s3c24xx_serial_remove(struct platform_device *dev)
2100 {
2101         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
2102
2103         if (port) {
2104                 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
2105                 uart_remove_one_port(&s3c24xx_uart_drv, port);
2106         }
2107
2108         uart_unregister_driver(&s3c24xx_uart_drv);
2109
2110         return 0;
2111 }
2112
2113 /* UART power management code */
2114 #ifdef CONFIG_PM_SLEEP
2115 static int s3c24xx_serial_suspend(struct device *dev)
2116 {
2117         struct uart_port *port = s3c24xx_dev_to_port(dev);
2118
2119         if (port)
2120                 uart_suspend_port(&s3c24xx_uart_drv, port);
2121
2122         return 0;
2123 }
2124
2125 static int s3c24xx_serial_resume(struct device *dev)
2126 {
2127         struct uart_port *port = s3c24xx_dev_to_port(dev);
2128         struct s3c24xx_uart_port *ourport = to_ourport(port);
2129
2130         if (port) {
2131                 clk_prepare_enable(ourport->clk);
2132                 if (!IS_ERR(ourport->baudclk))
2133                         clk_prepare_enable(ourport->baudclk);
2134                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
2135                 if (!IS_ERR(ourport->baudclk))
2136                         clk_disable_unprepare(ourport->baudclk);
2137                 clk_disable_unprepare(ourport->clk);
2138
2139                 uart_resume_port(&s3c24xx_uart_drv, port);
2140         }
2141
2142         return 0;
2143 }
2144
2145 static int s3c24xx_serial_resume_noirq(struct device *dev)
2146 {
2147         struct uart_port *port = s3c24xx_dev_to_port(dev);
2148         struct s3c24xx_uart_port *ourport = to_ourport(port);
2149
2150         if (port) {
2151                 /* restore IRQ mask */
2152                 if (s3c24xx_serial_has_interrupt_mask(port)) {
2153                         unsigned int uintm = 0xf;
2154
2155                         if (ourport->tx_enabled)
2156                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
2157                         if (ourport->rx_enabled)
2158                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
2159                         clk_prepare_enable(ourport->clk);
2160                         if (!IS_ERR(ourport->baudclk))
2161                                 clk_prepare_enable(ourport->baudclk);
2162                         wr_regl(port, S3C64XX_UINTM, uintm);
2163                         if (!IS_ERR(ourport->baudclk))
2164                                 clk_disable_unprepare(ourport->baudclk);
2165                         clk_disable_unprepare(ourport->clk);
2166                 }
2167         }
2168
2169         return 0;
2170 }
2171
2172 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2173         .suspend = s3c24xx_serial_suspend,
2174         .resume = s3c24xx_serial_resume,
2175         .resume_noirq = s3c24xx_serial_resume_noirq,
2176 };
2177 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
2178
2179 #else /* !CONFIG_PM_SLEEP */
2180
2181 #define SERIAL_SAMSUNG_PM_OPS   NULL
2182 #endif /* CONFIG_PM_SLEEP */
2183
2184 /* Console code */
2185
2186 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2187
2188 static struct uart_port *cons_uart;
2189
2190 static int
2191 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2192 {
2193         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2194         unsigned long ufstat, utrstat;
2195
2196         if (ufcon & S3C2410_UFCON_FIFOMODE) {
2197                 /* fifo mode - check amount of data in fifo registers... */
2198
2199                 ufstat = rd_regl(port, S3C2410_UFSTAT);
2200                 return (ufstat & info->tx_fifofull) ? 0 : 1;
2201         }
2202
2203         /* in non-fifo mode, we go and use the tx buffer empty */
2204
2205         utrstat = rd_regl(port, S3C2410_UTRSTAT);
2206         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2207 }
2208
2209 static bool
2210 s3c24xx_port_configured(unsigned int ucon)
2211 {
2212         /* consider the serial port configured if the tx/rx mode set */
2213         return (ucon & 0xf) != 0;
2214 }
2215
2216 #ifdef CONFIG_CONSOLE_POLL
2217 /*
2218  * Console polling routines for writing and reading from the uart while
2219  * in an interrupt or debug context.
2220  */
2221
2222 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2223 {
2224         struct s3c24xx_uart_port *ourport = to_ourport(port);
2225         unsigned int ufstat;
2226
2227         ufstat = rd_regl(port, S3C2410_UFSTAT);
2228         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2229                 return NO_POLL_CHAR;
2230
2231         return rd_reg(port, S3C2410_URXH);
2232 }
2233
2234 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2235                 unsigned char c)
2236 {
2237         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2238         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2239
2240         /* not possible to xmit on unconfigured port */
2241         if (!s3c24xx_port_configured(ucon))
2242                 return;
2243
2244         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2245                 cpu_relax();
2246         wr_reg(port, S3C2410_UTXH, c);
2247 }
2248
2249 #endif /* CONFIG_CONSOLE_POLL */
2250
2251 static void
2252 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2253 {
2254         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2255
2256         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2257                 cpu_relax();
2258         wr_reg(port, S3C2410_UTXH, ch);
2259 }
2260
2261 static void
2262 s3c24xx_serial_console_write(struct console *co, const char *s,
2263                              unsigned int count)
2264 {
2265         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2266
2267         /* not possible to xmit on unconfigured port */
2268         if (!s3c24xx_port_configured(ucon))
2269                 return;
2270
2271         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2272 }
2273
2274 static void __init
2275 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2276                            int *parity, int *bits)
2277 {
2278         struct clk *clk;
2279         unsigned int ulcon;
2280         unsigned int ucon;
2281         unsigned int ubrdiv;
2282         unsigned long rate;
2283         unsigned int clk_sel;
2284         char clk_name[MAX_CLK_NAME_LENGTH];
2285
2286         ulcon  = rd_regl(port, S3C2410_ULCON);
2287         ucon   = rd_regl(port, S3C2410_UCON);
2288         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2289
2290         if (s3c24xx_port_configured(ucon)) {
2291                 switch (ulcon & S3C2410_LCON_CSMASK) {
2292                 case S3C2410_LCON_CS5:
2293                         *bits = 5;
2294                         break;
2295                 case S3C2410_LCON_CS6:
2296                         *bits = 6;
2297                         break;
2298                 case S3C2410_LCON_CS7:
2299                         *bits = 7;
2300                         break;
2301                 case S3C2410_LCON_CS8:
2302                 default:
2303                         *bits = 8;
2304                         break;
2305                 }
2306
2307                 switch (ulcon & S3C2410_LCON_PMASK) {
2308                 case S3C2410_LCON_PEVEN:
2309                         *parity = 'e';
2310                         break;
2311
2312                 case S3C2410_LCON_PODD:
2313                         *parity = 'o';
2314                         break;
2315
2316                 case S3C2410_LCON_PNONE:
2317                 default:
2318                         *parity = 'n';
2319                 }
2320
2321                 /* now calculate the baud rate */
2322
2323                 clk_sel = s3c24xx_serial_getsource(port);
2324                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2325
2326                 clk = clk_get(port->dev, clk_name);
2327                 if (!IS_ERR(clk))
2328                         rate = clk_get_rate(clk);
2329                 else
2330                         rate = 1;
2331
2332                 *baud = rate / (16 * (ubrdiv + 1));
2333                 dev_dbg(port->dev, "calculated baud %d\n", *baud);
2334         }
2335 }
2336
2337 static int __init
2338 s3c24xx_serial_console_setup(struct console *co, char *options)
2339 {
2340         struct uart_port *port;
2341         int baud = 9600;
2342         int bits = 8;
2343         int parity = 'n';
2344         int flow = 'n';
2345
2346         /* is this a valid port */
2347
2348         if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2349                 co->index = 0;
2350
2351         port = &s3c24xx_serial_ports[co->index].port;
2352
2353         /* is the port configured? */
2354
2355         if (port->mapbase == 0x0)
2356                 return -ENODEV;
2357
2358         cons_uart = port;
2359
2360         /*
2361          * Check whether an invalid uart number has been specified, and
2362          * if so, search for the first available port that does have
2363          * console support.
2364          */
2365         if (options)
2366                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2367         else
2368                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2369
2370         dev_dbg(port->dev, "baud %d\n", baud);
2371
2372         return uart_set_options(port, co, baud, parity, bits, flow);
2373 }
2374
2375 static struct console s3c24xx_serial_console = {
2376         .name           = S3C24XX_SERIAL_NAME,
2377         .device         = uart_console_device,
2378         .flags          = CON_PRINTBUFFER,
2379         .index          = -1,
2380         .write          = s3c24xx_serial_console_write,
2381         .setup          = s3c24xx_serial_console_setup,
2382         .data           = &s3c24xx_uart_drv,
2383 };
2384 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2385
2386 #ifdef CONFIG_CPU_S3C2410
2387 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2388         .info = &(struct s3c24xx_uart_info) {
2389                 .name           = "Samsung S3C2410 UART",
2390                 .type           = PORT_S3C2410,
2391                 .fifosize       = 16,
2392                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2393                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2394                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2395                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2396                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2397                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2398                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2399                 .num_clks       = 2,
2400                 .clksel_mask    = S3C2410_UCON_CLKMASK,
2401                 .clksel_shift   = S3C2410_UCON_CLKSHIFT,
2402         },
2403         .def_cfg = &(struct s3c2410_uartcfg) {
2404                 .ucon           = S3C2410_UCON_DEFAULT,
2405                 .ufcon          = S3C2410_UFCON_DEFAULT,
2406         },
2407 };
2408 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2409 #else
2410 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2411 #endif
2412
2413 #ifdef CONFIG_CPU_S3C2412
2414 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2415         .info = &(struct s3c24xx_uart_info) {
2416                 .name           = "Samsung S3C2412 UART",
2417                 .type           = PORT_S3C2412,
2418                 .fifosize       = 64,
2419                 .has_divslot    = 1,
2420                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2421                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2422                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2423                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2424                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2425                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2426                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2427                 .num_clks       = 4,
2428                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2429                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2430         },
2431         .def_cfg = &(struct s3c2410_uartcfg) {
2432                 .ucon           = S3C2410_UCON_DEFAULT,
2433                 .ufcon          = S3C2410_UFCON_DEFAULT,
2434         },
2435 };
2436 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2437 #else
2438 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2439 #endif
2440
2441 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2442         defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2443 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2444         .info = &(struct s3c24xx_uart_info) {
2445                 .name           = "Samsung S3C2440 UART",
2446                 .type           = PORT_S3C2440,
2447                 .fifosize       = 64,
2448                 .has_divslot    = 1,
2449                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2450                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2451                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2452                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2453                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2454                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2455                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2456                 .num_clks       = 4,
2457                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2458                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2459         },
2460         .def_cfg = &(struct s3c2410_uartcfg) {
2461                 .ucon           = S3C2410_UCON_DEFAULT,
2462                 .ufcon          = S3C2410_UFCON_DEFAULT,
2463         },
2464 };
2465 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2466 #else
2467 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2468 #endif
2469
2470 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2471 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2472         .info = &(struct s3c24xx_uart_info) {
2473                 .name           = "Samsung S3C6400 UART",
2474                 .type           = PORT_S3C6400,
2475                 .fifosize       = 64,
2476                 .has_divslot    = 1,
2477                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2478                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2479                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2480                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2481                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2482                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2483                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2484                 .num_clks       = 4,
2485                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2486                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2487         },
2488         .def_cfg = &(struct s3c2410_uartcfg) {
2489                 .ucon           = S3C2410_UCON_DEFAULT,
2490                 .ufcon          = S3C2410_UFCON_DEFAULT,
2491         },
2492 };
2493 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2494 #else
2495 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2496 #endif
2497
2498 #ifdef CONFIG_CPU_S5PV210
2499 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2500         .info = &(struct s3c24xx_uart_info) {
2501                 .name           = "Samsung S5PV210 UART",
2502                 .type           = PORT_S3C6400,
2503                 .has_divslot    = 1,
2504                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2505                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2506                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2507                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2508                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2509                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2510                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2511                 .num_clks       = 2,
2512                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2513                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2514         },
2515         .def_cfg = &(struct s3c2410_uartcfg) {
2516                 .ucon           = S5PV210_UCON_DEFAULT,
2517                 .ufcon          = S5PV210_UFCON_DEFAULT,
2518         },
2519         .fifosize = { 256, 64, 16, 16 },
2520 };
2521 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2522 #else
2523 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2524 #endif
2525
2526 #if defined(CONFIG_ARCH_EXYNOS)
2527 #define EXYNOS_COMMON_SERIAL_DRV_DATA                           \
2528         .info = &(struct s3c24xx_uart_info) {                   \
2529                 .name           = "Samsung Exynos UART",        \
2530                 .type           = PORT_S3C6400,                 \
2531                 .has_divslot    = 1,                            \
2532                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2533                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2534                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2535                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2536                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2537                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2538                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2539                 .num_clks       = 1,                            \
2540                 .clksel_mask    = 0,                            \
2541                 .clksel_shift   = 0,                            \
2542         },                                                      \
2543         .def_cfg = &(struct s3c2410_uartcfg) {                  \
2544                 .ucon           = S5PV210_UCON_DEFAULT,         \
2545                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2546                 .has_fracval    = 1,                            \
2547         }                                                       \
2548
2549 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2550         EXYNOS_COMMON_SERIAL_DRV_DATA,
2551         .fifosize = { 256, 64, 16, 16 },
2552 };
2553
2554 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2555         EXYNOS_COMMON_SERIAL_DRV_DATA,
2556         .fifosize = { 64, 256, 16, 256 },
2557 };
2558
2559 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2560 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2561 #else
2562 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2563 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2564 #endif
2565
2566 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2567         {
2568                 .name           = "s3c2410-uart",
2569                 .driver_data    = S3C2410_SERIAL_DRV_DATA,
2570         }, {
2571                 .name           = "s3c2412-uart",
2572                 .driver_data    = S3C2412_SERIAL_DRV_DATA,
2573         }, {
2574                 .name           = "s3c2440-uart",
2575                 .driver_data    = S3C2440_SERIAL_DRV_DATA,
2576         }, {
2577                 .name           = "s3c6400-uart",
2578                 .driver_data    = S3C6400_SERIAL_DRV_DATA,
2579         }, {
2580                 .name           = "s5pv210-uart",
2581                 .driver_data    = S5PV210_SERIAL_DRV_DATA,
2582         }, {
2583                 .name           = "exynos4210-uart",
2584                 .driver_data    = EXYNOS4210_SERIAL_DRV_DATA,
2585         }, {
2586                 .name           = "exynos5433-uart",
2587                 .driver_data    = EXYNOS5433_SERIAL_DRV_DATA,
2588         },
2589         { },
2590 };
2591 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2592
2593 #ifdef CONFIG_OF
2594 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2595         { .compatible = "samsung,s3c2410-uart",
2596                 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2597         { .compatible = "samsung,s3c2412-uart",
2598                 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2599         { .compatible = "samsung,s3c2440-uart",
2600                 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2601         { .compatible = "samsung,s3c6400-uart",
2602                 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2603         { .compatible = "samsung,s5pv210-uart",
2604                 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2605         { .compatible = "samsung,exynos4210-uart",
2606                 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2607         { .compatible = "samsung,exynos5433-uart",
2608                 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2609         {},
2610 };
2611 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2612 #endif
2613
2614 static struct platform_driver samsung_serial_driver = {
2615         .probe          = s3c24xx_serial_probe,
2616         .remove         = s3c24xx_serial_remove,
2617         .id_table       = s3c24xx_serial_driver_ids,
2618         .driver         = {
2619                 .name   = "samsung-uart",
2620                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2621                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2622         },
2623 };
2624
2625 module_platform_driver(samsung_serial_driver);
2626
2627 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2628 /*
2629  * Early console.
2630  */
2631
2632 static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val)
2633 {
2634         switch (port->iotype) {
2635         case UPIO_MEM:
2636                 writeb(val, portaddr(port, reg));
2637                 break;
2638         case UPIO_MEM32:
2639                 writel(val, portaddr(port, reg));
2640                 break;
2641         }
2642 }
2643
2644 struct samsung_early_console_data {
2645         u32 txfull_mask;
2646 };
2647
2648 static void samsung_early_busyuart(struct uart_port *port)
2649 {
2650         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2651                 ;
2652 }
2653
2654 static void samsung_early_busyuart_fifo(struct uart_port *port)
2655 {
2656         struct samsung_early_console_data *data = port->private_data;
2657
2658         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2659                 ;
2660 }
2661
2662 static void samsung_early_putc(struct uart_port *port, int c)
2663 {
2664         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2665                 samsung_early_busyuart_fifo(port);
2666         else
2667                 samsung_early_busyuart(port);
2668
2669         wr_reg_barrier(port, S3C2410_UTXH, c);
2670 }
2671
2672 static void samsung_early_write(struct console *con, const char *s,
2673                                 unsigned int n)
2674 {
2675         struct earlycon_device *dev = con->data;
2676
2677         uart_console_write(&dev->port, s, n, samsung_early_putc);
2678 }
2679
2680 static int __init samsung_early_console_setup(struct earlycon_device *device,
2681                                               const char *opt)
2682 {
2683         if (!device->port.membase)
2684                 return -ENODEV;
2685
2686         device->con->write = samsung_early_write;
2687         return 0;
2688 }
2689
2690 /* S3C2410 */
2691 static struct samsung_early_console_data s3c2410_early_console_data = {
2692         .txfull_mask = S3C2410_UFSTAT_TXFULL,
2693 };
2694
2695 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2696                                               const char *opt)
2697 {
2698         device->port.private_data = &s3c2410_early_console_data;
2699         return samsung_early_console_setup(device, opt);
2700 }
2701
2702 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2703                         s3c2410_early_console_setup);
2704
2705 /* S3C2412, S3C2440, S3C64xx */
2706 static struct samsung_early_console_data s3c2440_early_console_data = {
2707         .txfull_mask = S3C2440_UFSTAT_TXFULL,
2708 };
2709
2710 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2711                                               const char *opt)
2712 {
2713         device->port.private_data = &s3c2440_early_console_data;
2714         return samsung_early_console_setup(device, opt);
2715 }
2716
2717 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2718                         s3c2440_early_console_setup);
2719 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2720                         s3c2440_early_console_setup);
2721 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2722                         s3c2440_early_console_setup);
2723
2724 /* S5PV210, Exynos */
2725 static struct samsung_early_console_data s5pv210_early_console_data = {
2726         .txfull_mask = S5PV210_UFSTAT_TXFULL,
2727 };
2728
2729 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2730                                               const char *opt)
2731 {
2732         device->port.private_data = &s5pv210_early_console_data;
2733         return samsung_early_console_setup(device, opt);
2734 }
2735
2736 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2737                         s5pv210_early_console_setup);
2738 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2739                         s5pv210_early_console_setup);
2740 #endif
2741
2742 MODULE_ALIAS("platform:samsung-uart");
2743 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2744 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2745 MODULE_LICENSE("GPL v2");