rtc/rtc-ds1307.c

   1 /*
   2  * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
   3  *
   4  *  Copyright (C) 2005 James Chapman (ds1337 core)
   5  *  Copyright (C) 2006 David Brownell
   6  *  Copyright (C) 2009 Matthias Fuchs (rx8025 support)
   7  *  Copyright (C) 2012 Bertrand Achard (nvram access fixes)
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/acpi.h>
  15 #include <linux/bcd.h>
  16 #include <linux/i2c.h>
  17 #include <linux/init.h>
  18 #include <linux/module.h>
  19 #include <linux/of_device.h>
  20 #include <linux/rtc/ds1307.h>
  21 #include <linux/rtc.h>
  22 #include <linux/slab.h>
  23 #include <linux/string.h>
  24 #include <linux/hwmon.h>
  25 #include <linux/hwmon-sysfs.h>
  26 #include <linux/clk-provider.h>
  27 #include <linux/regmap.h>
  28
  29 /*
  30  * We can't determine type by probing, but if we expect pre-Linux code
  31  * to have set the chip up as a clock (turning on the oscillator and
  32  * setting the date and time), Linux can ignore the non-clock features.
  33  * That's a natural job for a factory or repair bench.
  34  */
  35 enum ds_type {
  36         ds_1307,
  37         ds_1308,
  38         ds_1337,
  39         ds_1338,
  40         ds_1339,
  41         ds_1340,
  42         ds_1341,
  43         ds_1388,
  44         ds_3231,
  45         m41t0,
  46         m41t00,
  47         m41t11,
  48         mcp794xx,
  49         rx_8025,
  50         rx_8130,
  51         last_ds_type /* always last */
  52         /* rs5c372 too?  different address... */
  53 };
  54
  55 /* RTC registers don't differ much, except for the century flag */
  56 #define DS1307_REG_SECS         0x00    /* 00-59 */
  57 #       define DS1307_BIT_CH            0x80
  58 #       define DS1340_BIT_nEOSC         0x80
  59 #       define MCP794XX_BIT_ST          0x80
  60 #define DS1307_REG_MIN          0x01    /* 00-59 */
  61 #       define M41T0_BIT_OF             0x80
  62 #define DS1307_REG_HOUR         0x02    /* 00-23, or 1-12{am,pm} */
  63 #       define DS1307_BIT_12HR          0x40    /* in REG_HOUR */
  64 #       define DS1307_BIT_PM            0x20    /* in REG_HOUR */
  65 #       define DS1340_BIT_CENTURY_EN    0x80    /* in REG_HOUR */
  66 #       define DS1340_BIT_CENTURY       0x40    /* in REG_HOUR */
  67 #define DS1307_REG_WDAY         0x03    /* 01-07 */
  68 #       define MCP794XX_BIT_VBATEN      0x08
  69 #define DS1307_REG_MDAY         0x04    /* 01-31 */
  70 #define DS1307_REG_MONTH        0x05    /* 01-12 */
  71 #       define DS1337_BIT_CENTURY       0x80    /* in REG_MONTH */
  72 #define DS1307_REG_YEAR         0x06    /* 00-99 */
  73
  74 /*
  75  * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
  76  * start at 7, and they differ a LOT. Only control and status matter for
  77  * basic RTC date and time functionality; be careful using them.
  78  */
  79 #define DS1307_REG_CONTROL      0x07            /* or ds1338 */
  80 #       define DS1307_BIT_OUT           0x80
  81 #       define DS1338_BIT_OSF           0x20
  82 #       define DS1307_BIT_SQWE          0x10
  83 #       define DS1307_BIT_RS1           0x02
  84 #       define DS1307_BIT_RS0           0x01
  85 #define DS1337_REG_CONTROL      0x0e
  86 #       define DS1337_BIT_nEOSC         0x80
  87 #       define DS1339_BIT_BBSQI         0x20
  88 #       define DS3231_BIT_BBSQW         0x40 /* same as BBSQI */
  89 #       define DS1337_BIT_RS2           0x10
  90 #       define DS1337_BIT_RS1           0x08
  91 #       define DS1337_BIT_INTCN         0x04
  92 #       define DS1337_BIT_A2IE          0x02
  93 #       define DS1337_BIT_A1IE          0x01
  94 #define DS1340_REG_CONTROL      0x07
  95 #       define DS1340_BIT_OUT           0x80
  96 #       define DS1340_BIT_FT            0x40
  97 #       define DS1340_BIT_CALIB_SIGN    0x20
  98 #       define DS1340_M_CALIBRATION     0x1f
  99 #define DS1340_REG_FLAG         0x09
 100 #       define DS1340_BIT_OSF           0x80
 101 #define DS1337_REG_STATUS       0x0f
 102 #       define DS1337_BIT_OSF           0x80
 103 #       define DS3231_BIT_EN32KHZ       0x08
 104 #       define DS1337_BIT_A2I           0x02
 105 #       define DS1337_BIT_A1I           0x01
 106 #define DS1339_REG_ALARM1_SECS  0x07
 107
 108 #define DS13XX_TRICKLE_CHARGER_MAGIC    0xa0
 109
 110 #define RX8025_REG_CTRL1        0x0e
 111 #       define RX8025_BIT_2412          0x20
 112 #define RX8025_REG_CTRL2        0x0f
 113 #       define RX8025_BIT_PON           0x10
 114 #       define RX8025_BIT_VDET          0x40
 115 #       define RX8025_BIT_XST           0x20
 116
 117 struct ds1307 {
 118         enum ds_type            type;
 119         unsigned long           flags;
 120 #define HAS_NVRAM       0               /* bit 0 == sysfs file active */
 121 #define HAS_ALARM       1               /* bit 1 == irq claimed */
 122         struct device           *dev;
 123         struct regmap           *regmap;
 124         const char              *name;
 125         struct rtc_device       *rtc;
 126 #ifdef CONFIG_COMMON_CLK
 127         struct clk_hw           clks[2];
 128 #endif
 129 };
 130
 131 struct chip_desc {
 132         unsigned                alarm:1;
 133         u16                     nvram_offset;
 134         u16                     nvram_size;
 135         u8                      offset; /* register's offset */
 136         u8                      century_reg;
 137         u8                      century_enable_bit;
 138         u8                      century_bit;
 139         u8                      bbsqi_bit;
 140         irq_handler_t           irq_handler;
 141         const struct rtc_class_ops *rtc_ops;
 142         u16                     trickle_charger_reg;
 143         u8                      (*do_trickle_setup)(struct ds1307 *, u32,
 144                                                     bool);
 145 };
 146
 147 static int ds1307_get_time(struct device *dev, struct rtc_time *t);
 148 static int ds1307_set_time(struct device *dev, struct rtc_time *t);
 149 static u8 do_trickle_setup_ds1339(struct ds1307 *, u32 ohms, bool diode);
 150 static irqreturn_t rx8130_irq(int irq, void *dev_id);
 151 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t);
 152 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t);
 153 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled);
 154 static irqreturn_t mcp794xx_irq(int irq, void *dev_id);
 155 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t);
 156 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t);
 157 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled);
 158
 159 static const struct rtc_class_ops rx8130_rtc_ops = {
 160         .read_time      = ds1307_get_time,
 161         .set_time       = ds1307_set_time,
 162         .read_alarm     = rx8130_read_alarm,
 163         .set_alarm      = rx8130_set_alarm,
 164         .alarm_irq_enable = rx8130_alarm_irq_enable,
 165 };
 166
 167 static const struct rtc_class_ops mcp794xx_rtc_ops = {
 168         .read_time      = ds1307_get_time,
 169         .set_time       = ds1307_set_time,
 170         .read_alarm     = mcp794xx_read_alarm,
 171         .set_alarm      = mcp794xx_set_alarm,
 172         .alarm_irq_enable = mcp794xx_alarm_irq_enable,
 173 };
 174
 175 static const struct chip_desc chips[last_ds_type] = {
 176         [ds_1307] = {
 177                 .nvram_offset   = 8,
 178                 .nvram_size     = 56,
 179         },
 180         [ds_1308] = {
 181                 .nvram_offset   = 8,
 182                 .nvram_size     = 56,
 183         },
 184         [ds_1337] = {
 185                 .alarm          = 1,
 186                 .century_reg    = DS1307_REG_MONTH,
 187                 .century_bit    = DS1337_BIT_CENTURY,
 188         },
 189         [ds_1338] = {
 190                 .nvram_offset   = 8,
 191                 .nvram_size     = 56,
 192         },
 193         [ds_1339] = {
 194                 .alarm          = 1,
 195                 .century_reg    = DS1307_REG_MONTH,
 196                 .century_bit    = DS1337_BIT_CENTURY,
 197                 .bbsqi_bit      = DS1339_BIT_BBSQI,
 198                 .trickle_charger_reg = 0x10,
 199                 .do_trickle_setup = &do_trickle_setup_ds1339,
 200         },
 201         [ds_1340] = {
 202                 .century_reg    = DS1307_REG_HOUR,
 203                 .century_enable_bit = DS1340_BIT_CENTURY_EN,
 204                 .century_bit    = DS1340_BIT_CENTURY,
 205                 .do_trickle_setup = &do_trickle_setup_ds1339,
 206                 .trickle_charger_reg = 0x08,
 207         },
 208         [ds_1341] = {
 209                 .century_reg    = DS1307_REG_MONTH,
 210                 .century_bit    = DS1337_BIT_CENTURY,
 211         },
 212         [ds_1388] = {
 213                 .offset         = 1,
 214                 .trickle_charger_reg = 0x0a,
 215         },
 216         [ds_3231] = {
 217                 .alarm          = 1,
 218                 .century_reg    = DS1307_REG_MONTH,
 219                 .century_bit    = DS1337_BIT_CENTURY,
 220                 .bbsqi_bit      = DS3231_BIT_BBSQW,
 221         },
 222         [rx_8130] = {
 223                 .alarm          = 1,
 224                 /* this is battery backed SRAM */
 225                 .nvram_offset   = 0x20,
 226                 .nvram_size     = 4,    /* 32bit (4 word x 8 bit) */
 227                 .offset         = 0x10,
 228                 .irq_handler = rx8130_irq,
 229                 .rtc_ops = &rx8130_rtc_ops,
 230         },
 231         [m41t11] = {
 232                 /* this is battery backed SRAM */
 233                 .nvram_offset   = 8,
 234                 .nvram_size     = 56,
 235         },
 236         [mcp794xx] = {
 237                 .alarm          = 1,
 238                 /* this is battery backed SRAM */
 239                 .nvram_offset   = 0x20,
 240                 .nvram_size     = 0x40,
 241                 .irq_handler = mcp794xx_irq,
 242                 .rtc_ops = &mcp794xx_rtc_ops,
 243         },
 244 };
 245
 246 static const struct i2c_device_id ds1307_id[] = {
 247         { "ds1307", ds_1307 },
 248         { "ds1308", ds_1308 },
 249         { "ds1337", ds_1337 },
 250         { "ds1338", ds_1338 },
 251         { "ds1339", ds_1339 },
 252         { "ds1388", ds_1388 },
 253         { "ds1340", ds_1340 },
 254         { "ds1341", ds_1341 },
 255         { "ds3231", ds_3231 },
 256         { "m41t0", m41t0 },
 257         { "m41t00", m41t00 },
 258         { "m41t11", m41t11 },
 259         { "mcp7940x", mcp794xx },
 260         { "mcp7941x", mcp794xx },
 261         { "pt7c4338", ds_1307 },
 262         { "rx8025", rx_8025 },
 263         { "isl12057", ds_1337 },
 264         { "rx8130", rx_8130 },
 265         { }
 266 };
 267 MODULE_DEVICE_TABLE(i2c, ds1307_id);
 268
 269 #ifdef CONFIG_OF
 270 static const struct of_device_id ds1307_of_match[] = {
 271         {
 272                 .compatible = "dallas,ds1307",
 273                 .data = (void *)ds_1307
 274         },
 275         {
 276                 .compatible = "dallas,ds1308",
 277                 .data = (void *)ds_1308
 278         },
 279         {
 280                 .compatible = "dallas,ds1337",
 281                 .data = (void *)ds_1337
 282         },
 283         {
 284                 .compatible = "dallas,ds1338",
 285                 .data = (void *)ds_1338
 286         },
 287         {
 288                 .compatible = "dallas,ds1339",
 289                 .data = (void *)ds_1339
 290         },
 291         {
 292                 .compatible = "dallas,ds1388",
 293                 .data = (void *)ds_1388
 294         },
 295         {
 296                 .compatible = "dallas,ds1340",
 297                 .data = (void *)ds_1340
 298         },
 299         {
 300                 .compatible = "dallas,ds1341",
 301                 .data = (void *)ds_1341
 302         },
 303         {
 304                 .compatible = "maxim,ds3231",
 305                 .data = (void *)ds_3231
 306         },
 307         {
 308                 .compatible = "st,m41t0",
 309                 .data = (void *)m41t0
 310         },
 311         {
 312                 .compatible = "st,m41t00",
 313                 .data = (void *)m41t00
 314         },
 315         {
 316                 .compatible = "st,m41t11",
 317                 .data = (void *)m41t11
 318         },
 319         {
 320                 .compatible = "microchip,mcp7940x",
 321                 .data = (void *)mcp794xx
 322         },
 323         {
 324                 .compatible = "microchip,mcp7941x",
 325                 .data = (void *)mcp794xx
 326         },
 327         {
 328                 .compatible = "pericom,pt7c4338",
 329                 .data = (void *)ds_1307
 330         },
 331         {
 332                 .compatible = "epson,rx8025",
 333                 .data = (void *)rx_8025
 334         },
 335         {
 336                 .compatible = "isil,isl12057",
 337                 .data = (void *)ds_1337
 338         },
 339         {
 340                 .compatible = "epson,rx8130",
 341                 .data = (void *)rx_8130
 342         },
 343         { }
 344 };
 345 MODULE_DEVICE_TABLE(of, ds1307_of_match);
 346 #endif
 347
 348 #ifdef CONFIG_ACPI
 349 static const struct acpi_device_id ds1307_acpi_ids[] = {
 350         { .id = "DS1307", .driver_data = ds_1307 },
 351         { .id = "DS1308", .driver_data = ds_1308 },
 352         { .id = "DS1337", .driver_data = ds_1337 },
 353         { .id = "DS1338", .driver_data = ds_1338 },
 354         { .id = "DS1339", .driver_data = ds_1339 },
 355         { .id = "DS1388", .driver_data = ds_1388 },
 356         { .id = "DS1340", .driver_data = ds_1340 },
 357         { .id = "DS1341", .driver_data = ds_1341 },
 358         { .id = "DS3231", .driver_data = ds_3231 },
 359         { .id = "M41T0", .driver_data = m41t0 },
 360         { .id = "M41T00", .driver_data = m41t00 },
 361         { .id = "M41T11", .driver_data = m41t11 },
 362         { .id = "MCP7940X", .driver_data = mcp794xx },
 363         { .id = "MCP7941X", .driver_data = mcp794xx },
 364         { .id = "PT7C4338", .driver_data = ds_1307 },
 365         { .id = "RX8025", .driver_data = rx_8025 },
 366         { .id = "ISL12057", .driver_data = ds_1337 },
 367         { .id = "RX8130", .driver_data = rx_8130 },
 368         { }
 369 };
 370 MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
 371 #endif
 372
 373 /*
 374  * The ds1337 and ds1339 both have two alarms, but we only use the first
 375  * one (with a "seconds" field).  For ds1337 we expect nINTA is our alarm
 376  * signal; ds1339 chips have only one alarm signal.
 377  */
 378 static irqreturn_t ds1307_irq(int irq, void *dev_id)
 379 {
 380         struct ds1307           *ds1307 = dev_id;
 381         struct mutex            *lock = &ds1307->rtc->ops_lock;
 382         int                     stat, ret;
 383
 384         mutex_lock(lock);
 385         ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
 386         if (ret)
 387                 goto out;
 388
 389         if (stat & DS1337_BIT_A1I) {
 390                 stat &= ~DS1337_BIT_A1I;
 391                 regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
 392
 393                 ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
 394                                          DS1337_BIT_A1IE, 0);
 395                 if (ret)
 396                         goto out;
 397
 398                 rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
 399         }
 400
 401 out:
 402         mutex_unlock(lock);
 403
 404         return IRQ_HANDLED;
 405 }
 406
 407 /*----------------------------------------------------------------------*/
 408
 409 static int ds1307_get_time(struct device *dev, struct rtc_time *t)
 410 {
 411         struct ds1307   *ds1307 = dev_get_drvdata(dev);
 412         int             tmp, ret;
 413         const struct chip_desc *chip = &chips[ds1307->type];
 414         u8 regs[7];
 415
 416         /* read the RTC date and time registers all at once */
 417         ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
 418                                sizeof(regs));
 419         if (ret) {
 420                 dev_err(dev, "%s error %d\n", "read", ret);
 421                 return ret;
 422         }
 423
 424         dev_dbg(dev, "%s: %7ph\n", "read", regs);
 425
 426         /* if oscillator fail bit is set, no data can be trusted */
 427         if (ds1307->type == m41t0 &&
 428             regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
 429                 dev_warn_once(dev, "oscillator failed, set time!\n");
 430                 return -EINVAL;
 431         }
 432
 433         t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
 434         t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
 435         tmp = regs[DS1307_REG_HOUR] & 0x3f;
 436         t->tm_hour = bcd2bin(tmp);
 437         /* rx8130 is bit position, not BCD */
 438         if (ds1307->type == rx_8130)
 439                 t->tm_wday = fls(regs[DS1307_REG_WDAY] & 0x7f);
 440         else
 441                 t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
 442         t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
 443         tmp = regs[DS1307_REG_MONTH] & 0x1f;
 444         t->tm_mon = bcd2bin(tmp) - 1;
 445         t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
 446
 447         if (regs[chip->century_reg] & chip->century_bit &&
 448             IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
 449                 t->tm_year += 100;
 450
 451         dev_dbg(dev, "%s secs=%d, mins=%d, "
 452                 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
 453                 "read", t->tm_sec, t->tm_min,
 454                 t->tm_hour, t->tm_mday,
 455                 t->tm_mon, t->tm_year, t->tm_wday);
 456
 457         return 0;
 458 }
 459
 460 static int ds1307_set_time(struct device *dev, struct rtc_time *t)
 461 {
 462         struct ds1307   *ds1307 = dev_get_drvdata(dev);
 463         const struct chip_desc *chip = &chips[ds1307->type];
 464         int             result;
 465         int             tmp;
 466         u8              regs[7];
 467
 468         dev_dbg(dev, "%s secs=%d, mins=%d, "
 469                 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
 470                 "write", t->tm_sec, t->tm_min,
 471                 t->tm_hour, t->tm_mday,
 472                 t->tm_mon, t->tm_year, t->tm_wday);
 473
 474         if (t->tm_year < 100)
 475                 return -EINVAL;
 476
 477 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY
 478         if (t->tm_year > (chip->century_bit ? 299 : 199))
 479                 return -EINVAL;
 480 #else
 481         if (t->tm_year > 199)
 482                 return -EINVAL;
 483 #endif
 484
 485         regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
 486         regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
 487         regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
 488         /* rx8130 is bit position, not BCD */
 489         if (ds1307->type == rx_8130)
 490                 regs[DS1307_REG_WDAY] = 1 << t->tm_wday;
 491         else
 492                 regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
 493         regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
 494         regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
 495
 496         /* assume 20YY not 19YY */
 497         tmp = t->tm_year - 100;
 498         regs[DS1307_REG_YEAR] = bin2bcd(tmp);
 499
 500         if (chip->century_enable_bit)
 501                 regs[chip->century_reg] |= chip->century_enable_bit;
 502         if (t->tm_year > 199 && chip->century_bit)
 503                 regs[chip->century_reg] |= chip->century_bit;
 504
 505         if (ds1307->type == mcp794xx) {
 506                 /*
 507                  * these bits were cleared when preparing the date/time
 508                  * values and need to be set again before writing the
 509                  * regsfer out to the device.
 510                  */
 511                 regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
 512                 regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
 513         }
 514
 515         dev_dbg(dev, "%s: %7ph\n", "write", regs);
 516
 517         result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
 518                                    sizeof(regs));
 519         if (result) {
 520                 dev_err(dev, "%s error %d\n", "write", result);
 521                 return result;
 522         }
 523         return 0;
 524 }
 525
 526 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
 527 {
 528         struct ds1307           *ds1307 = dev_get_drvdata(dev);
 529         int                     ret;
 530         u8                      regs[9];
 531
 532         if (!test_bit(HAS_ALARM, &ds1307->flags))
 533                 return -EINVAL;
 534
 535         /* read all ALARM1, ALARM2, and status registers at once */
 536         ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
 537                                regs, sizeof(regs));
 538         if (ret) {
 539                 dev_err(dev, "%s error %d\n", "alarm read", ret);
 540                 return ret;
 541         }
 542
 543         dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
 544                 &regs[0], &regs[4], &regs[7]);
 545
 546         /*
 547          * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
 548          * and that all four fields are checked matches
 549          */
 550         t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
 551         t->time.tm_min = bcd2bin(regs[1] & 0x7f);
 552         t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
 553         t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
 554
 555         /* ... and status */
 556         t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
 557         t->pending = !!(regs[8] & DS1337_BIT_A1I);
 558
 559         dev_dbg(dev, "%s secs=%d, mins=%d, "
 560                 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
 561                 "alarm read", t->time.tm_sec, t->time.tm_min,
 562                 t->time.tm_hour, t->time.tm_mday,
 563                 t->enabled, t->pending);
 564
 565         return 0;
 566 }
 567
 568 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
 569 {
 570         struct ds1307           *ds1307 = dev_get_drvdata(dev);
 571         unsigned char           regs[9];
 572         u8                      control, status;
 573         int                     ret;
 574
 575         if (!test_bit(HAS_ALARM, &ds1307->flags))
 576                 return -EINVAL;
 577
 578         dev_dbg(dev, "%s secs=%d, mins=%d, "
 579                 "hours=%d, mday=%d, enabled=%d, pending=%d\n",
 580                 "alarm set", t->time.tm_sec, t->time.tm_min,
 581                 t->time.tm_hour, t->time.tm_mday,
 582                 t->enabled, t->pending);
 583
 584         /* read current status of both alarms and the chip */
 585         ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
 586                                sizeof(regs));
 587         if (ret) {
 588                 dev_err(dev, "%s error %d\n", "alarm write", ret);
 589                 return ret;
 590         }
 591         control = regs[7];
 592         status = regs[8];
 593
 594         dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
 595                 &regs[0], &regs[4], control, status);
 596
 597         /* set ALARM1, using 24 hour and day-of-month modes */
 598         regs[0] = bin2bcd(t->time.tm_sec);
 599         regs[1] = bin2bcd(t->time.tm_min);
 600         regs[2] = bin2bcd(t->time.tm_hour);
 601         regs[3] = bin2bcd(t->time.tm_mday);
 602
 603         /* set ALARM2 to non-garbage */
 604         regs[4] = 0;
 605         regs[5] = 0;
 606         regs[6] = 0;
 607
 608         /* disable alarms */
 609         regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
 610         regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
 611
 612         ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
 613                                 sizeof(regs));
 614         if (ret) {
 615                 dev_err(dev, "can't set alarm time\n");
 616                 return ret;
 617         }
 618
 619         /* optionally enable ALARM1 */
 620         if (t->enabled) {
 621                 dev_dbg(dev, "alarm IRQ armed\n");
 622                 regs[7] |= DS1337_BIT_A1IE;     /* only ALARM1 is used */
 623                 regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
 624         }
 625
 626         return 0;
 627 }
 628
 629 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
 630 {
 631         struct ds1307           *ds1307 = dev_get_drvdata(dev);
 632
 633         if (!test_bit(HAS_ALARM, &ds1307->flags))
 634                 return -ENOTTY;
 635
 636         return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
 637                                   DS1337_BIT_A1IE,
 638                                   enabled ? DS1337_BIT_A1IE : 0);
 639 }
 640
 641 static const struct rtc_class_ops ds13xx_rtc_ops = {
 642         .read_time      = ds1307_get_time,
 643         .set_time       = ds1307_set_time,
 644         .read_alarm     = ds1337_read_alarm,
 645         .set_alarm      = ds1337_set_alarm,
 646         .alarm_irq_enable = ds1307_alarm_irq_enable,
 647 };
 648
 649 /*----------------------------------------------------------------------*/
 650
 651 /*
 652  * Alarm support for rx8130 devices.
 653  */
 654
 655 #define RX8130_REG_ALARM_MIN            0x07
 656 #define RX8130_REG_ALARM_HOUR           0x08
 657 #define RX8130_REG_ALARM_WEEK_OR_DAY    0x09
 658 #define RX8130_REG_EXTENSION            0x0c
 659 #define RX8130_REG_EXTENSION_WADA       BIT(3)
 660 #define RX8130_REG_FLAG                 0x0d
 661 #define RX8130_REG_FLAG_AF              BIT(3)
 662 #define RX8130_REG_CONTROL0             0x0e
 663 #define RX8130_REG_CONTROL0_AIE         BIT(3)
 664
 665 static irqreturn_t rx8130_irq(int irq, void *dev_id)
 666 {
 667         struct ds1307           *ds1307 = dev_id;
 668         struct mutex            *lock = &ds1307->rtc->ops_lock;
 669         u8 ctl[3];
 670         int ret;
 671
 672         mutex_lock(lock);
 673
 674         /* Read control registers. */
 675         ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 676                                sizeof(ctl));
 677         if (ret < 0)
 678                 goto out;
 679         if (!(ctl[1] & RX8130_REG_FLAG_AF))
 680                 goto out;
 681         ctl[1] &= ~RX8130_REG_FLAG_AF;
 682         ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
 683
 684         ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 685                                 sizeof(ctl));
 686         if (ret < 0)
 687                 goto out;
 688
 689         rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
 690
 691 out:
 692         mutex_unlock(lock);
 693
 694         return IRQ_HANDLED;
 695 }
 696
 697 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
 698 {
 699         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 700         u8 ald[3], ctl[3];
 701         int ret;
 702
 703         if (!test_bit(HAS_ALARM, &ds1307->flags))
 704                 return -EINVAL;
 705
 706         /* Read alarm registers. */
 707         ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
 708                                sizeof(ald));
 709         if (ret < 0)
 710                 return ret;
 711
 712         /* Read control registers. */
 713         ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 714                                sizeof(ctl));
 715         if (ret < 0)
 716                 return ret;
 717
 718         t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
 719         t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
 720
 721         /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
 722         t->time.tm_sec = -1;
 723         t->time.tm_min = bcd2bin(ald[0] & 0x7f);
 724         t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
 725         t->time.tm_wday = -1;
 726         t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
 727         t->time.tm_mon = -1;
 728         t->time.tm_year = -1;
 729         t->time.tm_yday = -1;
 730         t->time.tm_isdst = -1;
 731
 732         dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
 733                 __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
 734                 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
 735
 736         return 0;
 737 }
 738
 739 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
 740 {
 741         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 742         u8 ald[3], ctl[3];
 743         int ret;
 744
 745         if (!test_bit(HAS_ALARM, &ds1307->flags))
 746                 return -EINVAL;
 747
 748         dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
 749                 "enabled=%d pending=%d\n", __func__,
 750                 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
 751                 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
 752                 t->enabled, t->pending);
 753
 754         /* Read control registers. */
 755         ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 756                                sizeof(ctl));
 757         if (ret < 0)
 758                 return ret;
 759
 760         ctl[0] &= RX8130_REG_EXTENSION_WADA;
 761         ctl[1] &= ~RX8130_REG_FLAG_AF;
 762         ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
 763
 764         ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
 765                                 sizeof(ctl));
 766         if (ret < 0)
 767                 return ret;
 768
 769         /* Hardware alarm precision is 1 minute! */
 770         ald[0] = bin2bcd(t->time.tm_min);
 771         ald[1] = bin2bcd(t->time.tm_hour);
 772         ald[2] = bin2bcd(t->time.tm_mday);
 773
 774         ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
 775                                 sizeof(ald));
 776         if (ret < 0)
 777                 return ret;
 778
 779         if (!t->enabled)
 780                 return 0;
 781
 782         ctl[2] |= RX8130_REG_CONTROL0_AIE;
 783
 784         return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
 785 }
 786
 787 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
 788 {
 789         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 790         int ret, reg;
 791
 792         if (!test_bit(HAS_ALARM, &ds1307->flags))
 793                 return -EINVAL;
 794
 795         ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, &reg);
 796         if (ret < 0)
 797                 return ret;
 798
 799         if (enabled)
 800                 reg |= RX8130_REG_CONTROL0_AIE;
 801         else
 802                 reg &= ~RX8130_REG_CONTROL0_AIE;
 803
 804         return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
 805 }
 806
 807 /*----------------------------------------------------------------------*/
 808
 809 /*
 810  * Alarm support for mcp794xx devices.
 811  */
 812
 813 #define MCP794XX_REG_CONTROL            0x07
 814 #       define MCP794XX_BIT_ALM0_EN     0x10
 815 #       define MCP794XX_BIT_ALM1_EN     0x20
 816 #define MCP794XX_REG_ALARM0_BASE        0x0a
 817 #define MCP794XX_REG_ALARM0_CTRL        0x0d
 818 #define MCP794XX_REG_ALARM1_BASE        0x11
 819 #define MCP794XX_REG_ALARM1_CTRL        0x14
 820 #       define MCP794XX_BIT_ALMX_IF     BIT(3)
 821 #       define MCP794XX_BIT_ALMX_C0     BIT(4)
 822 #       define MCP794XX_BIT_ALMX_C1     BIT(5)
 823 #       define MCP794XX_BIT_ALMX_C2     BIT(6)
 824 #       define MCP794XX_BIT_ALMX_POL    BIT(7)
 825 #       define MCP794XX_MSK_ALMX_MATCH  (MCP794XX_BIT_ALMX_C0 | \
 826                                          MCP794XX_BIT_ALMX_C1 | \
 827                                          MCP794XX_BIT_ALMX_C2)
 828
 829 static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
 830 {
 831         struct ds1307           *ds1307 = dev_id;
 832         struct mutex            *lock = &ds1307->rtc->ops_lock;
 833         int reg, ret;
 834
 835         mutex_lock(lock);
 836
 837         /* Check and clear alarm 0 interrupt flag. */
 838         ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
 839         if (ret)
 840                 goto out;
 841         if (!(reg & MCP794XX_BIT_ALMX_IF))
 842                 goto out;
 843         reg &= ~MCP794XX_BIT_ALMX_IF;
 844         ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
 845         if (ret)
 846                 goto out;
 847
 848         /* Disable alarm 0. */
 849         ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
 850                                  MCP794XX_BIT_ALM0_EN, 0);
 851         if (ret)
 852                 goto out;
 853
 854         rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
 855
 856 out:
 857         mutex_unlock(lock);
 858
 859         return IRQ_HANDLED;
 860 }
 861
 862 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
 863 {
 864         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 865         u8 regs[10];
 866         int ret;
 867
 868         if (!test_bit(HAS_ALARM, &ds1307->flags))
 869                 return -EINVAL;
 870
 871         /* Read control and alarm 0 registers. */
 872         ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
 873                                sizeof(regs));
 874         if (ret)
 875                 return ret;
 876
 877         t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
 878
 879         /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
 880         t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
 881         t->time.tm_min = bcd2bin(regs[4] & 0x7f);
 882         t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
 883         t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
 884         t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
 885         t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
 886         t->time.tm_year = -1;
 887         t->time.tm_yday = -1;
 888         t->time.tm_isdst = -1;
 889
 890         dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
 891                 "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
 892                 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
 893                 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
 894                 !!(regs[6] & MCP794XX_BIT_ALMX_POL),
 895                 !!(regs[6] & MCP794XX_BIT_ALMX_IF),
 896                 (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
 897
 898         return 0;
 899 }
 900
 901 /*
 902  * We may have a random RTC weekday, therefore calculate alarm weekday based
 903  * on current weekday we read from the RTC timekeeping regs
 904  */
 905 static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
 906 {
 907         struct rtc_time tm_now;
 908         int days_now, days_alarm, ret;
 909
 910         ret = ds1307_get_time(dev, &tm_now);
 911         if (ret)
 912                 return ret;
 913
 914         days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
 915         days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
 916
 917         return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
 918 }
 919
 920 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
 921 {
 922         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 923         unsigned char regs[10];
 924         int wday, ret;
 925
 926         if (!test_bit(HAS_ALARM, &ds1307->flags))
 927                 return -EINVAL;
 928
 929         wday = mcp794xx_alm_weekday(dev, &t->time);
 930         if (wday < 0)
 931                 return wday;
 932
 933         dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
 934                 "enabled=%d pending=%d\n", __func__,
 935                 t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
 936                 t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
 937                 t->enabled, t->pending);
 938
 939         /* Read control and alarm 0 registers. */
 940         ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
 941                                sizeof(regs));
 942         if (ret)
 943                 return ret;
 944
 945         /* Set alarm 0, using 24-hour and day-of-month modes. */
 946         regs[3] = bin2bcd(t->time.tm_sec);
 947         regs[4] = bin2bcd(t->time.tm_min);
 948         regs[5] = bin2bcd(t->time.tm_hour);
 949         regs[6] = wday;
 950         regs[7] = bin2bcd(t->time.tm_mday);
 951         regs[8] = bin2bcd(t->time.tm_mon + 1);
 952
 953         /* Clear the alarm 0 interrupt flag. */
 954         regs[6] &= ~MCP794XX_BIT_ALMX_IF;
 955         /* Set alarm match: second, minute, hour, day, date, month. */
 956         regs[6] |= MCP794XX_MSK_ALMX_MATCH;
 957         /* Disable interrupt. We will not enable until completely programmed */
 958         regs[0] &= ~MCP794XX_BIT_ALM0_EN;
 959
 960         ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
 961                                 sizeof(regs));
 962         if (ret)
 963                 return ret;
 964
 965         if (!t->enabled)
 966                 return 0;
 967         regs[0] |= MCP794XX_BIT_ALM0_EN;
 968         return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
 969 }
 970
 971 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
 972 {
 973         struct ds1307 *ds1307 = dev_get_drvdata(dev);
 974
 975         if (!test_bit(HAS_ALARM, &ds1307->flags))
 976                 return -EINVAL;
 977
 978         return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
 979                                   MCP794XX_BIT_ALM0_EN,
 980                                   enabled ? MCP794XX_BIT_ALM0_EN : 0);
 981 }
 982
 983 /*----------------------------------------------------------------------*/
 984
 985 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
 986                              size_t bytes)
 987 {
 988         struct ds1307 *ds1307 = priv;
 989         const struct chip_desc *chip = &chips[ds1307->type];
 990
 991         return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
 992                                 val, bytes);
 993 }
 994
 995 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
 996                               size_t bytes)
 997 {
 998         struct ds1307 *ds1307 = priv;
 999         const struct chip_desc *chip = &chips[ds1307->type];
1000
1001         return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
1002                                  val, bytes);
1003 }
1004
1005 /*----------------------------------------------------------------------*/
1006
1007 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307,
1008                                   u32 ohms, bool diode)
1009 {
1010         u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
1011                 DS1307_TRICKLE_CHARGER_NO_DIODE;
1012
1013         switch (ohms) {
1014         case 250:
1015                 setup |= DS1307_TRICKLE_CHARGER_250_OHM;
1016                 break;
1017         case 2000:
1018                 setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
1019                 break;
1020         case 4000:
1021                 setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
1022                 break;
1023         default:
1024                 dev_warn(ds1307->dev,
1025                          "Unsupported ohm value %u in dt\n", ohms);
1026                 return 0;
1027         }
1028         return setup;
1029 }
1030
1031 static u8 ds1307_trickle_init(struct ds1307 *ds1307,
1032                               const struct chip_desc *chip)
1033 {
1034         u32 ohms;
1035         bool diode = true;
1036
1037         if (!chip->do_trickle_setup)
1038                 return 0;
1039
1040         if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1041                                      &ohms))
1042                 return 0;
1043
1044         if (device_property_read_bool(ds1307->dev, "trickle-diode-disable"))
1045                 diode = false;
1046
1047         return chip->do_trickle_setup(ds1307, ohms, diode);
1048 }
1049
1050 /*----------------------------------------------------------------------*/
1051
1052 #if IS_REACHABLE(CONFIG_HWMON)
1053
1054 /*
1055  * Temperature sensor support for ds3231 devices.
1056  */
1057
1058 #define DS3231_REG_TEMPERATURE  0x11
1059
1060 /*
1061  * A user-initiated temperature conversion is not started by this function,
1062  * so the temperature is updated once every 64 seconds.
1063  */
1064 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
1065 {
1066         struct ds1307 *ds1307 = dev_get_drvdata(dev);
1067         u8 temp_buf[2];
1068         s16 temp;
1069         int ret;
1070
1071         ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1072                                temp_buf, sizeof(temp_buf));
1073         if (ret)
1074                 return ret;
1075         /*
1076          * Temperature is represented as a 10-bit code with a resolution of
1077          * 0.25 degree celsius and encoded in two's complement format.
1078          */
1079         temp = (temp_buf[0] << 8) | temp_buf[1];
1080         temp >>= 6;
1081         *mC = temp * 250;
1082
1083         return 0;
1084 }
1085
1086 static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1087                                       struct device_attribute *attr, char *buf)
1088 {
1089         int ret;
1090         s32 temp;
1091
1092         ret = ds3231_hwmon_read_temp(dev, &temp);
1093         if (ret)
1094                 return ret;
1095
1096         return sprintf(buf, "%d\n", temp);
1097 }
1098 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
1099                           NULL, 0);
1100
1101 static struct attribute *ds3231_hwmon_attrs[] = {
1102         &sensor_dev_attr_temp1_input.dev_attr.attr,
1103         NULL,
1104 };
1105 ATTRIBUTE_GROUPS(ds3231_hwmon);
1106
1107 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1108 {
1109         struct device *dev;
1110
1111         if (ds1307->type != ds_3231)
1112                 return;
1113
1114         dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1115                                                      ds1307,
1116                                                      ds3231_hwmon_groups);
1117         if (IS_ERR(dev)) {
1118                 dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1119                          PTR_ERR(dev));
1120         }
1121 }
1122
1123 #else
1124
1125 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1126 {
1127 }
1128
1129 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1130
1131 /*----------------------------------------------------------------------*/
1132
1133 /*
1134  * Square-wave output support for DS3231
1135  * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1136  */
1137 #ifdef CONFIG_COMMON_CLK
1138
1139 enum {
1140         DS3231_CLK_SQW = 0,
1141         DS3231_CLK_32KHZ,
1142 };
1143
1144 #define clk_sqw_to_ds1307(clk)  \
1145         container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1146 #define clk_32khz_to_ds1307(clk)        \
1147         container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1148
1149 static int ds3231_clk_sqw_rates[] = {
1150         1,
1151         1024,
1152         4096,
1153         8192,
1154 };
1155
1156 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1157 {
1158         struct mutex *lock = &ds1307->rtc->ops_lock;
1159         int ret;
1160
1161         mutex_lock(lock);
1162         ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1163                                  mask, value);
1164         mutex_unlock(lock);
1165
1166         return ret;
1167 }
1168
1169 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1170                                                 unsigned long parent_rate)
1171 {
1172         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1173         int control, ret;
1174         int rate_sel = 0;
1175
1176         ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1177         if (ret)
1178                 return ret;
1179         if (control & DS1337_BIT_RS1)
1180                 rate_sel += 1;
1181         if (control & DS1337_BIT_RS2)
1182                 rate_sel += 2;
1183
1184         return ds3231_clk_sqw_rates[rate_sel];
1185 }
1186
1187 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1188                                       unsigned long *prate)
1189 {
1190         int i;
1191
1192         for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1193                 if (ds3231_clk_sqw_rates[i] <= rate)
1194                         return ds3231_clk_sqw_rates[i];
1195         }
1196
1197         return 0;
1198 }
1199
1200 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1201                                    unsigned long parent_rate)
1202 {
1203         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1204         int control = 0;
1205         int rate_sel;
1206
1207         for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1208                         rate_sel++) {
1209                 if (ds3231_clk_sqw_rates[rate_sel] == rate)
1210                         break;
1211         }
1212
1213         if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1214                 return -EINVAL;
1215
1216         if (rate_sel & 1)
1217                 control |= DS1337_BIT_RS1;
1218         if (rate_sel & 2)
1219                 control |= DS1337_BIT_RS2;
1220
1221         return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1222                                 control);
1223 }
1224
1225 static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1226 {
1227         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1228
1229         return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1230 }
1231
1232 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1233 {
1234         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1235
1236         ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1237 }
1238
1239 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1240 {
1241         struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1242         int control, ret;
1243
1244         ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1245         if (ret)
1246                 return ret;
1247
1248         return !(control & DS1337_BIT_INTCN);
1249 }
1250
1251 static const struct clk_ops ds3231_clk_sqw_ops = {
1252         .prepare = ds3231_clk_sqw_prepare,
1253         .unprepare = ds3231_clk_sqw_unprepare,
1254         .is_prepared = ds3231_clk_sqw_is_prepared,
1255         .recalc_rate = ds3231_clk_sqw_recalc_rate,
1256         .round_rate = ds3231_clk_sqw_round_rate,
1257         .set_rate = ds3231_clk_sqw_set_rate,
1258 };
1259
1260 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1261                                                   unsigned long parent_rate)
1262 {
1263         return 32768;
1264 }
1265
1266 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1267 {
1268         struct mutex *lock = &ds1307->rtc->ops_lock;
1269         int ret;
1270
1271         mutex_lock(lock);
1272         ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1273                                  DS3231_BIT_EN32KHZ,
1274                                  enable ? DS3231_BIT_EN32KHZ : 0);
1275         mutex_unlock(lock);
1276
1277         return ret;
1278 }
1279
1280 static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1281 {
1282         struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1283
1284         return ds3231_clk_32khz_control(ds1307, true);
1285 }
1286
1287 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1288 {
1289         struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1290
1291         ds3231_clk_32khz_control(ds1307, false);
1292 }
1293
1294 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1295 {
1296         struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1297         int status, ret;
1298
1299         ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1300         if (ret)
1301                 return ret;
1302
1303         return !!(status & DS3231_BIT_EN32KHZ);
1304 }
1305
1306 static const struct clk_ops ds3231_clk_32khz_ops = {
1307         .prepare = ds3231_clk_32khz_prepare,
1308         .unprepare = ds3231_clk_32khz_unprepare,
1309         .is_prepared = ds3231_clk_32khz_is_prepared,
1310         .recalc_rate = ds3231_clk_32khz_recalc_rate,
1311 };
1312
1313 static struct clk_init_data ds3231_clks_init[] = {
1314         [DS3231_CLK_SQW] = {
1315                 .name = "ds3231_clk_sqw",
1316                 .ops = &ds3231_clk_sqw_ops,
1317         },
1318         [DS3231_CLK_32KHZ] = {
1319                 .name = "ds3231_clk_32khz",
1320                 .ops = &ds3231_clk_32khz_ops,
1321         },
1322 };
1323
1324 static int ds3231_clks_register(struct ds1307 *ds1307)
1325 {
1326         struct device_node *node = ds1307->dev->of_node;
1327         struct clk_onecell_data *onecell;
1328         int i;
1329
1330         onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1331         if (!onecell)
1332                 return -ENOMEM;
1333
1334         onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1335         onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1336                                      sizeof(onecell->clks[0]), GFP_KERNEL);
1337         if (!onecell->clks)
1338                 return -ENOMEM;
1339
1340         for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1341                 struct clk_init_data init = ds3231_clks_init[i];
1342
1343                 /*
1344                  * Interrupt signal due to alarm conditions and square-wave
1345                  * output share same pin, so don't initialize both.
1346                  */
1347                 if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
1348                         continue;
1349
1350                 /* optional override of the clockname */
1351                 of_property_read_string_index(node, "clock-output-names", i,
1352                                               &init.name);
1353                 ds1307->clks[i].init = &init;
1354
1355                 onecell->clks[i] = devm_clk_register(ds1307->dev,
1356                                                      &ds1307->clks[i]);
1357                 if (IS_ERR(onecell->clks[i]))
1358                         return PTR_ERR(onecell->clks[i]);
1359         }
1360
1361         if (!node)
1362                 return 0;
1363
1364         of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1365
1366         return 0;
1367 }
1368
1369 static void ds1307_clks_register(struct ds1307 *ds1307)
1370 {
1371         int ret;
1372
1373         if (ds1307->type != ds_3231)
1374                 return;
1375
1376         ret = ds3231_clks_register(ds1307);
1377         if (ret) {
1378                 dev_warn(ds1307->dev, "unable to register clock device %d\n",
1379                          ret);
1380         }
1381 }
1382
1383 #else
1384
1385 static void ds1307_clks_register(struct ds1307 *ds1307)
1386 {
1387 }
1388
1389 #endif /* CONFIG_COMMON_CLK */
1390
1391 static const struct regmap_config regmap_config = {
1392         .reg_bits = 8,
1393         .val_bits = 8,
1394 };
1395
1396 static int ds1307_probe(struct i2c_client *client,
1397                         const struct i2c_device_id *id)
1398 {
1399         struct ds1307           *ds1307;
1400         int                     err = -ENODEV;
1401         int                     tmp;
1402         const struct chip_desc  *chip;
1403         bool                    want_irq;
1404         bool                    ds1307_can_wakeup_device = false;
1405         unsigned char           regs[8];
1406         struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1407         u8                      trickle_charger_setup = 0;
1408
1409         ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1410         if (!ds1307)
1411                 return -ENOMEM;
1412
1413         dev_set_drvdata(&client->dev, ds1307);
1414         ds1307->dev = &client->dev;
1415         ds1307->name = client->name;
1416
1417         ds1307->regmap = devm_regmap_init_i2c(client, &regmap_config);
1418         if (IS_ERR(ds1307->regmap)) {
1419                 dev_err(ds1307->dev, "regmap allocation failed\n");
1420                 return PTR_ERR(ds1307->regmap);
1421         }
1422
1423         i2c_set_clientdata(client, ds1307);
1424
1425         if (client->dev.of_node) {
1426                 ds1307->type = (enum ds_type)
1427                         of_device_get_match_data(&client->dev);
1428                 chip = &chips[ds1307->type];
1429         } else if (id) {
1430                 chip = &chips[id->driver_data];
1431                 ds1307->type = id->driver_data;
1432         } else {
1433                 const struct acpi_device_id *acpi_id;
1434
1435                 acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
1436                                             ds1307->dev);
1437                 if (!acpi_id)
1438                         return -ENODEV;
1439                 chip = &chips[acpi_id->driver_data];
1440                 ds1307->type = acpi_id->driver_data;
1441         }
1442
1443         want_irq = client->irq > 0 && chip->alarm;
1444
1445         if (!pdata)
1446                 trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
1447         else if (pdata->trickle_charger_setup)
1448                 trickle_charger_setup = pdata->trickle_charger_setup;
1449
1450         if (trickle_charger_setup && chip->trickle_charger_reg) {
1451                 trickle_charger_setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
1452                 dev_dbg(ds1307->dev,
1453                         "writing trickle charger info 0x%x to 0x%x\n",
1454                         trickle_charger_setup, chip->trickle_charger_reg);
1455                 regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1456                              trickle_charger_setup);
1457         }
1458
1459 #ifdef CONFIG_OF
1460 /*
1461  * For devices with no IRQ directly connected to the SoC, the RTC chip
1462  * can be forced as a wakeup source by stating that explicitly in
1463  * the device's .dts file using the "wakeup-source" boolean property.
1464  * If the "wakeup-source" property is set, don't request an IRQ.
1465  * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1466  * if supported by the RTC.
1467  */
1468         if (chip->alarm && of_property_read_bool(client->dev.of_node,
1469                                                  "wakeup-source"))
1470                 ds1307_can_wakeup_device = true;
1471 #endif
1472
1473         switch (ds1307->type) {
1474         case ds_1337:
1475         case ds_1339:
1476         case ds_1341:
1477         case ds_3231:
1478                 /* get registers that the "rtc" read below won't read... */
1479                 err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1480                                        regs, 2);
1481                 if (err) {
1482                         dev_dbg(ds1307->dev, "read error %d\n", err);
1483                         goto exit;
1484                 }
1485
1486                 /* oscillator off?  turn it on, so clock can tick. */
1487                 if (regs[0] & DS1337_BIT_nEOSC)
1488                         regs[0] &= ~DS1337_BIT_nEOSC;
1489
1490                 /*
1491                  * Using IRQ or defined as wakeup-source?
1492                  * Disable the square wave and both alarms.
1493                  * For some variants, be sure alarms can trigger when we're
1494                  * running on Vbackup (BBSQI/BBSQW)
1495                  */
1496                 if (want_irq || ds1307_can_wakeup_device) {
1497                         regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1498                         regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1499                 }
1500
1501                 regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1502                              regs[0]);
1503
1504                 /* oscillator fault?  clear flag, and warn */
1505                 if (regs[1] & DS1337_BIT_OSF) {
1506                         regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1507                                      regs[1] & ~DS1337_BIT_OSF);
1508                         dev_warn(ds1307->dev, "SET TIME!\n");
1509                 }
1510                 break;
1511
1512         case rx_8025:
1513                 err = regmap_bulk_read(ds1307->regmap,
1514                                        RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
1515                 if (err) {
1516                         dev_dbg(ds1307->dev, "read error %d\n", err);
1517                         goto exit;
1518                 }
1519
1520                 /* oscillator off?  turn it on, so clock can tick. */
1521                 if (!(regs[1] & RX8025_BIT_XST)) {
1522                         regs[1] |= RX8025_BIT_XST;
1523                         regmap_write(ds1307->regmap,
1524                                      RX8025_REG_CTRL2 << 4 | 0x08,
1525                                      regs[1]);
1526                         dev_warn(ds1307->dev,
1527                                  "oscillator stop detected - SET TIME!\n");
1528                 }
1529
1530                 if (regs[1] & RX8025_BIT_PON) {
1531                         regs[1] &= ~RX8025_BIT_PON;
1532                         regmap_write(ds1307->regmap,
1533                                      RX8025_REG_CTRL2 << 4 | 0x08,
1534                                      regs[1]);
1535                         dev_warn(ds1307->dev, "power-on detected\n");
1536                 }
1537
1538                 if (regs[1] & RX8025_BIT_VDET) {
1539                         regs[1] &= ~RX8025_BIT_VDET;
1540                         regmap_write(ds1307->regmap,
1541                                      RX8025_REG_CTRL2 << 4 | 0x08,
1542                                      regs[1]);
1543                         dev_warn(ds1307->dev, "voltage drop detected\n");
1544                 }
1545
1546                 /* make sure we are running in 24hour mode */
1547                 if (!(regs[0] & RX8025_BIT_2412)) {
1548                         u8 hour;
1549
1550                         /* switch to 24 hour mode */
1551                         regmap_write(ds1307->regmap,
1552                                      RX8025_REG_CTRL1 << 4 | 0x08,
1553                                      regs[0] | RX8025_BIT_2412);
1554
1555                         err = regmap_bulk_read(ds1307->regmap,
1556                                                RX8025_REG_CTRL1 << 4 | 0x08,
1557                                                regs, 2);
1558                         if (err) {
1559                                 dev_dbg(ds1307->dev, "read error %d\n", err);
1560                                 goto exit;
1561                         }
1562
1563                         /* correct hour */
1564                         hour = bcd2bin(regs[DS1307_REG_HOUR]);
1565                         if (hour == 12)
1566                                 hour = 0;
1567                         if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1568                                 hour += 12;
1569
1570                         regmap_write(ds1307->regmap,
1571                                      DS1307_REG_HOUR << 4 | 0x08, hour);
1572                 }
1573                 break;
1574         default:
1575                 break;
1576         }
1577
1578 read_rtc:
1579         /* read RTC registers */
1580         err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1581                                sizeof(regs));
1582         if (err) {
1583                 dev_dbg(ds1307->dev, "read error %d\n", err);
1584                 goto exit;
1585         }
1586
1587         /*
1588          * minimal sanity checking; some chips (like DS1340) don't
1589          * specify the extra bits as must-be-zero, but there are
1590          * still a few values that are clearly out-of-range.
1591          */
1592         tmp = regs[DS1307_REG_SECS];
1593         switch (ds1307->type) {
1594         case ds_1307:
1595         case m41t0:
1596         case m41t00:
1597         case m41t11:
1598                 /* clock halted?  turn it on, so clock can tick. */
1599                 if (tmp & DS1307_BIT_CH) {
1600                         regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1601                         dev_warn(ds1307->dev, "SET TIME!\n");
1602                         goto read_rtc;
1603                 }
1604                 break;
1605         case ds_1308:
1606         case ds_1338:
1607                 /* clock halted?  turn it on, so clock can tick. */
1608                 if (tmp & DS1307_BIT_CH)
1609                         regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1610
1611                 /* oscillator fault?  clear flag, and warn */
1612                 if (regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
1613                         regmap_write(ds1307->regmap, DS1307_REG_CONTROL,
1614                                      regs[DS1307_REG_CONTROL] &
1615                                      ~DS1338_BIT_OSF);
1616                         dev_warn(ds1307->dev, "SET TIME!\n");
1617                         goto read_rtc;
1618                 }
1619                 break;
1620         case ds_1340:
1621                 /* clock halted?  turn it on, so clock can tick. */
1622                 if (tmp & DS1340_BIT_nEOSC)
1623                         regmap_write(ds1307->regmap, DS1307_REG_SECS, 0);
1624
1625                 err = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
1626                 if (err) {
1627                         dev_dbg(ds1307->dev, "read error %d\n", err);
1628                         goto exit;
1629                 }
1630
1631                 /* oscillator fault?  clear flag, and warn */
1632                 if (tmp & DS1340_BIT_OSF) {
1633                         regmap_write(ds1307->regmap, DS1340_REG_FLAG, 0);
1634                         dev_warn(ds1307->dev, "SET TIME!\n");
1635                 }
1636                 break;
1637         case mcp794xx:
1638                 /* make sure that the backup battery is enabled */
1639                 if (!(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1640                         regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1641                                      regs[DS1307_REG_WDAY] |
1642                                      MCP794XX_BIT_VBATEN);
1643                 }
1644
1645                 /* clock halted?  turn it on, so clock can tick. */
1646                 if (!(tmp & MCP794XX_BIT_ST)) {
1647                         regmap_write(ds1307->regmap, DS1307_REG_SECS,
1648                                      MCP794XX_BIT_ST);
1649                         dev_warn(ds1307->dev, "SET TIME!\n");
1650                         goto read_rtc;
1651                 }
1652
1653                 break;
1654         default:
1655                 break;
1656         }
1657
1658         tmp = regs[DS1307_REG_HOUR];
1659         switch (ds1307->type) {
1660         case ds_1340:
1661         case m41t0:
1662         case m41t00:
1663         case m41t11:
1664                 /*
1665                  * NOTE: ignores century bits; fix before deploying
1666                  * systems that will run through year 2100.
1667                  */
1668                 break;
1669         case rx_8025:
1670                 break;
1671         default:
1672                 if (!(tmp & DS1307_BIT_12HR))
1673                         break;
1674
1675                 /*
1676                  * Be sure we're in 24 hour mode.  Multi-master systems
1677                  * take note...
1678                  */
1679                 tmp = bcd2bin(tmp & 0x1f);
1680                 if (tmp == 12)
1681                         tmp = 0;
1682                 if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1683                         tmp += 12;
1684                 regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
1685                              bin2bcd(tmp));
1686         }
1687
1688         if (want_irq || ds1307_can_wakeup_device) {
1689                 device_set_wakeup_capable(ds1307->dev, true);
1690                 set_bit(HAS_ALARM, &ds1307->flags);
1691         }
1692
1693         ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
1694         if (IS_ERR(ds1307->rtc))
1695                 return PTR_ERR(ds1307->rtc);
1696
1697         if (ds1307_can_wakeup_device && !want_irq) {
1698                 dev_info(ds1307->dev,
1699                          "'wakeup-source' is set, request for an IRQ is disabled!\n");
1700                 /* We cannot support UIE mode if we do not have an IRQ line */
1701                 ds1307->rtc->uie_unsupported = 1;
1702         }
1703
1704         if (want_irq) {
1705                 err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1706                                                 chip->irq_handler ?: ds1307_irq,
1707                                                 IRQF_SHARED | IRQF_ONESHOT,
1708                                                 ds1307->name, ds1307);
1709                 if (err) {
1710                         client->irq = 0;
1711                         device_set_wakeup_capable(ds1307->dev, false);
1712                         clear_bit(HAS_ALARM, &ds1307->flags);
1713                         dev_err(ds1307->dev, "unable to request IRQ!\n");
1714                 } else {
1715                         dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
1716                 }
1717         }
1718
1719         ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
1720         err = rtc_register_device(ds1307->rtc);
1721         if (err)
1722                 return err;
1723
1724         if (chip->nvram_size) {
1725                 struct nvmem_config nvmem_cfg = {
1726                         .name = "ds1307_nvram",
1727                         .word_size = 1,
1728                         .stride = 1,
1729                         .size = chip->nvram_size,
1730                         .reg_read = ds1307_nvram_read,
1731                         .reg_write = ds1307_nvram_write,
1732                         .priv = ds1307,
1733                 };
1734
1735                 ds1307->rtc->nvram_old_abi = true;
1736                 rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
1737         }
1738
1739         ds1307_hwmon_register(ds1307);
1740         ds1307_clks_register(ds1307);
1741
1742         return 0;
1743
1744 exit:
1745         return err;
1746 }
1747
1748 static struct i2c_driver ds1307_driver = {
1749         .driver = {
1750                 .name   = "rtc-ds1307",
1751                 .of_match_table = of_match_ptr(ds1307_of_match),
1752                 .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
1753         },
1754         .probe          = ds1307_probe,
1755         .id_table       = ds1307_id,
1756 };
1757
1758 module_i2c_driver(ds1307_driver);
1759
1760 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
1761 MODULE_LICENSE("GPL");