1 Rockchip specific extensions to the Synopsys Designware MIPI DSI
2 ================================
5 - #address-cells: Should be <1>.
6 - #size-cells: Should be <0>.
7 - compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
8 "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
9 - reg: Represent the physical address range of the controller.
10 - interrupts: Represent the controller's interrupt to the CPU(s).
11 - clocks, clock-names: Phandles to the controller's pll reference
12 clock(ref) and APB clock(pclk). For RK3399, a phy config clock
13 (phy_cfg) and a grf clock(grf) are required. As described in [1].
14 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
15 - ports: contain a port node with endpoint definitions as defined in [2].
16 For vopb,set the reg = <0> and set the reg = <1> for vopl.
19 - power-domains: a phandle to mipi dsi power domain node.
20 - resets: list of phandle + reset specifier pairs, as described in [3].
21 - reset-names: string reset name, must be "apb".
23 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
24 [2] Documentation/devicetree/bindings/media/video-interfaces.txt
25 [3] Documentation/devicetree/bindings/reset/reset.txt
28 mipi_dsi: mipi@ff960000 {
31 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
32 reg = <0xff960000 0x4000>;
33 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
34 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
35 clock-names = "ref", "pclk";
36 resets = <&cru SRST_MIPIDSI0>;
38 rockchip,grf = <&grf>;
48 mipi_in_vopb: endpoint@0 {
50 remote-endpoint = <&vopb_out_mipi>;
52 mipi_in_vopl: endpoint@1 {
54 remote-endpoint = <&vopl_out_mipi>;
60 compatible ="boe,tv080wum-nl0";
63 enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
64 pinctrl-names = "default";
65 pinctrl-0 = <&lcd_en>;
66 backlight = <&backlight>;