1 // SPDX-License-Identifier: GPL-2.0-only
3 * SMP initialisation and IPI support
4 * Based on arch/arm64/kernel/smp.c
6 * Copyright (C) 2012 ARM Ltd.
7 * Copyright (C) 2015 Regents of the University of California
8 * Copyright (C) 2017 SiFive
11 #include <linux/cpu.h>
12 #include <linux/clockchips.h>
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/kexec.h>
16 #include <linux/profile.h>
17 #include <linux/smp.h>
18 #include <linux/sched.h>
19 #include <linux/seq_file.h>
20 #include <linux/delay.h>
21 #include <linux/irq_work.h>
24 #include <asm/tlbflush.h>
25 #include <asm/cacheflush.h>
26 #include <asm/cpu_ops.h>
28 enum ipi_message_type {
38 unsigned long __cpuid_to_hartid_map[NR_CPUS] __ro_after_init = {
39 [0 ... NR_CPUS-1] = INVALID_HARTID
42 void __init smp_setup_processor_id(void)
44 cpuid_to_hartid_map(0) = boot_cpu_hartid;
47 /* A collection of single bit ipi messages. */
49 unsigned long stats[IPI_MAX] ____cacheline_aligned;
50 unsigned long bits ____cacheline_aligned;
51 } ipi_data[NR_CPUS] __cacheline_aligned;
53 int riscv_hartid_to_cpuid(unsigned long hartid)
57 for (i = 0; i < NR_CPUS; i++)
58 if (cpuid_to_hartid_map(i) == hartid)
64 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
66 return phys_id == cpuid_to_hartid_map(cpu);
69 static void ipi_stop(void)
71 set_cpu_online(smp_processor_id(), false);
76 #ifdef CONFIG_KEXEC_CORE
77 static atomic_t waiting_for_crash_ipi = ATOMIC_INIT(0);
79 static inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
81 crash_save_cpu(regs, cpu);
83 atomic_dec(&waiting_for_crash_ipi);
87 #ifdef CONFIG_HOTPLUG_CPU
88 if (cpu_has_hotplug(cpu))
89 cpu_ops[cpu]->cpu_stop();
96 static inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs)
102 static const struct riscv_ipi_ops *ipi_ops __ro_after_init;
104 void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops)
108 EXPORT_SYMBOL_GPL(riscv_set_ipi_ops);
110 void riscv_clear_ipi(void)
112 if (ipi_ops && ipi_ops->ipi_clear)
113 ipi_ops->ipi_clear();
115 csr_clear(CSR_IP, IE_SIE);
117 EXPORT_SYMBOL_GPL(riscv_clear_ipi);
119 static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op)
123 smp_mb__before_atomic();
124 for_each_cpu(cpu, mask)
125 set_bit(op, &ipi_data[cpu].bits);
126 smp_mb__after_atomic();
128 if (ipi_ops && ipi_ops->ipi_inject)
129 ipi_ops->ipi_inject(mask);
131 pr_warn("SMP: IPI inject method not available\n");
134 static void send_ipi_single(int cpu, enum ipi_message_type op)
136 smp_mb__before_atomic();
137 set_bit(op, &ipi_data[cpu].bits);
138 smp_mb__after_atomic();
140 if (ipi_ops && ipi_ops->ipi_inject)
141 ipi_ops->ipi_inject(cpumask_of(cpu));
143 pr_warn("SMP: IPI inject method not available\n");
146 #ifdef CONFIG_IRQ_WORK
147 void arch_irq_work_raise(void)
149 send_ipi_single(smp_processor_id(), IPI_IRQ_WORK);
153 void handle_IPI(struct pt_regs *regs)
155 unsigned int cpu = smp_processor_id();
156 unsigned long *pending_ipis = &ipi_data[cpu].bits;
157 unsigned long *stats = ipi_data[cpu].stats;
164 /* Order bit clearing and data access. */
167 ops = xchg(pending_ipis, 0);
171 if (ops & (1 << IPI_RESCHEDULE)) {
172 stats[IPI_RESCHEDULE]++;
176 if (ops & (1 << IPI_CALL_FUNC)) {
177 stats[IPI_CALL_FUNC]++;
178 generic_smp_call_function_interrupt();
181 if (ops & (1 << IPI_CPU_STOP)) {
182 stats[IPI_CPU_STOP]++;
186 if (ops & (1 << IPI_CPU_CRASH_STOP)) {
187 ipi_cpu_crash_stop(cpu, get_irq_regs());
190 if (ops & (1 << IPI_IRQ_WORK)) {
191 stats[IPI_IRQ_WORK]++;
195 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
196 if (ops & (1 << IPI_TIMER)) {
198 tick_receive_broadcast();
201 BUG_ON((ops >> IPI_MAX) != 0);
203 /* Order data access and bit testing. */
208 static const char * const ipi_names[] = {
209 [IPI_RESCHEDULE] = "Rescheduling interrupts",
210 [IPI_CALL_FUNC] = "Function call interrupts",
211 [IPI_CPU_STOP] = "CPU stop interrupts",
212 [IPI_CPU_CRASH_STOP] = "CPU stop (for crash dump) interrupts",
213 [IPI_IRQ_WORK] = "IRQ work interrupts",
214 [IPI_TIMER] = "Timer broadcast interrupts",
217 void show_ipi_stats(struct seq_file *p, int prec)
221 for (i = 0; i < IPI_MAX; i++) {
222 seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i,
223 prec >= 4 ? " " : "");
224 for_each_online_cpu(cpu)
225 seq_printf(p, "%10lu ", ipi_data[cpu].stats[i]);
226 seq_printf(p, " %s\n", ipi_names[i]);
230 void arch_send_call_function_ipi_mask(struct cpumask *mask)
232 send_ipi_mask(mask, IPI_CALL_FUNC);
235 void arch_send_call_function_single_ipi(int cpu)
237 send_ipi_single(cpu, IPI_CALL_FUNC);
240 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
241 void tick_broadcast(const struct cpumask *mask)
243 send_ipi_mask(mask, IPI_TIMER);
247 void smp_send_stop(void)
249 unsigned long timeout;
251 if (num_online_cpus() > 1) {
254 cpumask_copy(&mask, cpu_online_mask);
255 cpumask_clear_cpu(smp_processor_id(), &mask);
257 if (system_state <= SYSTEM_RUNNING)
258 pr_crit("SMP: stopping secondary CPUs\n");
259 send_ipi_mask(&mask, IPI_CPU_STOP);
262 /* Wait up to one second for other CPUs to stop */
263 timeout = USEC_PER_SEC;
264 while (num_online_cpus() > 1 && timeout--)
267 if (num_online_cpus() > 1)
268 pr_warn("SMP: failed to stop secondary CPUs %*pbl\n",
269 cpumask_pr_args(cpu_online_mask));
272 #ifdef CONFIG_KEXEC_CORE
274 * The number of CPUs online, not counting this CPU (which may not be
275 * fully online and so not counted in num_online_cpus()).
277 static inline unsigned int num_other_online_cpus(void)
279 unsigned int this_cpu_online = cpu_online(smp_processor_id());
281 return num_online_cpus() - this_cpu_online;
284 void crash_smp_send_stop(void)
286 static int cpus_stopped;
288 unsigned long timeout;
291 * This function can be called twice in panic path, but obviously
292 * we execute this only once.
300 * If this cpu is the only one alive at this point in time, online or
301 * not, there are no stop messages to be sent around, so just back out.
303 if (num_other_online_cpus() == 0)
306 cpumask_copy(&mask, cpu_online_mask);
307 cpumask_clear_cpu(smp_processor_id(), &mask);
309 atomic_set(&waiting_for_crash_ipi, num_other_online_cpus());
311 pr_crit("SMP: stopping secondary CPUs\n");
312 send_ipi_mask(&mask, IPI_CPU_CRASH_STOP);
314 /* Wait up to one second for other CPUs to stop */
315 timeout = USEC_PER_SEC;
316 while ((atomic_read(&waiting_for_crash_ipi) > 0) && timeout--)
319 if (atomic_read(&waiting_for_crash_ipi) > 0)
320 pr_warn("SMP: failed to stop secondary CPUs %*pbl\n",
321 cpumask_pr_args(&mask));
324 bool smp_crash_stop_failed(void)
326 return (atomic_read(&waiting_for_crash_ipi) > 0);
330 void smp_send_reschedule(int cpu)
332 send_ipi_single(cpu, IPI_RESCHEDULE);
334 EXPORT_SYMBOL_GPL(smp_send_reschedule);