1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/serial/renesas,sci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Serial Communication Interface
10 - Geert Uytterhoeven <geert+renesas@glider.be>
20 - renesas,r9a07g043-sci # RZ/G2UL and RZ/Five
21 - renesas,r9a07g044-sci # RZ/G2{L,LC}
22 - renesas,r9a07g054-sci # RZ/V2L
23 - const: renesas,sci # generic SCI compatible UART
26 - const: renesas,sci # generic SCI compatible UART
33 - description: Error interrupt
34 - description: Receive buffer full interrupt
35 - description: Transmit buffer empty interrupt
36 - description: Transmit end interrupt
54 - fck # UART functional clock
55 - sck # optional external clock input
57 uart-has-rtscts: false
71 - renesas,r9a07g043-sci
72 - renesas,r9a07g044-sci
73 - renesas,r9a07g054-sci
86 unevaluatedProperties: false
90 #include <dt-bindings/clock/r9a07g044-cpg.h>
91 #include <dt-bindings/interrupt-controller/arm-gic.h>
97 sci0: serial@1004d000 {
98 compatible = "renesas,r9a07g044-sci", "renesas,sci";
99 reg = <0x1004d000 0x400>;
100 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
104 interrupt-names = "eri", "rxi", "txi", "tei";
105 clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
107 power-domains = <&cpg>;
108 resets = <&cpg R9A07G044_SCI0_RST>;