1 * Renesas Electronics Ethernet AVB
3 This file provides information on what the device node for the Ethernet AVB
7 - compatible: "renesas,etheravb-r8a7790" if the device is a part of R8A7790 SoC.
8 "renesas,etheravb-r8a7794" if the device is a part of R8A7794 SoC.
9 "renesas,etheravb-r8a7795" if the device is a part of R8A7795 SoC.
10 - reg: offset and length of (1) the register block and (2) the stream buffer.
11 - interrupts: A list of interrupt-specifiers, one for each entry in
13 If interrupt-names is not present, an interrupt specifier
14 for a single muxed interrupt.
15 - phy-mode: see ethernet.txt file in the same directory.
16 - phy-handle: see ethernet.txt file in the same directory.
17 - #address-cells: number of address cells for the MDIO bus, must be equal to 1.
18 - #size-cells: number of size cells on the MDIO bus, must be equal to 0.
19 - clocks: clock phandle and specifier pair.
20 - pinctrl-0: phandle, referring to a default pin configuration node.
23 - interrupt-parent: the phandle for the interrupt controller that services
24 interrupts for this device.
25 - interrupt-names: A list of interrupt names.
26 For the R8A7795 SoC this property is mandatory;
27 it should include one entry per channel, named "ch%u",
28 where %u is the channel number ranging from 0 to 24.
29 For other SoCs this property is optional; if present
30 it should contain "mux" for a single muxed interrupt.
31 - pinctrl-names: pin configuration state name ("default").
32 - renesas,no-ether-link: boolean, specify when a board does not provide a proper
34 - renesas,ether-link-active-low: boolean, specify when the AVB_LINK signal is
35 active-low instead of normal active-high.
40 compatible = "renesas,etheravb-r8a7795";
41 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
42 interrupt-parent = <&gic>;
43 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
44 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
48 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
49 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
50 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
51 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
52 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
53 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
54 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
55 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
56 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
57 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
58 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
59 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
68 interrupt-names = "ch0", "ch1", "ch2", "ch3",
69 "ch4", "ch5", "ch6", "ch7",
70 "ch8", "ch9", "ch10", "ch11",
71 "ch12", "ch13", "ch14", "ch15",
72 "ch16", "ch17", "ch18", "ch19",
73 "ch20", "ch21", "ch22", "ch23",
75 clocks = <&mstp8_clks R8A7795_CLK_ETHERAVB>;
76 power-domains = <&cpg_clocks>;
77 phy-mode = "rgmii-id";
80 pinctrl-0 = <ðer_pins>;
81 pinctrl-names = "default";
82 renesas,no-ether-link;
86 phy0: ethernet-phy@0 {
100 interrupt-parent = <&gpio2>;
101 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;