1 // SPDX-License-Identifier: GPL-2.0-only
3 * Qualcomm ADSP/SLPI Peripheral Image Loader for MSM8974 and MSM8996
5 * Copyright (C) 2016 Linaro Ltd
6 * Copyright (C) 2014 Sony Mobile Communications AB
7 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
10 #include <linux/clk.h>
11 #include <linux/firmware.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_domain.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/qcom_scm.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/remoteproc.h>
23 #include <linux/soc/qcom/mdt_loader.h>
24 #include <linux/soc/qcom/smem.h>
25 #include <linux/soc/qcom/smem_state.h>
27 #include "qcom_common.h"
28 #include "qcom_pil_info.h"
29 #include "qcom_q6v5.h"
30 #include "remoteproc_internal.h"
33 int crash_reason_smem;
34 const char *firmware_name;
39 char **active_pd_names;
40 char **proxy_pd_names;
43 const char *sysmon_name;
51 struct qcom_q6v5 q6v5;
54 struct clk *aggre2_clk;
56 struct regulator *cx_supply;
57 struct regulator *px_supply;
59 struct device *active_pds[1];
60 struct device *proxy_pds[3];
66 int crash_reason_smem;
68 const char *info_name;
70 struct completion start_done;
71 struct completion stop_done;
74 phys_addr_t mem_reloc;
78 struct qcom_rproc_glink glink_subdev;
79 struct qcom_rproc_subdev smd_subdev;
80 struct qcom_rproc_ssr ssr_subdev;
81 struct qcom_sysmon *sysmon;
84 static int adsp_pds_enable(struct qcom_adsp *adsp, struct device **pds,
90 for (i = 0; i < pd_count; i++) {
91 dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
92 ret = pm_runtime_get_sync(pds[i]);
94 pm_runtime_put_noidle(pds[i]);
95 dev_pm_genpd_set_performance_state(pds[i], 0);
103 for (i--; i >= 0; i--) {
104 dev_pm_genpd_set_performance_state(pds[i], 0);
105 pm_runtime_put(pds[i]);
111 static void adsp_pds_disable(struct qcom_adsp *adsp, struct device **pds,
116 for (i = 0; i < pd_count; i++) {
117 dev_pm_genpd_set_performance_state(pds[i], 0);
118 pm_runtime_put(pds[i]);
122 static int adsp_load(struct rproc *rproc, const struct firmware *fw)
124 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
127 ret = qcom_mdt_load(adsp->dev, fw, rproc->firmware, adsp->pas_id,
128 adsp->mem_region, adsp->mem_phys, adsp->mem_size,
133 qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size);
138 static int adsp_start(struct rproc *rproc)
140 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
143 qcom_q6v5_prepare(&adsp->q6v5);
145 ret = adsp_pds_enable(adsp, adsp->active_pds, adsp->active_pd_count);
149 ret = adsp_pds_enable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
151 goto disable_active_pds;
153 ret = clk_prepare_enable(adsp->xo);
155 goto disable_proxy_pds;
157 ret = clk_prepare_enable(adsp->aggre2_clk);
161 ret = regulator_enable(adsp->cx_supply);
163 goto disable_aggre2_clk;
165 ret = regulator_enable(adsp->px_supply);
167 goto disable_cx_supply;
169 ret = qcom_scm_pas_auth_and_reset(adsp->pas_id);
172 "failed to authenticate image and release reset\n");
173 goto disable_px_supply;
176 ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5000));
177 if (ret == -ETIMEDOUT) {
178 dev_err(adsp->dev, "start timed out\n");
179 qcom_scm_pas_shutdown(adsp->pas_id);
180 goto disable_px_supply;
186 regulator_disable(adsp->px_supply);
188 regulator_disable(adsp->cx_supply);
190 clk_disable_unprepare(adsp->aggre2_clk);
192 clk_disable_unprepare(adsp->xo);
194 adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
196 adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count);
198 qcom_q6v5_unprepare(&adsp->q6v5);
203 static void qcom_pas_handover(struct qcom_q6v5 *q6v5)
205 struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5);
207 regulator_disable(adsp->px_supply);
208 regulator_disable(adsp->cx_supply);
209 clk_disable_unprepare(adsp->aggre2_clk);
210 clk_disable_unprepare(adsp->xo);
211 adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
214 static int adsp_stop(struct rproc *rproc)
216 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
220 ret = qcom_q6v5_request_stop(&adsp->q6v5);
221 if (ret == -ETIMEDOUT)
222 dev_err(adsp->dev, "timed out on wait\n");
224 ret = qcom_scm_pas_shutdown(adsp->pas_id);
226 dev_err(adsp->dev, "failed to shutdown: %d\n", ret);
228 adsp_pds_disable(adsp, adsp->active_pds, adsp->active_pd_count);
229 handover = qcom_q6v5_unprepare(&adsp->q6v5);
231 qcom_pas_handover(&adsp->q6v5);
236 static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len)
238 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
241 offset = da - adsp->mem_reloc;
242 if (offset < 0 || offset + len > adsp->mem_size)
245 return adsp->mem_region + offset;
248 static unsigned long adsp_panic(struct rproc *rproc)
250 struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
252 return qcom_q6v5_panic(&adsp->q6v5);
255 static const struct rproc_ops adsp_ops = {
258 .da_to_va = adsp_da_to_va,
259 .parse_fw = qcom_register_dump_segments,
264 static int adsp_init_clock(struct qcom_adsp *adsp)
268 adsp->xo = devm_clk_get(adsp->dev, "xo");
269 if (IS_ERR(adsp->xo)) {
270 ret = PTR_ERR(adsp->xo);
271 if (ret != -EPROBE_DEFER)
272 dev_err(adsp->dev, "failed to get xo clock");
276 if (adsp->has_aggre2_clk) {
277 adsp->aggre2_clk = devm_clk_get(adsp->dev, "aggre2");
278 if (IS_ERR(adsp->aggre2_clk)) {
279 ret = PTR_ERR(adsp->aggre2_clk);
280 if (ret != -EPROBE_DEFER)
282 "failed to get aggre2 clock");
290 static int adsp_init_regulator(struct qcom_adsp *adsp)
292 adsp->cx_supply = devm_regulator_get(adsp->dev, "cx");
293 if (IS_ERR(adsp->cx_supply))
294 return PTR_ERR(adsp->cx_supply);
296 regulator_set_load(adsp->cx_supply, 100000);
298 adsp->px_supply = devm_regulator_get(adsp->dev, "px");
299 return PTR_ERR_OR_ZERO(adsp->px_supply);
302 static int adsp_pds_attach(struct device *dev, struct device **devs,
312 /* Handle single power domain */
313 if (dev->pm_domain) {
315 pm_runtime_enable(dev);
319 while (pd_names[num_pds])
322 for (i = 0; i < num_pds; i++) {
323 devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
324 if (IS_ERR_OR_NULL(devs[i])) {
325 ret = PTR_ERR(devs[i]) ? : -ENODATA;
333 for (i--; i >= 0; i--)
334 dev_pm_domain_detach(devs[i], false);
339 static void adsp_pds_detach(struct qcom_adsp *adsp, struct device **pds,
342 struct device *dev = adsp->dev;
345 /* Handle single power domain */
346 if (dev->pm_domain && pd_count) {
347 pm_runtime_disable(dev);
351 for (i = 0; i < pd_count; i++)
352 dev_pm_domain_detach(pds[i], false);
355 static int adsp_alloc_memory_region(struct qcom_adsp *adsp)
357 struct device_node *node;
361 node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0);
363 dev_err(adsp->dev, "no memory-region specified\n");
367 ret = of_address_to_resource(node, 0, &r);
371 adsp->mem_phys = adsp->mem_reloc = r.start;
372 adsp->mem_size = resource_size(&r);
373 adsp->mem_region = devm_ioremap_wc(adsp->dev, adsp->mem_phys, adsp->mem_size);
374 if (!adsp->mem_region) {
375 dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n",
376 &r.start, adsp->mem_size);
383 static int adsp_probe(struct platform_device *pdev)
385 const struct adsp_data *desc;
386 struct qcom_adsp *adsp;
391 desc = of_device_get_match_data(&pdev->dev);
395 if (!qcom_scm_is_available())
396 return -EPROBE_DEFER;
398 fw_name = desc->firmware_name;
399 ret = of_property_read_string(pdev->dev.of_node, "firmware-name",
401 if (ret < 0 && ret != -EINVAL)
404 rproc = rproc_alloc(&pdev->dev, pdev->name, &adsp_ops,
405 fw_name, sizeof(*adsp));
407 dev_err(&pdev->dev, "unable to allocate remoteproc\n");
411 rproc->auto_boot = desc->auto_boot;
412 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
414 adsp = (struct qcom_adsp *)rproc->priv;
415 adsp->dev = &pdev->dev;
417 adsp->pas_id = desc->pas_id;
418 adsp->has_aggre2_clk = desc->has_aggre2_clk;
419 adsp->info_name = desc->sysmon_name;
420 platform_set_drvdata(pdev, adsp);
422 device_wakeup_enable(adsp->dev);
424 ret = adsp_alloc_memory_region(adsp);
428 ret = adsp_init_clock(adsp);
432 ret = adsp_init_regulator(adsp);
436 ret = adsp_pds_attach(&pdev->dev, adsp->active_pds,
437 desc->active_pd_names);
440 adsp->active_pd_count = ret;
442 ret = adsp_pds_attach(&pdev->dev, adsp->proxy_pds,
443 desc->proxy_pd_names);
445 goto detach_active_pds;
446 adsp->proxy_pd_count = ret;
448 ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,
451 goto detach_proxy_pds;
453 qcom_add_glink_subdev(rproc, &adsp->glink_subdev, desc->ssr_name);
454 qcom_add_smd_subdev(rproc, &adsp->smd_subdev);
455 qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name);
456 adsp->sysmon = qcom_add_sysmon_subdev(rproc,
459 if (IS_ERR(adsp->sysmon)) {
460 ret = PTR_ERR(adsp->sysmon);
461 goto detach_proxy_pds;
464 ret = rproc_add(rproc);
466 goto detach_proxy_pds;
471 adsp_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count);
473 adsp_pds_detach(adsp, adsp->active_pds, adsp->active_pd_count);
480 static int adsp_remove(struct platform_device *pdev)
482 struct qcom_adsp *adsp = platform_get_drvdata(pdev);
484 rproc_del(adsp->rproc);
486 qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);
487 qcom_remove_sysmon_subdev(adsp->sysmon);
488 qcom_remove_smd_subdev(adsp->rproc, &adsp->smd_subdev);
489 qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);
490 rproc_free(adsp->rproc);
495 static const struct adsp_data adsp_resource_init = {
496 .crash_reason_smem = 423,
497 .firmware_name = "/*(DEBLOBBED)*/",
499 .has_aggre2_clk = false,
502 .sysmon_name = "adsp",
506 static const struct adsp_data sm8150_adsp_resource = {
507 .crash_reason_smem = 423,
508 .firmware_name = "/*(DEBLOBBED)*/",
510 .has_aggre2_clk = false,
512 .active_pd_names = (char*[]){
516 .proxy_pd_names = (char*[]){
521 .sysmon_name = "adsp",
525 static const struct adsp_data sm8250_adsp_resource = {
526 .crash_reason_smem = 423,
527 .firmware_name = "/*(DEBLOBBED)*/",
529 .has_aggre2_clk = false,
531 .active_pd_names = (char*[]){
535 .proxy_pd_names = (char*[]){
541 .sysmon_name = "adsp",
545 static const struct adsp_data msm8998_adsp_resource = {
546 .crash_reason_smem = 423,
547 .firmware_name = "/*(DEBLOBBED)*/",
549 .has_aggre2_clk = false,
551 .proxy_pd_names = (char*[]){
556 .sysmon_name = "adsp",
560 static const struct adsp_data cdsp_resource_init = {
561 .crash_reason_smem = 601,
562 .firmware_name = "/*(DEBLOBBED)*/",
564 .has_aggre2_clk = false,
567 .sysmon_name = "cdsp",
571 static const struct adsp_data sm8150_cdsp_resource = {
572 .crash_reason_smem = 601,
573 .firmware_name = "/*(DEBLOBBED)*/",
575 .has_aggre2_clk = false,
577 .active_pd_names = (char*[]){
581 .proxy_pd_names = (char*[]){
586 .sysmon_name = "cdsp",
590 static const struct adsp_data sm8250_cdsp_resource = {
591 .crash_reason_smem = 601,
592 .firmware_name = "/*(DEBLOBBED)*/",
594 .has_aggre2_clk = false,
596 .active_pd_names = (char*[]){
600 .proxy_pd_names = (char*[]){
605 .sysmon_name = "cdsp",
609 static const struct adsp_data mpss_resource_init = {
610 .crash_reason_smem = 421,
611 .firmware_name = "/*(DEBLOBBED)*/",
613 .has_aggre2_clk = false,
615 .active_pd_names = (char*[]){
619 .proxy_pd_names = (char*[]){
625 .sysmon_name = "modem",
629 static const struct adsp_data slpi_resource_init = {
630 .crash_reason_smem = 424,
631 .firmware_name = "/*(DEBLOBBED)*/",
633 .has_aggre2_clk = true,
636 .sysmon_name = "slpi",
640 static const struct adsp_data sm8150_slpi_resource = {
641 .crash_reason_smem = 424,
642 .firmware_name = "/*(DEBLOBBED)*/",
644 .has_aggre2_clk = false,
646 .active_pd_names = (char*[]){
650 .proxy_pd_names = (char*[]){
656 .sysmon_name = "slpi",
660 static const struct adsp_data sm8250_slpi_resource = {
661 .crash_reason_smem = 424,
662 .firmware_name = "/*(DEBLOBBED)*/",
664 .has_aggre2_clk = false,
666 .active_pd_names = (char*[]){
670 .proxy_pd_names = (char*[]){
676 .sysmon_name = "slpi",
680 static const struct adsp_data msm8998_slpi_resource = {
681 .crash_reason_smem = 424,
682 .firmware_name = "/*(DEBLOBBED)*/",
684 .has_aggre2_clk = true,
686 .proxy_pd_names = (char*[]){
691 .sysmon_name = "slpi",
695 static const struct adsp_data wcss_resource_init = {
696 .crash_reason_smem = 421,
697 .firmware_name = "/*(DEBLOBBED)*/",
701 .sysmon_name = "wcnss",
705 static const struct of_device_id adsp_of_match[] = {
706 { .compatible = "qcom,msm8974-adsp-pil", .data = &adsp_resource_init},
707 { .compatible = "qcom,msm8996-adsp-pil", .data = &adsp_resource_init},
708 { .compatible = "qcom,msm8996-slpi-pil", .data = &slpi_resource_init},
709 { .compatible = "qcom,msm8998-adsp-pas", .data = &msm8998_adsp_resource},
710 { .compatible = "qcom,msm8998-slpi-pas", .data = &msm8998_slpi_resource},
711 { .compatible = "qcom,qcs404-adsp-pas", .data = &adsp_resource_init },
712 { .compatible = "qcom,qcs404-cdsp-pas", .data = &cdsp_resource_init },
713 { .compatible = "qcom,qcs404-wcss-pas", .data = &wcss_resource_init },
714 { .compatible = "qcom,sc7180-mpss-pas", .data = &mpss_resource_init},
715 { .compatible = "qcom,sdm845-adsp-pas", .data = &adsp_resource_init},
716 { .compatible = "qcom,sdm845-cdsp-pas", .data = &cdsp_resource_init},
717 { .compatible = "qcom,sm8150-adsp-pas", .data = &sm8150_adsp_resource},
718 { .compatible = "qcom,sm8150-cdsp-pas", .data = &sm8150_cdsp_resource},
719 { .compatible = "qcom,sm8150-mpss-pas", .data = &mpss_resource_init},
720 { .compatible = "qcom,sm8150-slpi-pas", .data = &sm8150_slpi_resource},
721 { .compatible = "qcom,sm8250-adsp-pas", .data = &sm8250_adsp_resource},
722 { .compatible = "qcom,sm8250-cdsp-pas", .data = &sm8250_cdsp_resource},
723 { .compatible = "qcom,sm8250-slpi-pas", .data = &sm8250_slpi_resource},
726 MODULE_DEVICE_TABLE(of, adsp_of_match);
728 static struct platform_driver adsp_driver = {
730 .remove = adsp_remove,
732 .name = "qcom_q6v5_pas",
733 .of_match_table = adsp_of_match,
737 module_platform_driver(adsp_driver);
738 MODULE_DESCRIPTION("Qualcomm Hexagon v5 Peripheral Authentication Service driver");
739 MODULE_LICENSE("GPL v2");