2 * Register map access API - MMIO support
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/clk.h>
20 #include <linux/err.h>
22 #include <linux/module.h>
23 #include <linux/regmap.h>
24 #include <linux/slab.h>
28 struct regmap_mmio_context {
33 void (*reg_write)(struct regmap_mmio_context *ctx,
34 unsigned int reg, unsigned int val);
35 unsigned int (*reg_read)(struct regmap_mmio_context *ctx,
39 static int regmap_mmio_regbits_check(size_t reg_bits)
54 static int regmap_mmio_get_min_stride(size_t val_bits)
60 /* The core treats 0 as 1 */
81 static void regmap_mmio_write8(struct regmap_mmio_context *ctx,
85 writeb(val, ctx->regs + reg);
88 static void regmap_mmio_write16le(struct regmap_mmio_context *ctx,
92 writew(val, ctx->regs + reg);
95 static void regmap_mmio_write16be(struct regmap_mmio_context *ctx,
99 iowrite16be(val, ctx->regs + reg);
102 static void regmap_mmio_write32le(struct regmap_mmio_context *ctx,
106 writel(val, ctx->regs + reg);
109 static void regmap_mmio_write32be(struct regmap_mmio_context *ctx,
113 iowrite32be(val, ctx->regs + reg);
117 static void regmap_mmio_write64le(struct regmap_mmio_context *ctx,
121 writeq(val, ctx->regs + reg);
125 static int regmap_mmio_write(void *context, unsigned int reg, unsigned int val)
127 struct regmap_mmio_context *ctx = context;
130 if (!IS_ERR(ctx->clk)) {
131 ret = clk_enable(ctx->clk);
136 ctx->reg_write(ctx, reg, val);
138 if (!IS_ERR(ctx->clk))
139 clk_disable(ctx->clk);
144 static unsigned int regmap_mmio_read8(struct regmap_mmio_context *ctx,
147 return readb(ctx->regs + reg);
150 static unsigned int regmap_mmio_read16le(struct regmap_mmio_context *ctx,
153 return readw(ctx->regs + reg);
156 static unsigned int regmap_mmio_read16be(struct regmap_mmio_context *ctx,
159 return ioread16be(ctx->regs + reg);
162 static unsigned int regmap_mmio_read32le(struct regmap_mmio_context *ctx,
165 return readl(ctx->regs + reg);
168 static unsigned int regmap_mmio_read32be(struct regmap_mmio_context *ctx,
171 return ioread32be(ctx->regs + reg);
175 static unsigned int regmap_mmio_read64le(struct regmap_mmio_context *ctx,
178 return readq(ctx->regs + reg);
182 static int regmap_mmio_read(void *context, unsigned int reg, unsigned int *val)
184 struct regmap_mmio_context *ctx = context;
187 if (!IS_ERR(ctx->clk)) {
188 ret = clk_enable(ctx->clk);
193 *val = ctx->reg_read(ctx, reg);
195 if (!IS_ERR(ctx->clk))
196 clk_disable(ctx->clk);
201 static void regmap_mmio_free_context(void *context)
203 struct regmap_mmio_context *ctx = context;
205 if (!IS_ERR(ctx->clk)) {
206 clk_unprepare(ctx->clk);
212 static const struct regmap_bus regmap_mmio = {
214 .reg_write = regmap_mmio_write,
215 .reg_read = regmap_mmio_read,
216 .free_context = regmap_mmio_free_context,
217 .val_format_endian_default = REGMAP_ENDIAN_LITTLE,
220 static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev,
223 const struct regmap_config *config)
225 struct regmap_mmio_context *ctx;
229 ret = regmap_mmio_regbits_check(config->reg_bits);
233 if (config->pad_bits)
234 return ERR_PTR(-EINVAL);
236 min_stride = regmap_mmio_get_min_stride(config->val_bits);
238 return ERR_PTR(min_stride);
240 if (config->reg_stride < min_stride)
241 return ERR_PTR(-EINVAL);
243 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
245 return ERR_PTR(-ENOMEM);
248 ctx->val_bytes = config->val_bits / 8;
249 ctx->clk = ERR_PTR(-ENODEV);
251 switch (regmap_get_val_endian(dev, ®map_mmio, config)) {
252 case REGMAP_ENDIAN_DEFAULT:
253 case REGMAP_ENDIAN_LITTLE:
254 #ifdef __LITTLE_ENDIAN
255 case REGMAP_ENDIAN_NATIVE:
257 switch (config->val_bits) {
259 ctx->reg_read = regmap_mmio_read8;
260 ctx->reg_write = regmap_mmio_write8;
263 ctx->reg_read = regmap_mmio_read16le;
264 ctx->reg_write = regmap_mmio_write16le;
267 ctx->reg_read = regmap_mmio_read32le;
268 ctx->reg_write = regmap_mmio_write32le;
272 ctx->reg_read = regmap_mmio_read64le;
273 ctx->reg_write = regmap_mmio_write64le;
281 case REGMAP_ENDIAN_BIG:
283 case REGMAP_ENDIAN_NATIVE:
285 switch (config->val_bits) {
287 ctx->reg_read = regmap_mmio_read8;
288 ctx->reg_write = regmap_mmio_write8;
291 ctx->reg_read = regmap_mmio_read16be;
292 ctx->reg_write = regmap_mmio_write16be;
295 ctx->reg_read = regmap_mmio_read32be;
296 ctx->reg_write = regmap_mmio_write32be;
311 ctx->clk = clk_get(dev, clk_id);
312 if (IS_ERR(ctx->clk)) {
313 ret = PTR_ERR(ctx->clk);
317 ret = clk_prepare(ctx->clk);
331 struct regmap *__regmap_init_mmio_clk(struct device *dev, const char *clk_id,
333 const struct regmap_config *config,
334 struct lock_class_key *lock_key,
335 const char *lock_name)
337 struct regmap_mmio_context *ctx;
339 ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
341 return ERR_CAST(ctx);
343 return __regmap_init(dev, ®map_mmio, ctx, config,
344 lock_key, lock_name);
346 EXPORT_SYMBOL_GPL(__regmap_init_mmio_clk);
348 struct regmap *__devm_regmap_init_mmio_clk(struct device *dev,
351 const struct regmap_config *config,
352 struct lock_class_key *lock_key,
353 const char *lock_name)
355 struct regmap_mmio_context *ctx;
357 ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
359 return ERR_CAST(ctx);
361 return __devm_regmap_init(dev, ®map_mmio, ctx, config,
362 lock_key, lock_name);
364 EXPORT_SYMBOL_GPL(__devm_regmap_init_mmio_clk);
366 MODULE_LICENSE("GPL v2");