1 // SPDX-License-Identifier: GPL-2.0+
2 /* Renesas R-Car CAN FD device driver
4 * Copyright (C) 2015 Renesas Electronics Corp.
7 /* The R-Car CAN FD controller can operate in either one of the below two modes
9 * - Classical CAN (CAN 2.0) only mode
11 * This driver puts the controller in CAN FD only mode by default. In this
12 * mode, the controller acts as a CAN FD node that can also interoperate with
15 * To switch the controller to Classical CAN (CAN 2.0) only mode, add
16 * "renesas,no-can-fd" optional property to the device tree node. A h/w reset is
17 * also required to switch modes.
19 * Note: The h/w manual register naming convention is clumsy and not acceptable
20 * to use as it is in the driver. However, those names are added as comments
21 * wherever it is modified to a readable name.
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/interrupt.h>
29 #include <linux/errno.h>
30 #include <linux/netdevice.h>
31 #include <linux/platform_device.h>
32 #include <linux/can/led.h>
33 #include <linux/can/dev.h>
34 #include <linux/clk.h>
36 #include <linux/of_device.h>
37 #include <linux/bitmap.h>
38 #include <linux/bitops.h>
39 #include <linux/iopoll.h>
41 #define RCANFD_DRV_NAME "rcar_canfd"
43 /* Global register bits */
46 #define RCANFD_GRMCFG_RCMC BIT(0)
48 /* RSCFDnCFDGCFG / RSCFDnGCFG */
49 #define RCANFD_GCFG_EEFE BIT(6)
50 #define RCANFD_GCFG_CMPOC BIT(5) /* CAN FD only */
51 #define RCANFD_GCFG_DCS BIT(4)
52 #define RCANFD_GCFG_DCE BIT(1)
53 #define RCANFD_GCFG_TPRI BIT(0)
55 /* RSCFDnCFDGCTR / RSCFDnGCTR */
56 #define RCANFD_GCTR_TSRST BIT(16)
57 #define RCANFD_GCTR_CFMPOFIE BIT(11) /* CAN FD only */
58 #define RCANFD_GCTR_THLEIE BIT(10)
59 #define RCANFD_GCTR_MEIE BIT(9)
60 #define RCANFD_GCTR_DEIE BIT(8)
61 #define RCANFD_GCTR_GSLPR BIT(2)
62 #define RCANFD_GCTR_GMDC_MASK (0x3)
63 #define RCANFD_GCTR_GMDC_GOPM (0x0)
64 #define RCANFD_GCTR_GMDC_GRESET (0x1)
65 #define RCANFD_GCTR_GMDC_GTEST (0x2)
67 /* RSCFDnCFDGSTS / RSCFDnGSTS */
68 #define RCANFD_GSTS_GRAMINIT BIT(3)
69 #define RCANFD_GSTS_GSLPSTS BIT(2)
70 #define RCANFD_GSTS_GHLTSTS BIT(1)
71 #define RCANFD_GSTS_GRSTSTS BIT(0)
72 /* Non-operational status */
73 #define RCANFD_GSTS_GNOPM (BIT(0) | BIT(1) | BIT(2) | BIT(3))
75 /* RSCFDnCFDGERFL / RSCFDnGERFL */
76 #define RCANFD_GERFL_EEF1 BIT(17)
77 #define RCANFD_GERFL_EEF0 BIT(16)
78 #define RCANFD_GERFL_CMPOF BIT(3) /* CAN FD only */
79 #define RCANFD_GERFL_THLES BIT(2)
80 #define RCANFD_GERFL_MES BIT(1)
81 #define RCANFD_GERFL_DEF BIT(0)
83 #define RCANFD_GERFL_ERR(gpriv, x) ((x) & (RCANFD_GERFL_EEF1 |\
84 RCANFD_GERFL_EEF0 | RCANFD_GERFL_MES |\
86 RCANFD_GERFL_CMPOF : 0)))
88 /* AFL Rx rules registers */
90 /* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
91 #define RCANFD_GAFLCFG_SETRNC(n, x) (((x) & 0xff) << (24 - n * 8))
92 #define RCANFD_GAFLCFG_GETRNC(n, x) (((x) >> (24 - n * 8)) & 0xff)
94 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
95 #define RCANFD_GAFLECTR_AFLDAE BIT(8)
96 #define RCANFD_GAFLECTR_AFLPN(x) ((x) & 0x1f)
98 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
99 #define RCANFD_GAFLID_GAFLLB BIT(29)
101 /* RSCFDnCFDGAFLP1_j / RSCFDnGAFLP1_j */
102 #define RCANFD_GAFLP1_GAFLFDP(x) (1 << (x))
104 /* Channel register bits */
106 /* RSCFDnCmCFG - Classical CAN only */
107 #define RCANFD_CFG_SJW(x) (((x) & 0x3) << 24)
108 #define RCANFD_CFG_TSEG2(x) (((x) & 0x7) << 20)
109 #define RCANFD_CFG_TSEG1(x) (((x) & 0xf) << 16)
110 #define RCANFD_CFG_BRP(x) (((x) & 0x3ff) << 0)
112 /* RSCFDnCFDCmNCFG - CAN FD only */
113 #define RCANFD_NCFG_NTSEG2(x) (((x) & 0x1f) << 24)
114 #define RCANFD_NCFG_NTSEG1(x) (((x) & 0x7f) << 16)
115 #define RCANFD_NCFG_NSJW(x) (((x) & 0x1f) << 11)
116 #define RCANFD_NCFG_NBRP(x) (((x) & 0x3ff) << 0)
118 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */
119 #define RCANFD_CCTR_CTME BIT(24)
120 #define RCANFD_CCTR_ERRD BIT(23)
121 #define RCANFD_CCTR_BOM_MASK (0x3 << 21)
122 #define RCANFD_CCTR_BOM_ISO (0x0 << 21)
123 #define RCANFD_CCTR_BOM_BENTRY (0x1 << 21)
124 #define RCANFD_CCTR_BOM_BEND (0x2 << 21)
125 #define RCANFD_CCTR_TDCVFIE BIT(19)
126 #define RCANFD_CCTR_SOCOIE BIT(18)
127 #define RCANFD_CCTR_EOCOIE BIT(17)
128 #define RCANFD_CCTR_TAIE BIT(16)
129 #define RCANFD_CCTR_ALIE BIT(15)
130 #define RCANFD_CCTR_BLIE BIT(14)
131 #define RCANFD_CCTR_OLIE BIT(13)
132 #define RCANFD_CCTR_BORIE BIT(12)
133 #define RCANFD_CCTR_BOEIE BIT(11)
134 #define RCANFD_CCTR_EPIE BIT(10)
135 #define RCANFD_CCTR_EWIE BIT(9)
136 #define RCANFD_CCTR_BEIE BIT(8)
137 #define RCANFD_CCTR_CSLPR BIT(2)
138 #define RCANFD_CCTR_CHMDC_MASK (0x3)
139 #define RCANFD_CCTR_CHDMC_COPM (0x0)
140 #define RCANFD_CCTR_CHDMC_CRESET (0x1)
141 #define RCANFD_CCTR_CHDMC_CHLT (0x2)
143 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */
144 #define RCANFD_CSTS_COMSTS BIT(7)
145 #define RCANFD_CSTS_RECSTS BIT(6)
146 #define RCANFD_CSTS_TRMSTS BIT(5)
147 #define RCANFD_CSTS_BOSTS BIT(4)
148 #define RCANFD_CSTS_EPSTS BIT(3)
149 #define RCANFD_CSTS_SLPSTS BIT(2)
150 #define RCANFD_CSTS_HLTSTS BIT(1)
151 #define RCANFD_CSTS_CRSTSTS BIT(0)
153 #define RCANFD_CSTS_TECCNT(x) (((x) >> 24) & 0xff)
154 #define RCANFD_CSTS_RECCNT(x) (((x) >> 16) & 0xff)
156 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */
157 #define RCANFD_CERFL_ADERR BIT(14)
158 #define RCANFD_CERFL_B0ERR BIT(13)
159 #define RCANFD_CERFL_B1ERR BIT(12)
160 #define RCANFD_CERFL_CERR BIT(11)
161 #define RCANFD_CERFL_AERR BIT(10)
162 #define RCANFD_CERFL_FERR BIT(9)
163 #define RCANFD_CERFL_SERR BIT(8)
164 #define RCANFD_CERFL_ALF BIT(7)
165 #define RCANFD_CERFL_BLF BIT(6)
166 #define RCANFD_CERFL_OVLF BIT(5)
167 #define RCANFD_CERFL_BORF BIT(4)
168 #define RCANFD_CERFL_BOEF BIT(3)
169 #define RCANFD_CERFL_EPF BIT(2)
170 #define RCANFD_CERFL_EWF BIT(1)
171 #define RCANFD_CERFL_BEF BIT(0)
173 #define RCANFD_CERFL_ERR(x) ((x) & (0x7fff)) /* above bits 14:0 */
175 /* RSCFDnCFDCmDCFG */
176 #define RCANFD_DCFG_DSJW(x) (((x) & 0x7) << 24)
177 #define RCANFD_DCFG_DTSEG2(x) (((x) & 0x7) << 20)
178 #define RCANFD_DCFG_DTSEG1(x) (((x) & 0xf) << 16)
179 #define RCANFD_DCFG_DBRP(x) (((x) & 0xff) << 0)
181 /* RSCFDnCFDCmFDCFG */
182 #define RCANFD_FDCFG_TDCE BIT(9)
183 #define RCANFD_FDCFG_TDCOC BIT(8)
184 #define RCANFD_FDCFG_TDCO(x) (((x) & 0x7f) >> 16)
187 #define RCANFD_RFCC_RFIM BIT(12)
188 #define RCANFD_RFCC_RFDC(x) (((x) & 0x7) << 8)
189 #define RCANFD_RFCC_RFPLS(x) (((x) & 0x7) << 4)
190 #define RCANFD_RFCC_RFIE BIT(1)
191 #define RCANFD_RFCC_RFE BIT(0)
193 /* RSCFDnCFDRFSTSx */
194 #define RCANFD_RFSTS_RFIF BIT(3)
195 #define RCANFD_RFSTS_RFMLT BIT(2)
196 #define RCANFD_RFSTS_RFFLL BIT(1)
197 #define RCANFD_RFSTS_RFEMP BIT(0)
200 #define RCANFD_RFID_RFIDE BIT(31)
201 #define RCANFD_RFID_RFRTR BIT(30)
203 /* RSCFDnCFDRFPTRx */
204 #define RCANFD_RFPTR_RFDLC(x) (((x) >> 28) & 0xf)
205 #define RCANFD_RFPTR_RFPTR(x) (((x) >> 16) & 0xfff)
206 #define RCANFD_RFPTR_RFTS(x) (((x) >> 0) & 0xffff)
208 /* RSCFDnCFDRFFDSTSx */
209 #define RCANFD_RFFDSTS_RFFDF BIT(2)
210 #define RCANFD_RFFDSTS_RFBRS BIT(1)
211 #define RCANFD_RFFDSTS_RFESI BIT(0)
213 /* Common FIFO bits */
216 #define RCANFD_CFCC_CFTML(x) (((x) & 0xf) << 20)
217 #define RCANFD_CFCC_CFM(x) (((x) & 0x3) << 16)
218 #define RCANFD_CFCC_CFIM BIT(12)
219 #define RCANFD_CFCC_CFDC(x) (((x) & 0x7) << 8)
220 #define RCANFD_CFCC_CFPLS(x) (((x) & 0x7) << 4)
221 #define RCANFD_CFCC_CFTXIE BIT(2)
222 #define RCANFD_CFCC_CFE BIT(0)
224 /* RSCFDnCFDCFSTSk */
225 #define RCANFD_CFSTS_CFMC(x) (((x) >> 8) & 0xff)
226 #define RCANFD_CFSTS_CFTXIF BIT(4)
227 #define RCANFD_CFSTS_CFMLT BIT(2)
228 #define RCANFD_CFSTS_CFFLL BIT(1)
229 #define RCANFD_CFSTS_CFEMP BIT(0)
232 #define RCANFD_CFID_CFIDE BIT(31)
233 #define RCANFD_CFID_CFRTR BIT(30)
234 #define RCANFD_CFID_CFID_MASK(x) ((x) & 0x1fffffff)
236 /* RSCFDnCFDCFPTRk */
237 #define RCANFD_CFPTR_CFDLC(x) (((x) & 0xf) << 28)
238 #define RCANFD_CFPTR_CFPTR(x) (((x) & 0xfff) << 16)
239 #define RCANFD_CFPTR_CFTS(x) (((x) & 0xff) << 0)
241 /* RSCFDnCFDCFFDCSTSk */
242 #define RCANFD_CFFDCSTS_CFFDF BIT(2)
243 #define RCANFD_CFFDCSTS_CFBRS BIT(1)
244 #define RCANFD_CFFDCSTS_CFESI BIT(0)
246 /* This controller supports either Classical CAN only mode or CAN FD only mode.
247 * These modes are supported in two separate set of register maps & names.
248 * However, some of the register offsets are common for both modes. Those
249 * offsets are listed below as Common registers.
251 * The CAN FD only mode specific registers & Classical CAN only mode specific
252 * registers are listed separately. Their register names starts with
253 * RCANFD_F_xxx & RCANFD_C_xxx respectively.
256 /* Common registers */
258 /* RSCFDnCFDCmNCFG / RSCFDnCmCFG */
259 #define RCANFD_CCFG(m) (0x0000 + (0x10 * (m)))
260 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */
261 #define RCANFD_CCTR(m) (0x0004 + (0x10 * (m)))
262 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */
263 #define RCANFD_CSTS(m) (0x0008 + (0x10 * (m)))
264 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */
265 #define RCANFD_CERFL(m) (0x000C + (0x10 * (m)))
267 /* RSCFDnCFDGCFG / RSCFDnGCFG */
268 #define RCANFD_GCFG (0x0084)
269 /* RSCFDnCFDGCTR / RSCFDnGCTR */
270 #define RCANFD_GCTR (0x0088)
271 /* RSCFDnCFDGCTS / RSCFDnGCTS */
272 #define RCANFD_GSTS (0x008c)
273 /* RSCFDnCFDGERFL / RSCFDnGERFL */
274 #define RCANFD_GERFL (0x0090)
275 /* RSCFDnCFDGTSC / RSCFDnGTSC */
276 #define RCANFD_GTSC (0x0094)
277 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
278 #define RCANFD_GAFLECTR (0x0098)
279 /* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
280 #define RCANFD_GAFLCFG0 (0x009c)
281 /* RSCFDnCFDGAFLCFG1 / RSCFDnGAFLCFG1 */
282 #define RCANFD_GAFLCFG1 (0x00a0)
283 /* RSCFDnCFDRMNB / RSCFDnRMNB */
284 #define RCANFD_RMNB (0x00a4)
285 /* RSCFDnCFDRMND / RSCFDnRMND */
286 #define RCANFD_RMND(y) (0x00a8 + (0x04 * (y)))
288 /* RSCFDnCFDRFCCx / RSCFDnRFCCx */
289 #define RCANFD_RFCC(x) (0x00b8 + (0x04 * (x)))
290 /* RSCFDnCFDRFSTSx / RSCFDnRFSTSx */
291 #define RCANFD_RFSTS(x) (0x00d8 + (0x04 * (x)))
292 /* RSCFDnCFDRFPCTRx / RSCFDnRFPCTRx */
293 #define RCANFD_RFPCTR(x) (0x00f8 + (0x04 * (x)))
295 /* Common FIFO Control registers */
297 /* RSCFDnCFDCFCCx / RSCFDnCFCCx */
298 #define RCANFD_CFCC(ch, idx) (0x0118 + (0x0c * (ch)) + \
300 /* RSCFDnCFDCFSTSx / RSCFDnCFSTSx */
301 #define RCANFD_CFSTS(ch, idx) (0x0178 + (0x0c * (ch)) + \
303 /* RSCFDnCFDCFPCTRx / RSCFDnCFPCTRx */
304 #define RCANFD_CFPCTR(ch, idx) (0x01d8 + (0x0c * (ch)) + \
307 /* RSCFDnCFDFESTS / RSCFDnFESTS */
308 #define RCANFD_FESTS (0x0238)
309 /* RSCFDnCFDFFSTS / RSCFDnFFSTS */
310 #define RCANFD_FFSTS (0x023c)
311 /* RSCFDnCFDFMSTS / RSCFDnFMSTS */
312 #define RCANFD_FMSTS (0x0240)
313 /* RSCFDnCFDRFISTS / RSCFDnRFISTS */
314 #define RCANFD_RFISTS (0x0244)
315 /* RSCFDnCFDCFRISTS / RSCFDnCFRISTS */
316 #define RCANFD_CFRISTS (0x0248)
317 /* RSCFDnCFDCFTISTS / RSCFDnCFTISTS */
318 #define RCANFD_CFTISTS (0x024c)
320 /* RSCFDnCFDTMCp / RSCFDnTMCp */
321 #define RCANFD_TMC(p) (0x0250 + (0x01 * (p)))
322 /* RSCFDnCFDTMSTSp / RSCFDnTMSTSp */
323 #define RCANFD_TMSTS(p) (0x02d0 + (0x01 * (p)))
325 /* RSCFDnCFDTMTRSTSp / RSCFDnTMTRSTSp */
326 #define RCANFD_TMTRSTS(y) (0x0350 + (0x04 * (y)))
327 /* RSCFDnCFDTMTARSTSp / RSCFDnTMTARSTSp */
328 #define RCANFD_TMTARSTS(y) (0x0360 + (0x04 * (y)))
329 /* RSCFDnCFDTMTCSTSp / RSCFDnTMTCSTSp */
330 #define RCANFD_TMTCSTS(y) (0x0370 + (0x04 * (y)))
331 /* RSCFDnCFDTMTASTSp / RSCFDnTMTASTSp */
332 #define RCANFD_TMTASTS(y) (0x0380 + (0x04 * (y)))
333 /* RSCFDnCFDTMIECy / RSCFDnTMIECy */
334 #define RCANFD_TMIEC(y) (0x0390 + (0x04 * (y)))
336 /* RSCFDnCFDTXQCCm / RSCFDnTXQCCm */
337 #define RCANFD_TXQCC(m) (0x03a0 + (0x04 * (m)))
338 /* RSCFDnCFDTXQSTSm / RSCFDnTXQSTSm */
339 #define RCANFD_TXQSTS(m) (0x03c0 + (0x04 * (m)))
340 /* RSCFDnCFDTXQPCTRm / RSCFDnTXQPCTRm */
341 #define RCANFD_TXQPCTR(m) (0x03e0 + (0x04 * (m)))
343 /* RSCFDnCFDTHLCCm / RSCFDnTHLCCm */
344 #define RCANFD_THLCC(m) (0x0400 + (0x04 * (m)))
345 /* RSCFDnCFDTHLSTSm / RSCFDnTHLSTSm */
346 #define RCANFD_THLSTS(m) (0x0420 + (0x04 * (m)))
347 /* RSCFDnCFDTHLPCTRm / RSCFDnTHLPCTRm */
348 #define RCANFD_THLPCTR(m) (0x0440 + (0x04 * (m)))
350 /* RSCFDnCFDGTINTSTS0 / RSCFDnGTINTSTS0 */
351 #define RCANFD_GTINTSTS0 (0x0460)
352 /* RSCFDnCFDGTINTSTS1 / RSCFDnGTINTSTS1 */
353 #define RCANFD_GTINTSTS1 (0x0464)
354 /* RSCFDnCFDGTSTCFG / RSCFDnGTSTCFG */
355 #define RCANFD_GTSTCFG (0x0468)
356 /* RSCFDnCFDGTSTCTR / RSCFDnGTSTCTR */
357 #define RCANFD_GTSTCTR (0x046c)
358 /* RSCFDnCFDGLOCKK / RSCFDnGLOCKK */
359 #define RCANFD_GLOCKK (0x047c)
360 /* RSCFDnCFDGRMCFG */
361 #define RCANFD_GRMCFG (0x04fc)
363 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
364 #define RCANFD_GAFLID(offset, j) ((offset) + (0x10 * (j)))
365 /* RSCFDnCFDGAFLMj / RSCFDnGAFLMj */
366 #define RCANFD_GAFLM(offset, j) ((offset) + 0x04 + (0x10 * (j)))
367 /* RSCFDnCFDGAFLP0j / RSCFDnGAFLP0j */
368 #define RCANFD_GAFLP0(offset, j) ((offset) + 0x08 + (0x10 * (j)))
369 /* RSCFDnCFDGAFLP1j / RSCFDnGAFLP1j */
370 #define RCANFD_GAFLP1(offset, j) ((offset) + 0x0c + (0x10 * (j)))
372 /* Classical CAN only mode register map */
374 /* RSCFDnGAFLXXXj offset */
375 #define RCANFD_C_GAFL_OFFSET (0x0500)
377 /* RSCFDnRMXXXq -> RCANFD_C_RMXXX(q) */
378 #define RCANFD_C_RMID(q) (0x0600 + (0x10 * (q)))
379 #define RCANFD_C_RMPTR(q) (0x0604 + (0x10 * (q)))
380 #define RCANFD_C_RMDF0(q) (0x0608 + (0x10 * (q)))
381 #define RCANFD_C_RMDF1(q) (0x060c + (0x10 * (q)))
383 /* RSCFDnRFXXx -> RCANFD_C_RFXX(x) */
384 #define RCANFD_C_RFOFFSET (0x0e00)
385 #define RCANFD_C_RFID(x) (RCANFD_C_RFOFFSET + (0x10 * (x)))
386 #define RCANFD_C_RFPTR(x) (RCANFD_C_RFOFFSET + 0x04 + \
388 #define RCANFD_C_RFDF(x, df) (RCANFD_C_RFOFFSET + 0x08 + \
389 (0x10 * (x)) + (0x04 * (df)))
391 /* RSCFDnCFXXk -> RCANFD_C_CFXX(ch, k) */
392 #define RCANFD_C_CFOFFSET (0x0e80)
393 #define RCANFD_C_CFID(ch, idx) (RCANFD_C_CFOFFSET + (0x30 * (ch)) + \
395 #define RCANFD_C_CFPTR(ch, idx) (RCANFD_C_CFOFFSET + 0x04 + \
396 (0x30 * (ch)) + (0x10 * (idx)))
397 #define RCANFD_C_CFDF(ch, idx, df) (RCANFD_C_CFOFFSET + 0x08 + \
398 (0x30 * (ch)) + (0x10 * (idx)) + \
401 /* RSCFDnTMXXp -> RCANFD_C_TMXX(p) */
402 #define RCANFD_C_TMID(p) (0x1000 + (0x10 * (p)))
403 #define RCANFD_C_TMPTR(p) (0x1004 + (0x10 * (p)))
404 #define RCANFD_C_TMDF0(p) (0x1008 + (0x10 * (p)))
405 #define RCANFD_C_TMDF1(p) (0x100c + (0x10 * (p)))
408 #define RCANFD_C_THLACC(m) (0x1800 + (0x04 * (m)))
410 #define RCANFD_C_RPGACC(r) (0x1900 + (0x04 * (r)))
412 /* CAN FD mode specific register map */
414 /* RSCFDnCFDCmXXX -> RCANFD_F_XXX(m) */
415 #define RCANFD_F_DCFG(m) (0x0500 + (0x20 * (m)))
416 #define RCANFD_F_CFDCFG(m) (0x0504 + (0x20 * (m)))
417 #define RCANFD_F_CFDCTR(m) (0x0508 + (0x20 * (m)))
418 #define RCANFD_F_CFDSTS(m) (0x050c + (0x20 * (m)))
419 #define RCANFD_F_CFDCRC(m) (0x0510 + (0x20 * (m)))
421 /* RSCFDnCFDGAFLXXXj offset */
422 #define RCANFD_F_GAFL_OFFSET (0x1000)
424 /* RSCFDnCFDRMXXXq -> RCANFD_F_RMXXX(q) */
425 #define RCANFD_F_RMID(q) (0x2000 + (0x20 * (q)))
426 #define RCANFD_F_RMPTR(q) (0x2004 + (0x20 * (q)))
427 #define RCANFD_F_RMFDSTS(q) (0x2008 + (0x20 * (q)))
428 #define RCANFD_F_RMDF(q, b) (0x200c + (0x04 * (b)) + (0x20 * (q)))
430 /* RSCFDnCFDRFXXx -> RCANFD_F_RFXX(x) */
431 #define RCANFD_F_RFOFFSET (0x3000)
432 #define RCANFD_F_RFID(x) (RCANFD_F_RFOFFSET + (0x80 * (x)))
433 #define RCANFD_F_RFPTR(x) (RCANFD_F_RFOFFSET + 0x04 + \
435 #define RCANFD_F_RFFDSTS(x) (RCANFD_F_RFOFFSET + 0x08 + \
437 #define RCANFD_F_RFDF(x, df) (RCANFD_F_RFOFFSET + 0x0c + \
438 (0x80 * (x)) + (0x04 * (df)))
440 /* RSCFDnCFDCFXXk -> RCANFD_F_CFXX(ch, k) */
441 #define RCANFD_F_CFOFFSET (0x3400)
442 #define RCANFD_F_CFID(ch, idx) (RCANFD_F_CFOFFSET + (0x180 * (ch)) + \
444 #define RCANFD_F_CFPTR(ch, idx) (RCANFD_F_CFOFFSET + 0x04 + \
445 (0x180 * (ch)) + (0x80 * (idx)))
446 #define RCANFD_F_CFFDCSTS(ch, idx) (RCANFD_F_CFOFFSET + 0x08 + \
447 (0x180 * (ch)) + (0x80 * (idx)))
448 #define RCANFD_F_CFDF(ch, idx, df) (RCANFD_F_CFOFFSET + 0x0c + \
449 (0x180 * (ch)) + (0x80 * (idx)) + \
452 /* RSCFDnCFDTMXXp -> RCANFD_F_TMXX(p) */
453 #define RCANFD_F_TMID(p) (0x4000 + (0x20 * (p)))
454 #define RCANFD_F_TMPTR(p) (0x4004 + (0x20 * (p)))
455 #define RCANFD_F_TMFDCTR(p) (0x4008 + (0x20 * (p)))
456 #define RCANFD_F_TMDF(p, b) (0x400c + (0x20 * (p)) + (0x04 * (b)))
458 /* RSCFDnCFDTHLACCm */
459 #define RCANFD_F_THLACC(m) (0x6000 + (0x04 * (m)))
460 /* RSCFDnCFDRPGACCr */
461 #define RCANFD_F_RPGACC(r) (0x6400 + (0x04 * (r)))
464 #define RCANFD_FIFO_DEPTH 8 /* Tx FIFO depth */
465 #define RCANFD_NAPI_WEIGHT 8 /* Rx poll quota */
467 #define RCANFD_NUM_CHANNELS 2 /* Two channels max */
468 #define RCANFD_CHANNELS_MASK BIT((RCANFD_NUM_CHANNELS) - 1)
470 #define RCANFD_GAFL_PAGENUM(entry) ((entry) / 16)
471 #define RCANFD_CHANNEL_NUMRULES 1 /* only one rule per channel */
473 /* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
474 * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
475 * number is added to RFFIFO index.
477 #define RCANFD_RFFIFO_IDX 0
479 /* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
480 * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
482 #define RCANFD_CFFIFO_IDX 0
484 /* fCAN clock select register settings */
485 enum rcar_canfd_fcanclk {
486 RCANFD_CANFDCLK = 0, /* CANFD clock */
487 RCANFD_EXTCLK, /* Externally input clock */
490 struct rcar_canfd_global;
492 /* Channel priv data */
493 struct rcar_canfd_channel {
494 struct can_priv can; /* Must be the first member */
495 struct net_device *ndev;
496 struct rcar_canfd_global *gpriv; /* Controller reference */
497 void __iomem *base; /* Register base address */
498 struct napi_struct napi;
499 u8 tx_len[RCANFD_FIFO_DEPTH]; /* For net stats */
500 u32 tx_head; /* Incremented on xmit */
501 u32 tx_tail; /* Incremented on xmit done */
502 u32 channel; /* Channel number */
503 spinlock_t tx_lock; /* To protect tx path */
506 /* Global priv data */
507 struct rcar_canfd_global {
508 struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
509 void __iomem *base; /* Register base address */
510 struct platform_device *pdev; /* Respective platform device */
511 struct clk *clkp; /* Peripheral clock */
512 struct clk *can_clk; /* fCAN clock */
513 enum rcar_canfd_fcanclk fcan; /* CANFD or Ext clock */
514 unsigned long channels_mask; /* Enabled channels mask */
515 bool fdmode; /* CAN FD or Classical CAN only mode */
518 /* CAN FD mode nominal rate constants */
519 static const struct can_bittiming_const rcar_canfd_nom_bittiming_const = {
520 .name = RCANFD_DRV_NAME,
531 /* CAN FD mode data rate constants */
532 static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
533 .name = RCANFD_DRV_NAME,
544 /* Classical CAN mode bitrate constants */
545 static const struct can_bittiming_const rcar_canfd_bittiming_const = {
546 .name = RCANFD_DRV_NAME,
557 /* Helper functions */
558 static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
560 u32 data = readl(reg);
563 data |= (val & mask);
567 static inline u32 rcar_canfd_read(void __iomem *base, u32 offset)
569 return readl(base + (offset));
572 static inline void rcar_canfd_write(void __iomem *base, u32 offset, u32 val)
574 writel(val, base + (offset));
577 static void rcar_canfd_set_bit(void __iomem *base, u32 reg, u32 val)
579 rcar_canfd_update(val, val, base + (reg));
582 static void rcar_canfd_clear_bit(void __iomem *base, u32 reg, u32 val)
584 rcar_canfd_update(val, 0, base + (reg));
587 static void rcar_canfd_update_bit(void __iomem *base, u32 reg,
590 rcar_canfd_update(mask, val, base + (reg));
593 static void rcar_canfd_get_data(struct rcar_canfd_channel *priv,
594 struct canfd_frame *cf, u32 off)
598 lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
599 for (i = 0; i < lwords; i++)
600 *((u32 *)cf->data + i) =
601 rcar_canfd_read(priv->base, off + (i * sizeof(u32)));
604 static void rcar_canfd_put_data(struct rcar_canfd_channel *priv,
605 struct canfd_frame *cf, u32 off)
609 lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
610 for (i = 0; i < lwords; i++)
611 rcar_canfd_write(priv->base, off + (i * sizeof(u32)),
612 *((u32 *)cf->data + i));
615 static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
619 for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
620 can_free_echo_skb(ndev, i);
623 static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
628 /* Check RAMINIT flag as CAN RAM initialization takes place
629 * after the MCU reset
631 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
632 !(sts & RCANFD_GSTS_GRAMINIT), 2, 500000);
634 dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
638 /* Transition to Global Reset mode */
639 rcar_canfd_clear_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
640 rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR,
641 RCANFD_GCTR_GMDC_MASK, RCANFD_GCTR_GMDC_GRESET);
643 /* Ensure Global reset mode */
644 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
645 (sts & RCANFD_GSTS_GRSTSTS), 2, 500000);
647 dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
651 /* Reset Global error flags */
652 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
654 /* Set the controller into appropriate mode */
656 rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG,
659 rcar_canfd_clear_bit(gpriv->base, RCANFD_GRMCFG,
662 /* Transition all Channels to reset mode */
663 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
664 rcar_canfd_clear_bit(gpriv->base,
665 RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
667 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
668 RCANFD_CCTR_CHMDC_MASK,
669 RCANFD_CCTR_CHDMC_CRESET);
671 /* Ensure Channel reset mode */
672 err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
673 (sts & RCANFD_CSTS_CRSTSTS),
676 dev_dbg(&gpriv->pdev->dev,
677 "channel %u reset failed\n", ch);
684 static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
688 /* Global configuration settings */
690 /* ECC Error flag Enable */
691 cfg = RCANFD_GCFG_EEFE;
694 /* Truncate payload to configured message size RFPLS */
695 cfg |= RCANFD_GCFG_CMPOC;
697 /* Set External Clock if selected */
698 if (gpriv->fcan != RCANFD_CANFDCLK)
699 cfg |= RCANFD_GCFG_DCS;
701 rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg);
703 /* Channel configuration settings */
704 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
705 rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch),
707 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
708 RCANFD_CCTR_BOM_MASK,
709 RCANFD_CCTR_BOM_BENTRY);
713 static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
717 int offset, start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
718 u32 ridx = ch + RCANFD_RFFIFO_IDX;
721 start = 0; /* Channel 0 always starts from 0th rule */
723 /* Get number of Channel 0 rules and adjust */
724 cfg = rcar_canfd_read(gpriv->base, RCANFD_GAFLCFG0);
725 start = RCANFD_GAFLCFG_GETRNC(0, cfg);
728 /* Enable write access to entry */
729 page = RCANFD_GAFL_PAGENUM(start);
730 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR,
731 (RCANFD_GAFLECTR_AFLPN(page) |
732 RCANFD_GAFLECTR_AFLDAE));
734 /* Write number of rules for channel */
735 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG0,
736 RCANFD_GAFLCFG_SETRNC(ch, num_rules));
738 offset = RCANFD_F_GAFL_OFFSET;
740 offset = RCANFD_C_GAFL_OFFSET;
743 rcar_canfd_write(gpriv->base, RCANFD_GAFLID(offset, start), 0);
744 /* IDE or RTR is not considered for matching */
745 rcar_canfd_write(gpriv->base, RCANFD_GAFLM(offset, start), 0);
746 /* Any data length accepted */
747 rcar_canfd_write(gpriv->base, RCANFD_GAFLP0(offset, start), 0);
748 /* Place the msg in corresponding Rx FIFO entry */
749 rcar_canfd_write(gpriv->base, RCANFD_GAFLP1(offset, start),
750 RCANFD_GAFLP1_GAFLFDP(ridx));
752 /* Disable write access to page */
753 rcar_canfd_clear_bit(gpriv->base,
754 RCANFD_GAFLECTR, RCANFD_GAFLECTR_AFLDAE);
757 static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
759 /* Rx FIFO is used for reception */
763 /* Select Rx FIFO based on channel */
764 u32 ridx = ch + RCANFD_RFFIFO_IDX;
766 rfdc = 2; /* b010 - 8 messages Rx FIFO depth */
768 rfpls = 7; /* b111 - Max 64 bytes payload */
770 rfpls = 0; /* b000 - Max 8 bytes payload */
772 cfg = (RCANFD_RFCC_RFIM | RCANFD_RFCC_RFDC(rfdc) |
773 RCANFD_RFCC_RFPLS(rfpls) | RCANFD_RFCC_RFIE);
774 rcar_canfd_write(gpriv->base, RCANFD_RFCC(ridx), cfg);
777 static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
779 /* Tx/Rx(Common) FIFO configured in Tx mode is
780 * used for transmission
782 * Each channel has 3 Common FIFO dedicated to them.
783 * Use the 1st (index 0) out of 3
786 u16 cftml, cfm, cfdc, cfpls;
788 cftml = 0; /* 0th buffer */
789 cfm = 1; /* b01 - Transmit mode */
790 cfdc = 2; /* b010 - 8 messages Tx FIFO depth */
792 cfpls = 7; /* b111 - Max 64 bytes payload */
794 cfpls = 0; /* b000 - Max 8 bytes payload */
796 cfg = (RCANFD_CFCC_CFTML(cftml) | RCANFD_CFCC_CFM(cfm) |
797 RCANFD_CFCC_CFIM | RCANFD_CFCC_CFDC(cfdc) |
798 RCANFD_CFCC_CFPLS(cfpls) | RCANFD_CFCC_CFTXIE);
799 rcar_canfd_write(gpriv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX), cfg);
802 /* Clear FD mode specific control/status register */
803 rcar_canfd_write(gpriv->base,
804 RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), 0);
807 static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
811 /* Clear any stray error interrupt flags */
812 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
814 /* Global interrupts setup */
815 ctr = RCANFD_GCTR_MEIE;
817 ctr |= RCANFD_GCTR_CFMPOFIE;
819 rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr);
822 static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
825 /* Disable all interrupts */
826 rcar_canfd_write(gpriv->base, RCANFD_GCTR, 0);
828 /* Clear any stray error interrupt flags */
829 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
832 static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
835 u32 ctr, ch = priv->channel;
837 /* Clear any stray error flags */
838 rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
840 /* Channel interrupts setup */
841 ctr = (RCANFD_CCTR_TAIE |
842 RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
843 RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
844 RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
845 RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
846 rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr);
849 static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
852 u32 ctr, ch = priv->channel;
854 ctr = (RCANFD_CCTR_TAIE |
855 RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
856 RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
857 RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
858 RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
859 rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr);
861 /* Clear any stray error flags */
862 rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
865 static void rcar_canfd_global_error(struct net_device *ndev)
867 struct rcar_canfd_channel *priv = netdev_priv(ndev);
868 struct rcar_canfd_global *gpriv = priv->gpriv;
869 struct net_device_stats *stats = &ndev->stats;
870 u32 ch = priv->channel;
872 u32 ridx = ch + RCANFD_RFFIFO_IDX;
874 gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
875 if ((gerfl & RCANFD_GERFL_EEF0) && (ch == 0)) {
876 netdev_dbg(ndev, "Ch0: ECC Error flag\n");
879 if ((gerfl & RCANFD_GERFL_EEF1) && (ch == 1)) {
880 netdev_dbg(ndev, "Ch1: ECC Error flag\n");
883 if (gerfl & RCANFD_GERFL_MES) {
884 sts = rcar_canfd_read(priv->base,
885 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
886 if (sts & RCANFD_CFSTS_CFMLT) {
887 netdev_dbg(ndev, "Tx Message Lost flag\n");
889 rcar_canfd_write(priv->base,
890 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
891 sts & ~RCANFD_CFSTS_CFMLT);
894 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
895 if (sts & RCANFD_RFSTS_RFMLT) {
896 netdev_dbg(ndev, "Rx Message Lost flag\n");
898 rcar_canfd_write(priv->base, RCANFD_RFSTS(ridx),
899 sts & ~RCANFD_RFSTS_RFMLT);
902 if (gpriv->fdmode && gerfl & RCANFD_GERFL_CMPOF) {
903 /* Message Lost flag will be set for respective channel
904 * when this condition happens with counters and flags
907 netdev_dbg(ndev, "global payload overflow interrupt\n");
910 /* Clear all global error interrupts. Only affected channels bits
913 rcar_canfd_write(priv->base, RCANFD_GERFL, 0);
916 static void rcar_canfd_error(struct net_device *ndev, u32 cerfl,
917 u16 txerr, u16 rxerr)
919 struct rcar_canfd_channel *priv = netdev_priv(ndev);
920 struct net_device_stats *stats = &ndev->stats;
921 struct can_frame *cf;
923 u32 ch = priv->channel;
925 netdev_dbg(ndev, "ch erfl %x txerr %u rxerr %u\n", cerfl, txerr, rxerr);
927 /* Propagate the error condition to the CAN stack */
928 skb = alloc_can_err_skb(ndev, &cf);
934 /* Channel error interrupts */
935 if (cerfl & RCANFD_CERFL_BEF) {
936 netdev_dbg(ndev, "Bus error\n");
937 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
938 cf->data[2] = CAN_ERR_PROT_UNSPEC;
939 priv->can.can_stats.bus_error++;
941 if (cerfl & RCANFD_CERFL_ADERR) {
942 netdev_dbg(ndev, "ACK Delimiter Error\n");
944 cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
946 if (cerfl & RCANFD_CERFL_B0ERR) {
947 netdev_dbg(ndev, "Bit Error (dominant)\n");
949 cf->data[2] |= CAN_ERR_PROT_BIT0;
951 if (cerfl & RCANFD_CERFL_B1ERR) {
952 netdev_dbg(ndev, "Bit Error (recessive)\n");
954 cf->data[2] |= CAN_ERR_PROT_BIT1;
956 if (cerfl & RCANFD_CERFL_CERR) {
957 netdev_dbg(ndev, "CRC Error\n");
959 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
961 if (cerfl & RCANFD_CERFL_AERR) {
962 netdev_dbg(ndev, "ACK Error\n");
964 cf->can_id |= CAN_ERR_ACK;
965 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
967 if (cerfl & RCANFD_CERFL_FERR) {
968 netdev_dbg(ndev, "Form Error\n");
970 cf->data[2] |= CAN_ERR_PROT_FORM;
972 if (cerfl & RCANFD_CERFL_SERR) {
973 netdev_dbg(ndev, "Stuff Error\n");
975 cf->data[2] |= CAN_ERR_PROT_STUFF;
977 if (cerfl & RCANFD_CERFL_ALF) {
978 netdev_dbg(ndev, "Arbitration lost Error\n");
979 priv->can.can_stats.arbitration_lost++;
980 cf->can_id |= CAN_ERR_LOSTARB;
981 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
983 if (cerfl & RCANFD_CERFL_BLF) {
984 netdev_dbg(ndev, "Bus Lock Error\n");
986 cf->can_id |= CAN_ERR_BUSERROR;
988 if (cerfl & RCANFD_CERFL_EWF) {
989 netdev_dbg(ndev, "Error warning interrupt\n");
990 priv->can.state = CAN_STATE_ERROR_WARNING;
991 priv->can.can_stats.error_warning++;
992 cf->can_id |= CAN_ERR_CRTL;
993 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
994 CAN_ERR_CRTL_RX_WARNING;
998 if (cerfl & RCANFD_CERFL_EPF) {
999 netdev_dbg(ndev, "Error passive interrupt\n");
1000 priv->can.state = CAN_STATE_ERROR_PASSIVE;
1001 priv->can.can_stats.error_passive++;
1002 cf->can_id |= CAN_ERR_CRTL;
1003 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
1004 CAN_ERR_CRTL_RX_PASSIVE;
1005 cf->data[6] = txerr;
1006 cf->data[7] = rxerr;
1008 if (cerfl & RCANFD_CERFL_BOEF) {
1009 netdev_dbg(ndev, "Bus-off entry interrupt\n");
1010 rcar_canfd_tx_failure_cleanup(ndev);
1011 priv->can.state = CAN_STATE_BUS_OFF;
1012 priv->can.can_stats.bus_off++;
1014 cf->can_id |= CAN_ERR_BUSOFF;
1016 if (cerfl & RCANFD_CERFL_OVLF) {
1018 "Overload Frame Transmission error interrupt\n");
1020 cf->can_id |= CAN_ERR_PROT;
1021 cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
1024 /* Clear channel error interrupts that are handled */
1025 rcar_canfd_write(priv->base, RCANFD_CERFL(ch),
1026 RCANFD_CERFL_ERR(~cerfl));
1027 stats->rx_packets++;
1028 stats->rx_bytes += cf->can_dlc;
1032 static void rcar_canfd_tx_done(struct net_device *ndev)
1034 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1035 struct net_device_stats *stats = &ndev->stats;
1037 unsigned long flags;
1038 u32 ch = priv->channel;
1043 sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
1044 stats->tx_packets++;
1045 stats->tx_bytes += priv->tx_len[sent];
1046 priv->tx_len[sent] = 0;
1047 can_get_echo_skb(ndev, sent);
1049 spin_lock_irqsave(&priv->tx_lock, flags);
1051 sts = rcar_canfd_read(priv->base,
1052 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
1053 unsent = RCANFD_CFSTS_CFMC(sts);
1055 /* Wake producer only when there is room */
1056 if (unsent != RCANFD_FIFO_DEPTH)
1057 netif_wake_queue(ndev);
1059 if (priv->tx_head - priv->tx_tail <= unsent) {
1060 spin_unlock_irqrestore(&priv->tx_lock, flags);
1063 spin_unlock_irqrestore(&priv->tx_lock, flags);
1067 /* Clear interrupt */
1068 rcar_canfd_write(priv->base, RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
1069 sts & ~RCANFD_CFSTS_CFTXIF);
1070 can_led_event(ndev, CAN_LED_EVENT_TX);
1073 static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
1075 struct rcar_canfd_global *gpriv = dev_id;
1076 struct net_device *ndev;
1077 struct rcar_canfd_channel *priv;
1081 /* Global error interrupts still indicate a condition specific
1082 * to a channel. RxFIFO interrupt is a global interrupt.
1084 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1085 priv = gpriv->ch[ch];
1087 ridx = ch + RCANFD_RFFIFO_IDX;
1089 /* Global error interrupts */
1090 gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
1091 if (unlikely(RCANFD_GERFL_ERR(gpriv, gerfl)))
1092 rcar_canfd_global_error(ndev);
1094 /* Handle Rx interrupts */
1095 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
1096 cc = rcar_canfd_read(priv->base, RCANFD_RFCC(ridx));
1097 if (likely(sts & RCANFD_RFSTS_RFIF &&
1098 cc & RCANFD_RFCC_RFIE)) {
1099 if (napi_schedule_prep(&priv->napi)) {
1100 /* Disable Rx FIFO interrupts */
1101 rcar_canfd_clear_bit(priv->base,
1104 __napi_schedule(&priv->napi);
1111 static void rcar_canfd_state_change(struct net_device *ndev,
1112 u16 txerr, u16 rxerr)
1114 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1115 struct net_device_stats *stats = &ndev->stats;
1116 enum can_state rx_state, tx_state, state = priv->can.state;
1117 struct can_frame *cf;
1118 struct sk_buff *skb;
1120 /* Handle transition from error to normal states */
1121 if (txerr < 96 && rxerr < 96)
1122 state = CAN_STATE_ERROR_ACTIVE;
1123 else if (txerr < 128 && rxerr < 128)
1124 state = CAN_STATE_ERROR_WARNING;
1126 if (state != priv->can.state) {
1127 netdev_dbg(ndev, "state: new %d, old %d: txerr %u, rxerr %u\n",
1128 state, priv->can.state, txerr, rxerr);
1129 skb = alloc_can_err_skb(ndev, &cf);
1131 stats->rx_dropped++;
1134 tx_state = txerr >= rxerr ? state : 0;
1135 rx_state = txerr <= rxerr ? state : 0;
1137 can_change_state(ndev, cf, tx_state, rx_state);
1138 stats->rx_packets++;
1139 stats->rx_bytes += cf->can_dlc;
1144 static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
1146 struct rcar_canfd_global *gpriv = dev_id;
1147 struct net_device *ndev;
1148 struct rcar_canfd_channel *priv;
1152 /* Common FIFO is a per channel resource */
1153 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1154 priv = gpriv->ch[ch];
1157 /* Channel error interrupts */
1158 cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
1159 sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1160 txerr = RCANFD_CSTS_TECCNT(sts);
1161 rxerr = RCANFD_CSTS_RECCNT(sts);
1162 if (unlikely(RCANFD_CERFL_ERR(cerfl)))
1163 rcar_canfd_error(ndev, cerfl, txerr, rxerr);
1165 /* Handle state change to lower states */
1166 if (unlikely((priv->can.state != CAN_STATE_ERROR_ACTIVE) &&
1167 (priv->can.state != CAN_STATE_BUS_OFF)))
1168 rcar_canfd_state_change(ndev, txerr, rxerr);
1170 /* Handle Tx interrupts */
1171 sts = rcar_canfd_read(priv->base,
1172 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
1173 if (likely(sts & RCANFD_CFSTS_CFTXIF))
1174 rcar_canfd_tx_done(ndev);
1179 static void rcar_canfd_set_bittiming(struct net_device *dev)
1181 struct rcar_canfd_channel *priv = netdev_priv(dev);
1182 const struct can_bittiming *bt = &priv->can.bittiming;
1183 const struct can_bittiming *dbt = &priv->can.data_bittiming;
1184 u16 brp, sjw, tseg1, tseg2;
1186 u32 ch = priv->channel;
1188 /* Nominal bit timing settings */
1191 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1192 tseg2 = bt->phase_seg2 - 1;
1194 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1195 /* CAN FD only mode */
1196 cfg = (RCANFD_NCFG_NTSEG1(tseg1) | RCANFD_NCFG_NBRP(brp) |
1197 RCANFD_NCFG_NSJW(sjw) | RCANFD_NCFG_NTSEG2(tseg2));
1199 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1200 netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1201 brp, sjw, tseg1, tseg2);
1203 /* Data bit timing settings */
1206 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1207 tseg2 = dbt->phase_seg2 - 1;
1209 cfg = (RCANFD_DCFG_DTSEG1(tseg1) | RCANFD_DCFG_DBRP(brp) |
1210 RCANFD_DCFG_DSJW(sjw) | RCANFD_DCFG_DTSEG2(tseg2));
1212 rcar_canfd_write(priv->base, RCANFD_F_DCFG(ch), cfg);
1213 netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1214 brp, sjw, tseg1, tseg2);
1216 /* Classical CAN only mode */
1217 cfg = (RCANFD_CFG_TSEG1(tseg1) | RCANFD_CFG_BRP(brp) |
1218 RCANFD_CFG_SJW(sjw) | RCANFD_CFG_TSEG2(tseg2));
1220 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1221 netdev_dbg(priv->ndev,
1222 "rate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1223 brp, sjw, tseg1, tseg2);
1227 static int rcar_canfd_start(struct net_device *ndev)
1229 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1230 int err = -EOPNOTSUPP;
1231 u32 sts, ch = priv->channel;
1232 u32 ridx = ch + RCANFD_RFFIFO_IDX;
1234 rcar_canfd_set_bittiming(ndev);
1236 rcar_canfd_enable_channel_interrupts(priv);
1238 /* Set channel to Operational mode */
1239 rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1240 RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_COPM);
1242 /* Verify channel mode change */
1243 err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1244 (sts & RCANFD_CSTS_COMSTS), 2, 500000);
1246 netdev_err(ndev, "channel %u communication state failed\n", ch);
1247 goto fail_mode_change;
1250 /* Enable Common & Rx FIFO */
1251 rcar_canfd_set_bit(priv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
1253 rcar_canfd_set_bit(priv->base, RCANFD_RFCC(ridx), RCANFD_RFCC_RFE);
1255 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1259 rcar_canfd_disable_channel_interrupts(priv);
1263 static int rcar_canfd_open(struct net_device *ndev)
1265 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1266 struct rcar_canfd_global *gpriv = priv->gpriv;
1269 /* Peripheral clock is already enabled in probe */
1270 err = clk_prepare_enable(gpriv->can_clk);
1272 netdev_err(ndev, "failed to enable CAN clock, error %d\n", err);
1276 err = open_candev(ndev);
1278 netdev_err(ndev, "open_candev() failed, error %d\n", err);
1282 napi_enable(&priv->napi);
1283 err = rcar_canfd_start(ndev);
1286 netif_start_queue(ndev);
1287 can_led_event(ndev, CAN_LED_EVENT_OPEN);
1290 napi_disable(&priv->napi);
1293 clk_disable_unprepare(gpriv->can_clk);
1298 static void rcar_canfd_stop(struct net_device *ndev)
1300 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1302 u32 sts, ch = priv->channel;
1303 u32 ridx = ch + RCANFD_RFFIFO_IDX;
1305 /* Transition to channel reset mode */
1306 rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1307 RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_CRESET);
1309 /* Check Channel reset mode */
1310 err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1311 (sts & RCANFD_CSTS_CRSTSTS), 2, 500000);
1313 netdev_err(ndev, "channel %u reset failed\n", ch);
1315 rcar_canfd_disable_channel_interrupts(priv);
1317 /* Disable Common & Rx FIFO */
1318 rcar_canfd_clear_bit(priv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
1320 rcar_canfd_clear_bit(priv->base, RCANFD_RFCC(ridx), RCANFD_RFCC_RFE);
1322 /* Set the state as STOPPED */
1323 priv->can.state = CAN_STATE_STOPPED;
1326 static int rcar_canfd_close(struct net_device *ndev)
1328 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1329 struct rcar_canfd_global *gpriv = priv->gpriv;
1331 netif_stop_queue(ndev);
1332 rcar_canfd_stop(ndev);
1333 napi_disable(&priv->napi);
1334 clk_disable_unprepare(gpriv->can_clk);
1336 can_led_event(ndev, CAN_LED_EVENT_STOP);
1340 static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
1341 struct net_device *ndev)
1343 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1344 struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1345 u32 sts = 0, id, dlc;
1346 unsigned long flags;
1347 u32 ch = priv->channel;
1349 if (can_dropped_invalid_skb(ndev, skb))
1350 return NETDEV_TX_OK;
1352 if (cf->can_id & CAN_EFF_FLAG) {
1353 id = cf->can_id & CAN_EFF_MASK;
1354 id |= RCANFD_CFID_CFIDE;
1356 id = cf->can_id & CAN_SFF_MASK;
1359 if (cf->can_id & CAN_RTR_FLAG)
1360 id |= RCANFD_CFID_CFRTR;
1362 dlc = RCANFD_CFPTR_CFDLC(can_len2dlc(cf->len));
1364 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1365 rcar_canfd_write(priv->base,
1366 RCANFD_F_CFID(ch, RCANFD_CFFIFO_IDX), id);
1367 rcar_canfd_write(priv->base,
1368 RCANFD_F_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
1370 if (can_is_canfd_skb(skb)) {
1371 /* CAN FD frame format */
1372 sts |= RCANFD_CFFDCSTS_CFFDF;
1373 if (cf->flags & CANFD_BRS)
1374 sts |= RCANFD_CFFDCSTS_CFBRS;
1376 if (priv->can.state == CAN_STATE_ERROR_PASSIVE)
1377 sts |= RCANFD_CFFDCSTS_CFESI;
1380 rcar_canfd_write(priv->base,
1381 RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), sts);
1383 rcar_canfd_put_data(priv, cf,
1384 RCANFD_F_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
1386 rcar_canfd_write(priv->base,
1387 RCANFD_C_CFID(ch, RCANFD_CFFIFO_IDX), id);
1388 rcar_canfd_write(priv->base,
1389 RCANFD_C_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
1390 rcar_canfd_put_data(priv, cf,
1391 RCANFD_C_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
1394 priv->tx_len[priv->tx_head % RCANFD_FIFO_DEPTH] = cf->len;
1395 can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH);
1397 spin_lock_irqsave(&priv->tx_lock, flags);
1400 /* Stop the queue if we've filled all FIFO entries */
1401 if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
1402 netif_stop_queue(ndev);
1404 /* Start Tx: Write 0xff to CFPC to increment the CPU-side
1405 * pointer for the Common FIFO
1407 rcar_canfd_write(priv->base,
1408 RCANFD_CFPCTR(ch, RCANFD_CFFIFO_IDX), 0xff);
1410 spin_unlock_irqrestore(&priv->tx_lock, flags);
1411 return NETDEV_TX_OK;
1414 static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
1416 struct net_device_stats *stats = &priv->ndev->stats;
1417 struct canfd_frame *cf;
1418 struct sk_buff *skb;
1419 u32 sts = 0, id, dlc;
1420 u32 ch = priv->channel;
1421 u32 ridx = ch + RCANFD_RFFIFO_IDX;
1423 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1424 id = rcar_canfd_read(priv->base, RCANFD_F_RFID(ridx));
1425 dlc = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(ridx));
1427 sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(ridx));
1428 if (sts & RCANFD_RFFDSTS_RFFDF)
1429 skb = alloc_canfd_skb(priv->ndev, &cf);
1431 skb = alloc_can_skb(priv->ndev,
1432 (struct can_frame **)&cf);
1434 id = rcar_canfd_read(priv->base, RCANFD_C_RFID(ridx));
1435 dlc = rcar_canfd_read(priv->base, RCANFD_C_RFPTR(ridx));
1436 skb = alloc_can_skb(priv->ndev, (struct can_frame **)&cf);
1440 stats->rx_dropped++;
1444 if (id & RCANFD_RFID_RFIDE)
1445 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
1447 cf->can_id = id & CAN_SFF_MASK;
1449 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1450 if (sts & RCANFD_RFFDSTS_RFFDF)
1451 cf->len = can_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1453 cf->len = get_can_dlc(RCANFD_RFPTR_RFDLC(dlc));
1455 if (sts & RCANFD_RFFDSTS_RFESI) {
1456 cf->flags |= CANFD_ESI;
1457 netdev_dbg(priv->ndev, "ESI Error\n");
1460 if (!(sts & RCANFD_RFFDSTS_RFFDF) && (id & RCANFD_RFID_RFRTR)) {
1461 cf->can_id |= CAN_RTR_FLAG;
1463 if (sts & RCANFD_RFFDSTS_RFBRS)
1464 cf->flags |= CANFD_BRS;
1466 rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(ridx, 0));
1469 cf->len = get_can_dlc(RCANFD_RFPTR_RFDLC(dlc));
1470 if (id & RCANFD_RFID_RFRTR)
1471 cf->can_id |= CAN_RTR_FLAG;
1473 rcar_canfd_get_data(priv, cf, RCANFD_C_RFDF(ridx, 0));
1476 /* Write 0xff to RFPC to increment the CPU-side
1477 * pointer of the Rx FIFO
1479 rcar_canfd_write(priv->base, RCANFD_RFPCTR(ridx), 0xff);
1481 can_led_event(priv->ndev, CAN_LED_EVENT_RX);
1483 stats->rx_bytes += cf->len;
1484 stats->rx_packets++;
1485 netif_receive_skb(skb);
1488 static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
1490 struct rcar_canfd_channel *priv =
1491 container_of(napi, struct rcar_canfd_channel, napi);
1494 u32 ch = priv->channel;
1495 u32 ridx = ch + RCANFD_RFFIFO_IDX;
1497 for (num_pkts = 0; num_pkts < quota; num_pkts++) {
1498 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
1499 /* Check FIFO empty condition */
1500 if (sts & RCANFD_RFSTS_RFEMP)
1503 rcar_canfd_rx_pkt(priv);
1505 /* Clear interrupt bit */
1506 if (sts & RCANFD_RFSTS_RFIF)
1507 rcar_canfd_write(priv->base, RCANFD_RFSTS(ridx),
1508 sts & ~RCANFD_RFSTS_RFIF);
1511 /* All packets processed */
1512 if (num_pkts < quota) {
1513 if (napi_complete_done(napi, num_pkts)) {
1514 /* Enable Rx FIFO interrupts */
1515 rcar_canfd_set_bit(priv->base, RCANFD_RFCC(ridx),
1522 static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
1527 case CAN_MODE_START:
1528 err = rcar_canfd_start(ndev);
1531 netif_wake_queue(ndev);
1538 static int rcar_canfd_get_berr_counter(const struct net_device *dev,
1539 struct can_berr_counter *bec)
1541 struct rcar_canfd_channel *priv = netdev_priv(dev);
1542 u32 val, ch = priv->channel;
1544 /* Peripheral clock is already enabled in probe */
1545 val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1546 bec->txerr = RCANFD_CSTS_TECCNT(val);
1547 bec->rxerr = RCANFD_CSTS_RECCNT(val);
1551 static const struct net_device_ops rcar_canfd_netdev_ops = {
1552 .ndo_open = rcar_canfd_open,
1553 .ndo_stop = rcar_canfd_close,
1554 .ndo_start_xmit = rcar_canfd_start_xmit,
1555 .ndo_change_mtu = can_change_mtu,
1558 static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
1561 struct platform_device *pdev = gpriv->pdev;
1562 struct rcar_canfd_channel *priv;
1563 struct net_device *ndev;
1566 ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
1568 dev_err(&pdev->dev, "alloc_candev() failed\n");
1572 priv = netdev_priv(ndev);
1574 ndev->netdev_ops = &rcar_canfd_netdev_ops;
1575 ndev->flags |= IFF_ECHO;
1577 priv->base = gpriv->base;
1579 priv->can.clock.freq = fcan_freq;
1580 dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
1582 if (gpriv->fdmode) {
1583 priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
1584 priv->can.data_bittiming_const =
1585 &rcar_canfd_data_bittiming_const;
1587 /* Controller starts in CAN FD only mode */
1588 can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD);
1589 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1591 /* Controller starts in Classical CAN only mode */
1592 priv->can.bittiming_const = &rcar_canfd_bittiming_const;
1593 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1596 priv->can.do_set_mode = rcar_canfd_do_set_mode;
1597 priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
1598 priv->gpriv = gpriv;
1599 SET_NETDEV_DEV(ndev, &pdev->dev);
1601 netif_napi_add(ndev, &priv->napi, rcar_canfd_rx_poll,
1602 RCANFD_NAPI_WEIGHT);
1603 spin_lock_init(&priv->tx_lock);
1604 devm_can_led_init(ndev);
1605 gpriv->ch[priv->channel] = priv;
1606 err = register_candev(ndev);
1609 "register_candev() failed, error %d\n", err);
1612 dev_info(&pdev->dev, "device registered (channel %u)\n", priv->channel);
1616 netif_napi_del(&priv->napi);
1622 static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
1624 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1627 unregister_candev(priv->ndev);
1628 netif_napi_del(&priv->napi);
1629 free_candev(priv->ndev);
1633 static int rcar_canfd_probe(struct platform_device *pdev)
1636 u32 sts, ch, fcan_freq;
1637 struct rcar_canfd_global *gpriv;
1638 struct device_node *of_child;
1639 unsigned long channels_mask = 0;
1640 int err, ch_irq, g_irq;
1641 bool fdmode = true; /* CAN FD only mode - default */
1643 if (of_property_read_bool(pdev->dev.of_node, "renesas,no-can-fd"))
1644 fdmode = false; /* Classical CAN only mode */
1646 of_child = of_get_child_by_name(pdev->dev.of_node, "channel0");
1647 if (of_child && of_device_is_available(of_child))
1648 channels_mask |= BIT(0); /* Channel 0 */
1650 of_child = of_get_child_by_name(pdev->dev.of_node, "channel1");
1651 if (of_child && of_device_is_available(of_child))
1652 channels_mask |= BIT(1); /* Channel 1 */
1654 ch_irq = platform_get_irq(pdev, 0);
1660 g_irq = platform_get_irq(pdev, 1);
1666 /* Global controller context */
1667 gpriv = devm_kzalloc(&pdev->dev, sizeof(*gpriv), GFP_KERNEL);
1673 gpriv->channels_mask = channels_mask;
1674 gpriv->fdmode = fdmode;
1676 /* Peripheral clock */
1677 gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
1678 if (IS_ERR(gpriv->clkp)) {
1679 err = PTR_ERR(gpriv->clkp);
1680 dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n",
1685 /* fCAN clock: Pick External clock. If not available fallback to
1688 gpriv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
1689 if (IS_ERR(gpriv->can_clk) || (clk_get_rate(gpriv->can_clk) == 0)) {
1690 gpriv->can_clk = devm_clk_get(&pdev->dev, "canfd");
1691 if (IS_ERR(gpriv->can_clk)) {
1692 err = PTR_ERR(gpriv->can_clk);
1694 "cannot get canfd clock, error %d\n", err);
1697 gpriv->fcan = RCANFD_CANFDCLK;
1700 gpriv->fcan = RCANFD_EXTCLK;
1702 fcan_freq = clk_get_rate(gpriv->can_clk);
1704 if (gpriv->fcan == RCANFD_CANFDCLK)
1705 /* CANFD clock is further divided by (1/2) within the IP */
1708 addr = devm_platform_ioremap_resource(pdev, 0);
1710 err = PTR_ERR(addr);
1715 /* Request IRQ that's common for both channels */
1716 err = devm_request_irq(&pdev->dev, ch_irq,
1717 rcar_canfd_channel_interrupt, 0,
1718 "canfd.chn", gpriv);
1720 dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1724 err = devm_request_irq(&pdev->dev, g_irq,
1725 rcar_canfd_global_interrupt, 0,
1726 "canfd.gbl", gpriv);
1728 dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1733 /* Enable peripheral clock for register access */
1734 err = clk_prepare_enable(gpriv->clkp);
1737 "failed to enable peripheral clock, error %d\n", err);
1741 err = rcar_canfd_reset_controller(gpriv);
1743 dev_err(&pdev->dev, "reset controller failed\n");
1747 /* Controller in Global reset & Channel reset mode */
1748 rcar_canfd_configure_controller(gpriv);
1750 /* Configure per channel attributes */
1751 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1752 /* Configure Channel's Rx fifo */
1753 rcar_canfd_configure_rx(gpriv, ch);
1755 /* Configure Channel's Tx (Common) fifo */
1756 rcar_canfd_configure_tx(gpriv, ch);
1758 /* Configure receive rules */
1759 rcar_canfd_configure_afl_rules(gpriv, ch);
1762 /* Configure common interrupts */
1763 rcar_canfd_enable_global_interrupts(gpriv);
1765 /* Start Global operation mode */
1766 rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GMDC_MASK,
1767 RCANFD_GCTR_GMDC_GOPM);
1769 /* Verify mode change */
1770 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
1771 !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
1773 dev_err(&pdev->dev, "global operational mode failed\n");
1777 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1778 err = rcar_canfd_channel_probe(gpriv, ch, fcan_freq);
1783 platform_set_drvdata(pdev, gpriv);
1784 dev_info(&pdev->dev, "global operational state (clk %d, fdmode %d)\n",
1785 gpriv->fcan, gpriv->fdmode);
1789 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
1790 rcar_canfd_channel_remove(gpriv, ch);
1792 rcar_canfd_disable_global_interrupts(gpriv);
1794 clk_disable_unprepare(gpriv->clkp);
1799 static int rcar_canfd_remove(struct platform_device *pdev)
1801 struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
1804 rcar_canfd_reset_controller(gpriv);
1805 rcar_canfd_disable_global_interrupts(gpriv);
1807 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1808 rcar_canfd_disable_channel_interrupts(gpriv->ch[ch]);
1809 rcar_canfd_channel_remove(gpriv, ch);
1812 /* Enter global sleep mode */
1813 rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
1814 clk_disable_unprepare(gpriv->clkp);
1818 static int __maybe_unused rcar_canfd_suspend(struct device *dev)
1823 static int __maybe_unused rcar_canfd_resume(struct device *dev)
1828 static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
1831 static const struct of_device_id rcar_canfd_of_table[] = {
1832 { .compatible = "renesas,rcar-gen3-canfd" },
1836 MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
1838 static struct platform_driver rcar_canfd_driver = {
1840 .name = RCANFD_DRV_NAME,
1841 .of_match_table = of_match_ptr(rcar_canfd_of_table),
1842 .pm = &rcar_canfd_pm_ops,
1844 .probe = rcar_canfd_probe,
1845 .remove = rcar_canfd_remove,
1848 module_platform_driver(rcar_canfd_driver);
1850 MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
1851 MODULE_LICENSE("GPL");
1852 MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
1853 MODULE_ALIAS("platform:" RCANFD_DRV_NAME);