2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/mlx5/device.h>
37 #include <linux/mlx5/driver.h>
39 #define MLX5_INVALID_LKEY 0x100
40 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5)
41 #define MLX5_DIF_SIZE 8
42 #define MLX5_STRIDE_BLOCK_OP 0x400
43 #define MLX5_CPY_GRD_MASK 0xc0
44 #define MLX5_CPY_APP_MASK 0x30
45 #define MLX5_CPY_REF_MASK 0x0f
46 #define MLX5_BSF_INC_REFTAG (1 << 6)
47 #define MLX5_BSF_INL_VALID (1 << 15)
48 #define MLX5_BSF_REFRESH_DIF (1 << 14)
49 #define MLX5_BSF_REPEAT_BLOCK (1 << 7)
50 #define MLX5_BSF_APPTAG_ESCAPE 0x1
51 #define MLX5_BSF_APPREF_ESCAPE 0x2
53 #define MLX5_QPN_BITS 24
54 #define MLX5_QPN_MASK ((1 << MLX5_QPN_BITS) - 1)
57 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
58 MLX5_QP_OPTPAR_RRE = 1 << 1,
59 MLX5_QP_OPTPAR_RAE = 1 << 2,
60 MLX5_QP_OPTPAR_RWE = 1 << 3,
61 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
62 MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
63 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
64 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
65 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
66 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
67 MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
68 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
69 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
70 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
71 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
72 MLX5_QP_OPTPAR_SRQN = 1 << 18,
73 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
74 MLX5_QP_OPTPAR_DC_HS = 1 << 20,
75 MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
79 MLX5_QP_STATE_RST = 0,
80 MLX5_QP_STATE_INIT = 1,
81 MLX5_QP_STATE_RTR = 2,
82 MLX5_QP_STATE_RTS = 3,
83 MLX5_QP_STATE_SQER = 4,
84 MLX5_QP_STATE_SQD = 5,
85 MLX5_QP_STATE_ERR = 6,
86 MLX5_QP_STATE_SQ_DRAINING = 7,
87 MLX5_QP_STATE_SUSPENDED = 9,
100 MLX5_QP_ST_QP1 = 0x8,
101 MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
102 MLX5_QP_ST_RAW_IPV6 = 0xa,
103 MLX5_QP_ST_SNIFFER = 0xb,
104 MLX5_QP_ST_SYNC_UMR = 0xe,
105 MLX5_QP_ST_PTP_1588 = 0xd,
106 MLX5_QP_ST_REG_UMR = 0xc,
111 MLX5_QP_PM_MIGRATED = 0x3,
112 MLX5_QP_PM_ARMED = 0x0,
113 MLX5_QP_PM_REARM = 0x1
117 MLX5_NON_ZERO_RQ = 0 << 24,
118 MLX5_SRQ_RQ = 1 << 24,
119 MLX5_CRQ_RQ = 2 << 24,
120 MLX5_ZERO_LEN_RQ = 3 << 24
125 MLX5_QP_BIT_SRE = 1 << 15,
126 MLX5_QP_BIT_SWE = 1 << 14,
127 MLX5_QP_BIT_SAE = 1 << 13,
129 MLX5_QP_BIT_RRE = 1 << 15,
130 MLX5_QP_BIT_RWE = 1 << 14,
131 MLX5_QP_BIT_RAE = 1 << 13,
132 MLX5_QP_BIT_RIC = 1 << 4,
136 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
137 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
138 MLX5_WQE_CTRL_SOLICITED = 1 << 1,
142 MLX5_SEND_WQE_DS = 16,
143 MLX5_SEND_WQE_BB = 64,
146 #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
149 MLX5_SEND_WQE_MAX_WQEBBS = 16,
153 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
154 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
155 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
156 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
157 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31
161 MLX5_FENCE_MODE_NONE = 0 << 5,
162 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
163 MLX5_FENCE_MODE_FENCE = 2 << 5,
164 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
165 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
169 MLX5_QP_LAT_SENSITIVE = 1 << 28,
170 MLX5_QP_BLOCK_MCAST = 1 << 30,
171 MLX5_QP_ENABLE_SIG = 1 << 31,
180 MLX5_FLAGS_INLINE = 1<<7,
181 MLX5_FLAGS_CHECK_FREE = 1<<5,
184 struct mlx5_wqe_fmr_seg {
195 struct mlx5_wqe_ctrl_seg {
196 __be32 opmod_idx_opcode;
204 #define MLX5_WQE_CTRL_DS_MASK 0x3f
205 #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00
206 #define MLX5_WQE_CTRL_QPN_SHIFT 8
207 #define MLX5_WQE_DS_UNITS 16
208 #define MLX5_WQE_CTRL_OPCODE_MASK 0xff
209 #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
210 #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8
213 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4,
214 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5,
215 MLX5_ETH_WQE_L3_CSUM = 1 << 6,
216 MLX5_ETH_WQE_L4_CSUM = 1 << 7,
219 struct mlx5_wqe_eth_seg {
225 __be16 inline_hdr_sz;
226 u8 inline_hdr_start[2];
229 struct mlx5_wqe_xrc_seg {
234 struct mlx5_wqe_masked_atomic_seg {
237 __be64 swap_add_mask;
260 struct mlx5_wqe_datagram_seg {
264 struct mlx5_wqe_raddr_seg {
270 struct mlx5_wqe_atomic_seg {
275 struct mlx5_wqe_data_seg {
281 struct mlx5_wqe_umr_ctrl_seg {
284 __be16 klm_octowords;
285 __be16 bsf_octowords;
290 struct mlx5_seg_set_psv {
294 __be32 transient_sig;
298 struct mlx5_seg_get_psv {
306 struct mlx5_seg_check_psv {
308 __be16 err_coalescing_op;
312 __be16 xport_err_mask;
320 struct mlx5_rwqe_sig {
326 struct mlx5_wqe_signature_seg {
332 #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff
334 struct mlx5_wqe_inline_seg {
343 struct mlx5_bsf_inl {
350 u8 dif_inc_ref_guard_check;
351 __be16 dif_app_bitmask_check;
355 struct mlx5_bsf_basic {
367 __be32 raw_data_size;
371 struct mlx5_bsf_ext {
372 __be32 t_init_gen_pro_size;
373 __be32 rsvd_epi_size;
377 struct mlx5_bsf_inl w_inl;
378 struct mlx5_bsf_inl m_inl;
387 struct mlx5_stride_block_entry {
394 struct mlx5_stride_block_ctrl_seg {
395 __be32 bcount_per_cycle;
402 enum mlx5_pagefault_flags {
403 MLX5_PFAULT_REQUESTOR = 1 << 0,
404 MLX5_PFAULT_WRITE = 1 << 1,
405 MLX5_PFAULT_RDMA = 1 << 2,
408 /* Contains the details of a pagefault. */
409 struct mlx5_pagefault {
412 enum mlx5_pagefault_flags flags;
414 /* Initiator or send message responder pagefault details. */
416 /* Received packet size, only valid for responders. */
419 * WQE index. Refers to either the send queue or
420 * receive queue, according to event_subtype.
424 /* RDMA responder pagefault details */
428 * Received packet size, minimal size page fault
429 * resolution required for forward progress.
438 struct mlx5_core_qp {
439 struct mlx5_core_rsc_common common; /* must be first */
440 void (*event) (struct mlx5_core_qp *, int);
441 void (*pfault_handler)(struct mlx5_core_qp *, struct mlx5_pagefault *);
443 struct mlx5_rsc_debug *dbg;
447 struct mlx5_qp_path {
459 __be32 tclass_flowlabel;
467 struct mlx5_qp_context {
473 __be32 qp_counter_set_usr_page;
475 __be32 log_pg_sz_remote_qpn;
476 struct mlx5_qp_path pri_path;
477 struct mlx5_qp_path alt_path;
480 __be32 next_send_psn;
483 __be32 last_acked_psn;
486 __be32 rnr_nextrecvpsn;
493 __be16 hw_sq_wqe_counter;
494 __be16 sw_sq_wqe_counter;
495 __be16 hw_rcyclic_byte_counter;
496 __be16 hw_rq_counter;
497 __be16 sw_rcyclic_byte_counter;
498 __be16 sw_rq_counter;
503 __be64 dc_access_key;
507 struct mlx5_create_qp_mbox_in {
508 struct mlx5_inbox_hdr hdr;
511 __be32 opt_param_mask;
513 struct mlx5_qp_context ctx;
518 struct mlx5_create_qp_mbox_out {
519 struct mlx5_outbox_hdr hdr;
524 struct mlx5_destroy_qp_mbox_in {
525 struct mlx5_inbox_hdr hdr;
530 struct mlx5_destroy_qp_mbox_out {
531 struct mlx5_outbox_hdr hdr;
535 struct mlx5_modify_qp_mbox_in {
536 struct mlx5_inbox_hdr hdr;
541 struct mlx5_qp_context ctx;
545 struct mlx5_modify_qp_mbox_out {
546 struct mlx5_outbox_hdr hdr;
550 struct mlx5_query_qp_mbox_in {
551 struct mlx5_inbox_hdr hdr;
556 struct mlx5_query_qp_mbox_out {
557 struct mlx5_outbox_hdr hdr;
561 struct mlx5_qp_context ctx;
566 struct mlx5_conf_sqp_mbox_in {
567 struct mlx5_inbox_hdr hdr;
573 struct mlx5_conf_sqp_mbox_out {
574 struct mlx5_outbox_hdr hdr;
578 struct mlx5_alloc_xrcd_mbox_in {
579 struct mlx5_inbox_hdr hdr;
583 struct mlx5_alloc_xrcd_mbox_out {
584 struct mlx5_outbox_hdr hdr;
589 struct mlx5_dealloc_xrcd_mbox_in {
590 struct mlx5_inbox_hdr hdr;
595 struct mlx5_dealloc_xrcd_mbox_out {
596 struct mlx5_outbox_hdr hdr;
600 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
602 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
605 static inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key)
607 return radix_tree_lookup(&dev->priv.mr_table.tree, key);
610 struct mlx5_page_fault_resume_mbox_in {
611 struct mlx5_inbox_hdr hdr;
616 struct mlx5_page_fault_resume_mbox_out {
617 struct mlx5_outbox_hdr hdr;
621 int mlx5_core_create_qp(struct mlx5_core_dev *dev,
622 struct mlx5_core_qp *qp,
623 struct mlx5_create_qp_mbox_in *in,
625 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state,
626 enum mlx5_qp_state new_state,
627 struct mlx5_modify_qp_mbox_in *in, int sqd_event,
628 struct mlx5_core_qp *qp);
629 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
630 struct mlx5_core_qp *qp);
631 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
632 struct mlx5_query_qp_mbox_out *out, int outlen);
634 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
635 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
636 void mlx5_init_qp_table(struct mlx5_core_dev *dev);
637 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
638 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
639 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
640 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
641 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 qpn,
642 u8 context, int error);
645 static inline const char *mlx5_qp_type_str(int type)
648 case MLX5_QP_ST_RC: return "RC";
649 case MLX5_QP_ST_UC: return "C";
650 case MLX5_QP_ST_UD: return "UD";
651 case MLX5_QP_ST_XRC: return "XRC";
652 case MLX5_QP_ST_MLX: return "MLX";
653 case MLX5_QP_ST_QP0: return "QP0";
654 case MLX5_QP_ST_QP1: return "QP1";
655 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
656 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
657 case MLX5_QP_ST_SNIFFER: return "SNIFFER";
658 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
659 case MLX5_QP_ST_PTP_1588: return "PTP_1588";
660 case MLX5_QP_ST_REG_UMR: return "REG_UMR";
661 default: return "Invalid transport type";
665 static inline const char *mlx5_qp_state_str(int state)
668 case MLX5_QP_STATE_RST:
670 case MLX5_QP_STATE_INIT:
672 case MLX5_QP_STATE_RTR:
674 case MLX5_QP_STATE_RTS:
676 case MLX5_QP_STATE_SQER:
678 case MLX5_QP_STATE_SQD:
680 case MLX5_QP_STATE_ERR:
682 case MLX5_QP_STATE_SQ_DRAINING:
683 return "SQ_DRAINING";
684 case MLX5_QP_STATE_SUSPENDED:
686 default: return "Invalid QP state";
690 #endif /* MLX5_QP_H */