2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/log2.h>
35 #include <linux/etherdevice.h>
37 #include <linux/slab.h>
38 #include <linux/netdevice.h>
39 #include <linux/vmalloc.h>
41 #include <rdma/ib_cache.h>
42 #include <rdma/ib_pack.h>
43 #include <rdma/ib_addr.h>
44 #include <rdma/ib_mad.h>
46 #include <linux/mlx4/driver.h>
47 #include <linux/mlx4/qp.h>
50 #include <rdma/mlx4-abi.h>
52 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
53 struct mlx4_ib_cq *recv_cq);
54 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
55 struct mlx4_ib_cq *recv_cq);
58 MLX4_IB_ACK_REQ_FREQ = 8,
62 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
63 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
64 MLX4_IB_LINK_TYPE_IB = 0,
65 MLX4_IB_LINK_TYPE_ETH = 1
70 * Largest possible UD header: send with GRH and immediate
71 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
72 * tag. (LRH would only use 8 bytes, so Ethernet is the
75 MLX4_IB_UD_HEADER_SIZE = 82,
76 MLX4_IB_LSO_HEADER_SPARE = 128,
80 MLX4_IB_IBOE_ETHERTYPE = 0x8915
88 struct ib_ud_header ud_header;
89 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
90 struct ib_qp *roce_v2_gsi;
94 MLX4_IB_MIN_SQ_STRIDE = 6,
95 MLX4_IB_CACHE_LINE_SIZE = 64,
100 MLX4_RAW_QP_MSGMAX = 31,
107 static const __be32 mlx4_ib_opcode[] = {
108 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
109 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
110 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
111 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
112 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
113 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
114 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
115 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
116 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
117 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
118 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
119 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
120 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
123 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
125 return container_of(mqp, struct mlx4_ib_sqp, qp);
128 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
130 if (!mlx4_is_master(dev->dev))
133 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
134 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
138 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
143 /* PPF or Native -- real SQP */
144 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
145 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
146 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
149 /* VF or PF -- proxy SQP */
150 if (mlx4_is_mfunc(dev->dev)) {
151 for (i = 0; i < dev->dev->caps.num_ports; i++) {
152 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
153 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
162 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
165 /* used for INIT/CLOSE port logic */
166 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
171 /* PPF or Native -- real QP0 */
172 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
173 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
174 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
177 /* VF or PF -- proxy QP0 */
178 if (mlx4_is_mfunc(dev->dev)) {
179 for (i = 0; i < dev->dev->caps.num_ports; i++) {
180 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
189 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
191 return mlx4_buf_offset(&qp->buf, offset);
194 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
196 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
199 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
201 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
205 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
206 * first four bytes of every 64 byte chunk with
207 * 0x7FFFFFF | (invalid_ownership_value << 31).
209 * When the max work request size is less than or equal to the WQE
210 * basic block size, as an optimization, we can stamp all WQEs with
211 * 0xffffffff, and skip the very first chunk of each WQE.
213 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
221 struct mlx4_wqe_ctrl_seg *ctrl;
223 if (qp->sq_max_wqes_per_wr > 1) {
224 s = roundup(size, 1U << qp->sq.wqe_shift);
225 for (i = 0; i < s; i += 64) {
226 ind = (i >> qp->sq.wqe_shift) + n;
227 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
228 cpu_to_be32(0xffffffff);
229 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
230 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
234 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
235 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
236 for (i = 64; i < s; i += 64) {
238 *wqe = cpu_to_be32(0xffffffff);
243 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
245 struct mlx4_wqe_ctrl_seg *ctrl;
246 struct mlx4_wqe_inline_seg *inl;
250 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
251 s = sizeof(struct mlx4_wqe_ctrl_seg);
253 if (qp->ibqp.qp_type == IB_QPT_UD) {
254 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
255 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
256 memset(dgram, 0, sizeof *dgram);
257 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
258 s += sizeof(struct mlx4_wqe_datagram_seg);
261 /* Pad the remainder of the WQE with an inline data segment. */
264 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
266 ctrl->srcrb_flags = 0;
267 ctrl->qpn_vlan.fence_size = size / 16;
269 * Make sure descriptor is fully written before setting ownership bit
270 * (because HW can start executing as soon as we do).
274 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
275 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
277 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
280 /* Post NOP WQE to prevent wrap-around in the middle of WR */
281 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
283 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
284 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
285 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
291 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
293 struct ib_event event;
294 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
296 if (type == MLX4_EVENT_TYPE_PATH_MIG)
297 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
299 if (ibqp->event_handler) {
300 event.device = ibqp->device;
301 event.element.qp = ibqp;
303 case MLX4_EVENT_TYPE_PATH_MIG:
304 event.event = IB_EVENT_PATH_MIG;
306 case MLX4_EVENT_TYPE_COMM_EST:
307 event.event = IB_EVENT_COMM_EST;
309 case MLX4_EVENT_TYPE_SQ_DRAINED:
310 event.event = IB_EVENT_SQ_DRAINED;
312 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
313 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
315 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
316 event.event = IB_EVENT_QP_FATAL;
318 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
319 event.event = IB_EVENT_PATH_MIG_ERR;
321 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
322 event.event = IB_EVENT_QP_REQ_ERR;
324 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
325 event.event = IB_EVENT_QP_ACCESS_ERR;
328 pr_warn("Unexpected event type %d "
329 "on QP %06x\n", type, qp->qpn);
333 ibqp->event_handler(&event, ibqp->qp_context);
337 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
340 * UD WQEs must have a datagram segment.
341 * RC and UC WQEs might have a remote address segment.
342 * MLX WQEs need two extra inline data segments (for the UD
343 * header and space for the ICRC).
347 return sizeof (struct mlx4_wqe_ctrl_seg) +
348 sizeof (struct mlx4_wqe_datagram_seg) +
349 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
350 case MLX4_IB_QPT_PROXY_SMI_OWNER:
351 case MLX4_IB_QPT_PROXY_SMI:
352 case MLX4_IB_QPT_PROXY_GSI:
353 return sizeof (struct mlx4_wqe_ctrl_seg) +
354 sizeof (struct mlx4_wqe_datagram_seg) + 64;
355 case MLX4_IB_QPT_TUN_SMI_OWNER:
356 case MLX4_IB_QPT_TUN_GSI:
357 return sizeof (struct mlx4_wqe_ctrl_seg) +
358 sizeof (struct mlx4_wqe_datagram_seg);
361 return sizeof (struct mlx4_wqe_ctrl_seg) +
362 sizeof (struct mlx4_wqe_raddr_seg);
364 return sizeof (struct mlx4_wqe_ctrl_seg) +
365 sizeof (struct mlx4_wqe_masked_atomic_seg) +
366 sizeof (struct mlx4_wqe_raddr_seg);
367 case MLX4_IB_QPT_SMI:
368 case MLX4_IB_QPT_GSI:
369 return sizeof (struct mlx4_wqe_ctrl_seg) +
370 ALIGN(MLX4_IB_UD_HEADER_SIZE +
371 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
373 sizeof (struct mlx4_wqe_inline_seg),
374 sizeof (struct mlx4_wqe_data_seg)) +
376 sizeof (struct mlx4_wqe_inline_seg),
377 sizeof (struct mlx4_wqe_data_seg));
379 return sizeof (struct mlx4_wqe_ctrl_seg);
383 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
384 int is_user, int has_rq, struct mlx4_ib_qp *qp)
386 /* Sanity check RQ size before proceeding */
387 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
388 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
392 if (cap->max_recv_wr)
395 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
397 /* HW requires >= 1 RQ entry with >= 1 gather entry */
398 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
401 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
402 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
403 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
406 /* leave userspace return values as they were, so as not to break ABI */
408 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
409 cap->max_recv_sge = qp->rq.max_gs;
411 cap->max_recv_wr = qp->rq.max_post =
412 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
413 cap->max_recv_sge = min(qp->rq.max_gs,
414 min(dev->dev->caps.max_sq_sg,
415 dev->dev->caps.max_rq_sg));
421 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
422 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp,
427 /* Sanity check SQ size before proceeding */
428 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
429 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
430 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
431 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
435 * For MLX transport we need 2 extra S/G entries:
436 * one for the header and one for the checksum at the end
438 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
439 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
440 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
443 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
444 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
445 send_wqe_overhead(type, qp->flags);
447 if (s > dev->dev->caps.max_sq_desc_sz)
451 * Hermon supports shrinking WQEs, such that a single work
452 * request can include multiple units of 1 << wqe_shift. This
453 * way, work requests can differ in size, and do not have to
454 * be a power of 2 in size, saving memory and speeding up send
455 * WR posting. Unfortunately, if we do this then the
456 * wqe_index field in CQEs can't be used to look up the WR ID
457 * anymore, so we do this only if selective signaling is off.
459 * Further, on 32-bit platforms, we can't use vmap() to make
460 * the QP buffer virtually contiguous. Thus we have to use
461 * constant-sized WRs to make sure a WR is always fully within
462 * a single page-sized chunk.
464 * Finally, we use NOP work requests to pad the end of the
465 * work queue, to avoid wrap-around in the middle of WR. We
466 * set NEC bit to avoid getting completions with error for
467 * these NOP WRs, but since NEC is only supported starting
468 * with firmware 2.2.232, we use constant-sized WRs for older
471 * And, since MLX QPs only support SEND, we use constant-sized
474 * We look for the smallest value of wqe_shift such that the
475 * resulting number of wqes does not exceed device
478 * We set WQE size to at least 64 bytes, this way stamping
479 * invalidates each WQE.
481 if (shrink_wqe && dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
482 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
483 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
484 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
485 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
486 qp->sq.wqe_shift = ilog2(64);
488 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
491 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
494 * We need to leave 2 KB + 1 WR of headroom in the SQ to
495 * allow HW to prefetch.
497 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
498 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
499 qp->sq_max_wqes_per_wr +
502 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
505 if (qp->sq_max_wqes_per_wr <= 1)
511 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
512 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
513 send_wqe_overhead(type, qp->flags)) /
514 sizeof (struct mlx4_wqe_data_seg);
516 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
517 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
518 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
520 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
522 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
526 cap->max_send_wr = qp->sq.max_post =
527 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
528 cap->max_send_sge = min(qp->sq.max_gs,
529 min(dev->dev->caps.max_sq_sg,
530 dev->dev->caps.max_rq_sg));
531 /* We don't support inline sends for kernel QPs (yet) */
532 cap->max_inline_data = 0;
537 static int set_user_sq_size(struct mlx4_ib_dev *dev,
538 struct mlx4_ib_qp *qp,
539 struct mlx4_ib_create_qp *ucmd)
541 /* Sanity check SQ size before proceeding */
542 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
543 ucmd->log_sq_stride >
544 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
545 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
548 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
549 qp->sq.wqe_shift = ucmd->log_sq_stride;
551 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
552 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
557 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
562 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
564 if (!qp->sqp_proxy_rcv)
566 for (i = 0; i < qp->rq.wqe_cnt; i++) {
567 qp->sqp_proxy_rcv[i].addr =
568 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
570 if (!qp->sqp_proxy_rcv[i].addr)
572 qp->sqp_proxy_rcv[i].map =
573 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
574 sizeof (struct mlx4_ib_proxy_sqp_hdr),
576 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
577 kfree(qp->sqp_proxy_rcv[i].addr);
586 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
587 sizeof (struct mlx4_ib_proxy_sqp_hdr),
589 kfree(qp->sqp_proxy_rcv[i].addr);
591 kfree(qp->sqp_proxy_rcv);
592 qp->sqp_proxy_rcv = NULL;
596 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
600 for (i = 0; i < qp->rq.wqe_cnt; i++) {
601 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
602 sizeof (struct mlx4_ib_proxy_sqp_hdr),
604 kfree(qp->sqp_proxy_rcv[i].addr);
606 kfree(qp->sqp_proxy_rcv);
609 static int qp_has_rq(struct ib_qp_init_attr *attr)
611 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
617 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
620 for (i = 0; i < dev->caps.num_ports; i++) {
621 if (qpn == dev->caps.qp0_proxy[i])
622 return !!dev->caps.qp0_qkey[i];
627 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
628 struct mlx4_ib_qp *qp)
630 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
631 mlx4_counter_free(dev->dev, qp->counter_index->index);
632 list_del(&qp->counter_index->list);
633 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
635 kfree(qp->counter_index);
636 qp->counter_index = NULL;
639 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
640 struct ib_qp_init_attr *init_attr,
641 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
646 struct ib_qp_cap backup_cap;
647 struct mlx4_ib_sqp *sqp;
648 struct mlx4_ib_qp *qp;
649 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
650 struct mlx4_ib_cq *mcq;
653 /* When tunneling special qps, we use a plain UD qp */
655 if (mlx4_is_mfunc(dev->dev) &&
656 (!mlx4_is_master(dev->dev) ||
657 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
658 if (init_attr->qp_type == IB_QPT_GSI)
659 qp_type = MLX4_IB_QPT_PROXY_GSI;
661 if (mlx4_is_master(dev->dev) ||
662 qp0_enabled_vf(dev->dev, sqpn))
663 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
665 qp_type = MLX4_IB_QPT_PROXY_SMI;
669 /* add extra sg entry for tunneling */
670 init_attr->cap.max_recv_sge++;
671 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
672 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
673 container_of(init_attr,
674 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
675 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
676 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
677 !mlx4_is_master(dev->dev))
679 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
680 qp_type = MLX4_IB_QPT_TUN_GSI;
681 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
682 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
684 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
686 qp_type = MLX4_IB_QPT_TUN_SMI;
687 /* we are definitely in the PPF here, since we are creating
688 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
689 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
690 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
695 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
696 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
697 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
698 sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
702 qp->pri.vid = 0xFFFF;
703 qp->alt.vid = 0xFFFF;
705 qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
708 qp->pri.vid = 0xFFFF;
709 qp->alt.vid = 0xFFFF;
714 qp->mlx4_ib_qp_type = qp_type;
716 mutex_init(&qp->mutex);
717 spin_lock_init(&qp->sq.lock);
718 spin_lock_init(&qp->rq.lock);
719 INIT_LIST_HEAD(&qp->gid_list);
720 INIT_LIST_HEAD(&qp->steering_rules);
722 qp->state = IB_QPS_RESET;
723 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
724 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
726 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
731 struct mlx4_ib_create_qp ucmd;
733 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
738 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
740 err = set_user_sq_size(dev, qp, &ucmd);
744 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
746 if (IS_ERR(qp->umem)) {
747 err = PTR_ERR(qp->umem);
751 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
752 ilog2(qp->umem->page_size), &qp->mtt);
756 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
760 if (qp_has_rq(init_attr)) {
761 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
762 ucmd.db_addr, &qp->db);
767 qp->sq_no_prefetch = 0;
769 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
770 qp->flags |= MLX4_IB_QP_LSO;
772 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
773 if (dev->steering_support ==
774 MLX4_STEERING_MODE_DEVICE_MANAGED)
775 qp->flags |= MLX4_IB_QP_NETIF;
782 memcpy(&backup_cap, &init_attr->cap, sizeof(backup_cap));
783 err = set_kernel_sq_size(dev, &init_attr->cap,
788 if (qp_has_rq(init_attr)) {
789 err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
796 if (mlx4_buf_alloc(dev->dev, qp->buf_size, qp->buf_size,
798 memcpy(&init_attr->cap, &backup_cap,
800 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type,
805 if (mlx4_buf_alloc(dev->dev, qp->buf_size,
806 PAGE_SIZE * 2, &qp->buf, gfp)) {
812 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
817 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
821 qp->sq.wrid = kmalloc_array(qp->sq.wqe_cnt, sizeof(u64),
824 qp->sq.wrid = __vmalloc(qp->sq.wqe_cnt * sizeof(u64),
826 qp->rq.wrid = kmalloc_array(qp->rq.wqe_cnt, sizeof(u64),
829 qp->rq.wrid = __vmalloc(qp->rq.wqe_cnt * sizeof(u64),
831 if (!qp->sq.wrid || !qp->rq.wrid) {
838 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
839 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
840 if (alloc_proxy_bufs(pd->device, qp)) {
846 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
847 * otherwise, the WQE BlueFlame setup flow wrongly causes
849 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
850 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
851 (init_attr->cap.max_send_wr ?
852 MLX4_RESERVE_ETH_BF_QP : 0) |
853 (init_attr->cap.max_recv_wr ?
854 MLX4_RESERVE_A0_QP : 0));
856 if (qp->flags & MLX4_IB_QP_NETIF)
857 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
859 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
865 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
866 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
868 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
872 if (init_attr->qp_type == IB_QPT_XRC_TGT)
873 qp->mqp.qpn |= (1 << 23);
876 * Hardware wants QPN written in big-endian order (after
877 * shifting) for send doorbell. Precompute this value to save
878 * a little bit when posting sends.
880 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
882 qp->mqp.event = mlx4_ib_qp_event;
886 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
887 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
888 to_mcq(init_attr->recv_cq));
889 /* Maintain device to QPs access, needed for further handling
892 list_add_tail(&qp->qps_list, &dev->qp_list);
893 /* Maintain CQ to QPs access, needed for further handling
896 mcq = to_mcq(init_attr->send_cq);
897 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
898 mcq = to_mcq(init_attr->recv_cq);
899 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
900 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
901 to_mcq(init_attr->recv_cq));
902 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
907 if (qp->flags & MLX4_IB_QP_NETIF)
908 mlx4_ib_steer_qp_free(dev, qpn, 1);
910 mlx4_qp_release_range(dev->dev, qpn, 1);
913 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
914 free_proxy_bufs(pd->device, qp);
917 if (qp_has_rq(init_attr))
918 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
925 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
929 ib_umem_release(qp->umem);
931 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
934 if (!pd->uobject && qp_has_rq(init_attr))
935 mlx4_db_free(dev->dev, &qp->db);
943 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
946 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
947 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
948 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
949 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
950 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
951 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
952 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
957 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
958 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
960 if (send_cq == recv_cq) {
961 spin_lock(&send_cq->lock);
962 __acquire(&recv_cq->lock);
963 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
964 spin_lock(&send_cq->lock);
965 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
967 spin_lock(&recv_cq->lock);
968 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
972 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
973 __releases(&send_cq->lock) __releases(&recv_cq->lock)
975 if (send_cq == recv_cq) {
976 __release(&recv_cq->lock);
977 spin_unlock(&send_cq->lock);
978 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
979 spin_unlock(&recv_cq->lock);
980 spin_unlock(&send_cq->lock);
982 spin_unlock(&send_cq->lock);
983 spin_unlock(&recv_cq->lock);
987 static void del_gid_entries(struct mlx4_ib_qp *qp)
989 struct mlx4_ib_gid_entry *ge, *tmp;
991 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
997 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
999 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1000 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1002 return to_mpd(qp->ibqp.pd);
1005 static void get_cqs(struct mlx4_ib_qp *qp,
1006 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1008 switch (qp->ibqp.qp_type) {
1009 case IB_QPT_XRC_TGT:
1010 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1011 *recv_cq = *send_cq;
1013 case IB_QPT_XRC_INI:
1014 *send_cq = to_mcq(qp->ibqp.send_cq);
1015 *recv_cq = *send_cq;
1018 *send_cq = to_mcq(qp->ibqp.send_cq);
1019 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1024 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1027 struct mlx4_ib_cq *send_cq, *recv_cq;
1028 unsigned long flags;
1030 if (qp->state != IB_QPS_RESET) {
1031 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1032 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1033 pr_warn("modify QP %06x to RESET failed.\n",
1035 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1036 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1038 qp->pri.smac_port = 0;
1041 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1044 if (qp->pri.vid < 0x1000) {
1045 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1046 qp->pri.vid = 0xFFFF;
1047 qp->pri.candidate_vid = 0xFFFF;
1048 qp->pri.update_vid = 0;
1050 if (qp->alt.vid < 0x1000) {
1051 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1052 qp->alt.vid = 0xFFFF;
1053 qp->alt.candidate_vid = 0xFFFF;
1054 qp->alt.update_vid = 0;
1058 get_cqs(qp, &send_cq, &recv_cq);
1060 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1061 mlx4_ib_lock_cqs(send_cq, recv_cq);
1063 /* del from lists under both locks above to protect reset flow paths */
1064 list_del(&qp->qps_list);
1065 list_del(&qp->cq_send_list);
1066 list_del(&qp->cq_recv_list);
1068 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1069 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1070 if (send_cq != recv_cq)
1071 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1074 mlx4_qp_remove(dev->dev, &qp->mqp);
1076 mlx4_ib_unlock_cqs(send_cq, recv_cq);
1077 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1079 mlx4_qp_free(dev->dev, &qp->mqp);
1081 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1082 if (qp->flags & MLX4_IB_QP_NETIF)
1083 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1085 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1088 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1092 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1094 ib_umem_release(qp->umem);
1096 kvfree(qp->sq.wrid);
1097 kvfree(qp->rq.wrid);
1098 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1099 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1100 free_proxy_bufs(&dev->ib_dev, qp);
1101 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1103 mlx4_db_free(dev->dev, &qp->db);
1106 del_gid_entries(qp);
1109 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1112 if (!mlx4_is_mfunc(dev->dev) ||
1113 (mlx4_is_master(dev->dev) &&
1114 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1115 return dev->dev->phys_caps.base_sqpn +
1116 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1119 /* PF or VF -- creating proxies */
1120 if (attr->qp_type == IB_QPT_SMI)
1121 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1123 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1126 static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1127 struct ib_qp_init_attr *init_attr,
1128 struct ib_udata *udata)
1130 struct mlx4_ib_qp *qp = NULL;
1132 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1136 gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1137 GFP_NOIO : GFP_KERNEL;
1139 * We only support LSO, vendor flag1, and multicast loopback blocking,
1140 * and only for kernel UD QPs.
1142 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1143 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1144 MLX4_IB_SRIOV_TUNNEL_QP |
1147 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1148 MLX4_IB_QP_CREATE_USE_GFP_NOIO))
1149 return ERR_PTR(-EINVAL);
1151 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1152 if (init_attr->qp_type != IB_QPT_UD)
1153 return ERR_PTR(-EINVAL);
1156 if (init_attr->create_flags) {
1157 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1158 return ERR_PTR(-EINVAL);
1160 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1161 MLX4_IB_QP_CREATE_USE_GFP_NOIO |
1162 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1163 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1164 init_attr->qp_type != IB_QPT_UD) ||
1165 (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1166 init_attr->qp_type > IB_QPT_GSI) ||
1167 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1168 init_attr->qp_type != IB_QPT_GSI))
1169 return ERR_PTR(-EINVAL);
1172 switch (init_attr->qp_type) {
1173 case IB_QPT_XRC_TGT:
1174 pd = to_mxrcd(init_attr->xrcd)->pd;
1175 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1176 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1178 case IB_QPT_XRC_INI:
1179 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1180 return ERR_PTR(-ENOSYS);
1181 init_attr->recv_cq = init_attr->send_cq;
1185 case IB_QPT_RAW_PACKET:
1186 qp = kzalloc(sizeof *qp, gfp);
1188 return ERR_PTR(-ENOMEM);
1189 qp->pri.vid = 0xFFFF;
1190 qp->alt.vid = 0xFFFF;
1194 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
1195 udata, 0, &qp, gfp);
1198 return ERR_PTR(err);
1201 qp->ibqp.qp_num = qp->mqp.qpn;
1211 /* Userspace is not allowed to create special QPs: */
1213 return ERR_PTR(-EINVAL);
1214 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
1215 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev, 1, 1, &sqpn, 0);
1218 return ERR_PTR(res);
1220 sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1223 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
1227 return ERR_PTR(err);
1229 qp->port = init_attr->port_num;
1230 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1231 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
1235 /* Don't support raw QPs */
1236 return ERR_PTR(-EINVAL);
1242 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1243 struct ib_qp_init_attr *init_attr,
1244 struct ib_udata *udata) {
1245 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1247 struct mlx4_ib_dev *dev = to_mdev(device);
1249 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1251 if (!IS_ERR(ibqp) &&
1252 (init_attr->qp_type == IB_QPT_GSI) &&
1253 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1254 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1255 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1258 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1259 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1260 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1262 if (IS_ERR(sqp->roce_v2_gsi)) {
1263 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1264 sqp->roce_v2_gsi = NULL;
1266 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1267 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1270 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1276 static int _mlx4_ib_destroy_qp(struct ib_qp *qp)
1278 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1279 struct mlx4_ib_qp *mqp = to_mqp(qp);
1280 struct mlx4_ib_pd *pd;
1282 if (is_qp0(dev, mqp))
1283 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1285 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1286 dev->qp1_proxy[mqp->port - 1] == mqp) {
1287 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1288 dev->qp1_proxy[mqp->port - 1] = NULL;
1289 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1292 if (mqp->counter_index)
1293 mlx4_ib_free_qp_counter(dev, mqp);
1296 destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
1298 if (is_sqp(dev, mqp))
1299 kfree(to_msqp(mqp));
1306 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1308 struct mlx4_ib_qp *mqp = to_mqp(qp);
1310 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1311 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1313 if (sqp->roce_v2_gsi)
1314 ib_destroy_qp(sqp->roce_v2_gsi);
1317 return _mlx4_ib_destroy_qp(qp);
1320 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1323 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1324 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1325 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1326 case MLX4_IB_QPT_XRC_INI:
1327 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1328 case MLX4_IB_QPT_SMI:
1329 case MLX4_IB_QPT_GSI:
1330 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1332 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1333 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1334 MLX4_QP_ST_MLX : -1);
1335 case MLX4_IB_QPT_PROXY_SMI:
1336 case MLX4_IB_QPT_TUN_SMI:
1337 case MLX4_IB_QPT_PROXY_GSI:
1338 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1339 MLX4_QP_ST_UD : -1);
1344 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1349 u32 hw_access_flags = 0;
1351 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1352 dest_rd_atomic = attr->max_dest_rd_atomic;
1354 dest_rd_atomic = qp->resp_depth;
1356 if (attr_mask & IB_QP_ACCESS_FLAGS)
1357 access_flags = attr->qp_access_flags;
1359 access_flags = qp->atomic_rd_en;
1361 if (!dest_rd_atomic)
1362 access_flags &= IB_ACCESS_REMOTE_WRITE;
1364 if (access_flags & IB_ACCESS_REMOTE_READ)
1365 hw_access_flags |= MLX4_QP_BIT_RRE;
1366 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1367 hw_access_flags |= MLX4_QP_BIT_RAE;
1368 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1369 hw_access_flags |= MLX4_QP_BIT_RWE;
1371 return cpu_to_be32(hw_access_flags);
1374 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1377 if (attr_mask & IB_QP_PKEY_INDEX)
1378 sqp->pkey_index = attr->pkey_index;
1379 if (attr_mask & IB_QP_QKEY)
1380 sqp->qkey = attr->qkey;
1381 if (attr_mask & IB_QP_SQ_PSN)
1382 sqp->send_psn = attr->sq_psn;
1385 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1387 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1390 static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1391 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1392 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1394 int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1395 IB_LINK_LAYER_ETHERNET;
1401 path->grh_mylmc = ah->src_path_bits & 0x7f;
1402 path->rlid = cpu_to_be16(ah->dlid);
1403 if (ah->static_rate) {
1404 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1405 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1406 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1407 --path->static_rate;
1409 path->static_rate = 0;
1411 if (ah->ah_flags & IB_AH_GRH) {
1412 int real_sgid_index = mlx4_ib_gid_index_to_real_index(dev,
1414 ah->grh.sgid_index);
1416 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
1417 pr_err("sgid_index (%u) too large. max is %d\n",
1418 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1422 path->grh_mylmc |= 1 << 7;
1423 path->mgid_index = real_sgid_index;
1424 path->hop_limit = ah->grh.hop_limit;
1425 path->tclass_flowlabel =
1426 cpu_to_be32((ah->grh.traffic_class << 20) |
1427 (ah->grh.flow_label));
1428 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1432 if (!(ah->ah_flags & IB_AH_GRH))
1435 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1436 ((port - 1) << 6) | ((ah->sl & 7) << 3);
1438 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1439 if (vlan_tag < 0x1000) {
1440 if (smac_info->vid < 0x1000) {
1441 /* both valid vlan ids */
1442 if (smac_info->vid != vlan_tag) {
1443 /* different VIDs. unreg old and reg new */
1444 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1447 smac_info->candidate_vid = vlan_tag;
1448 smac_info->candidate_vlan_index = vidx;
1449 smac_info->candidate_vlan_port = port;
1450 smac_info->update_vid = 1;
1451 path->vlan_index = vidx;
1453 path->vlan_index = smac_info->vlan_index;
1456 /* no current vlan tag in qp */
1457 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1460 smac_info->candidate_vid = vlan_tag;
1461 smac_info->candidate_vlan_index = vidx;
1462 smac_info->candidate_vlan_port = port;
1463 smac_info->update_vid = 1;
1464 path->vlan_index = vidx;
1466 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1469 /* have current vlan tag. unregister it at modify-qp success */
1470 if (smac_info->vid < 0x1000) {
1471 smac_info->candidate_vid = 0xFFFF;
1472 smac_info->update_vid = 1;
1476 /* get smac_index for RoCE use.
1477 * If no smac was yet assigned, register one.
1478 * If one was already assigned, but the new mac differs,
1479 * unregister the old one and register the new one.
1481 if ((!smac_info->smac && !smac_info->smac_port) ||
1482 smac_info->smac != smac) {
1483 /* register candidate now, unreg if needed, after success */
1484 smac_index = mlx4_register_mac(dev->dev, port, smac);
1485 if (smac_index >= 0) {
1486 smac_info->candidate_smac_index = smac_index;
1487 smac_info->candidate_smac = smac;
1488 smac_info->candidate_smac_port = port;
1493 smac_index = smac_info->smac_index;
1496 memcpy(path->dmac, ah->dmac, 6);
1497 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1498 /* put MAC table smac index for IBoE */
1499 path->grh_mylmc = (u8) (smac_index) | 0x80;
1501 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1502 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
1508 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1509 enum ib_qp_attr_mask qp_attr_mask,
1510 struct mlx4_ib_qp *mqp,
1511 struct mlx4_qp_path *path, u8 port,
1512 u16 vlan_id, u8 *smac)
1514 return _mlx4_set_path(dev, &qp->ah_attr,
1515 mlx4_mac_to_u64(smac),
1517 path, &mqp->pri, port);
1520 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1521 const struct ib_qp_attr *qp,
1522 enum ib_qp_attr_mask qp_attr_mask,
1523 struct mlx4_ib_qp *mqp,
1524 struct mlx4_qp_path *path, u8 port)
1526 return _mlx4_set_path(dev, &qp->alt_ah_attr,
1529 path, &mqp->alt, port);
1532 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1534 struct mlx4_ib_gid_entry *ge, *tmp;
1536 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1537 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1539 ge->port = qp->port;
1544 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1545 struct mlx4_ib_qp *qp,
1546 struct mlx4_qp_context *context)
1551 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
1553 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1554 if (!qp->pri.smac && !qp->pri.smac_port) {
1555 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1556 if (smac_index >= 0) {
1557 qp->pri.candidate_smac_index = smac_index;
1558 qp->pri.candidate_smac = u64_mac;
1559 qp->pri.candidate_smac_port = qp->port;
1560 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1568 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1570 struct counter_index *new_counter_index;
1574 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1575 IB_LINK_LAYER_ETHERNET ||
1576 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1577 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1580 err = mlx4_counter_alloc(dev->dev, &tmp_idx);
1584 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1585 if (!new_counter_index) {
1586 mlx4_counter_free(dev->dev, tmp_idx);
1590 new_counter_index->index = tmp_idx;
1591 new_counter_index->allocated = 1;
1592 qp->counter_index = new_counter_index;
1594 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1595 list_add_tail(&new_counter_index->list,
1596 &dev->counters_table[qp->port - 1].counters_list);
1597 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1603 MLX4_QPC_ROCE_MODE_1 = 0,
1604 MLX4_QPC_ROCE_MODE_2 = 2,
1605 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
1608 static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
1611 case IB_GID_TYPE_ROCE:
1612 return MLX4_QPC_ROCE_MODE_1;
1613 case IB_GID_TYPE_ROCE_UDP_ENCAP:
1614 return MLX4_QPC_ROCE_MODE_2;
1616 return MLX4_QPC_ROCE_MODE_UNDEFINED;
1620 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1621 const struct ib_qp_attr *attr, int attr_mask,
1622 enum ib_qp_state cur_state, enum ib_qp_state new_state)
1624 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1625 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1626 struct mlx4_ib_pd *pd;
1627 struct mlx4_ib_cq *send_cq, *recv_cq;
1628 struct mlx4_qp_context *context;
1629 enum mlx4_qp_optpar optpar = 0;
1635 /* APM is not supported under RoCE */
1636 if (attr_mask & IB_QP_ALT_PATH &&
1637 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1638 IB_LINK_LAYER_ETHERNET)
1641 context = kzalloc(sizeof *context, GFP_KERNEL);
1645 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1646 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
1648 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1649 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1651 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1652 switch (attr->path_mig_state) {
1653 case IB_MIG_MIGRATED:
1654 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1657 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1660 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1665 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
1666 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
1667 else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1668 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
1669 else if (ibqp->qp_type == IB_QPT_UD) {
1670 if (qp->flags & MLX4_IB_QP_LSO)
1671 context->mtu_msgmax = (IB_MTU_4096 << 5) |
1672 ilog2(dev->dev->caps.max_gso_sz);
1674 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13;
1675 } else if (attr_mask & IB_QP_PATH_MTU) {
1676 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
1677 pr_err("path MTU (%u) is invalid\n",
1681 context->mtu_msgmax = (attr->path_mtu << 5) |
1682 ilog2(dev->dev->caps.max_msg_sz);
1686 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
1687 context->rq_size_stride |= qp->rq.wqe_shift - 4;
1690 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1691 context->sq_size_stride |= qp->sq.wqe_shift - 4;
1693 if (new_state == IB_QPS_RESET && qp->counter_index)
1694 mlx4_ib_free_qp_counter(dev, qp);
1696 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1697 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1698 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1699 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1700 context->param3 |= cpu_to_be32(1 << 30);
1703 if (qp->ibqp.uobject)
1704 context->usr_page = cpu_to_be32(
1705 mlx4_to_hw_uar_index(dev->dev,
1706 to_mucontext(ibqp->uobject->context)->uar.index));
1708 context->usr_page = cpu_to_be32(
1709 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
1711 if (attr_mask & IB_QP_DEST_QPN)
1712 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1714 if (attr_mask & IB_QP_PORT) {
1715 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1716 !(attr_mask & IB_QP_AV)) {
1717 mlx4_set_sched(&context->pri_path, attr->port_num);
1718 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1722 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1723 err = create_qp_lb_counter(dev, qp);
1728 dev->counters_table[qp->port - 1].default_counter;
1729 if (qp->counter_index)
1730 counter_index = qp->counter_index->index;
1732 if (counter_index != -1) {
1733 context->pri_path.counter_index = counter_index;
1734 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1735 if (qp->counter_index) {
1736 context->pri_path.fl |=
1737 MLX4_FL_ETH_SRC_CHECK_MC_LB;
1738 context->pri_path.vlan_control |=
1739 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
1742 context->pri_path.counter_index =
1743 MLX4_SINK_COUNTER_INDEX(dev->dev);
1745 if (qp->flags & MLX4_IB_QP_NETIF) {
1746 mlx4_ib_steer_qp_reg(dev, qp, 1);
1750 if (ibqp->qp_type == IB_QPT_GSI) {
1751 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
1752 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
1753 u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
1755 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
1759 if (attr_mask & IB_QP_PKEY_INDEX) {
1760 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1761 context->pri_path.disable_pkey_check = 0x40;
1762 context->pri_path.pkey_index = attr->pkey_index;
1763 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1766 if (attr_mask & IB_QP_AV) {
1767 u8 port_num = mlx4_is_bonded(to_mdev(ibqp->device)->dev) ? 1 :
1768 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1770 struct ib_gid_attr gid_attr = {.gid_type = IB_GID_TYPE_IB};
1774 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
1775 attr->ah_attr.ah_flags & IB_AH_GRH;
1777 if (is_eth && attr->ah_attr.ah_flags & IB_AH_GRH) {
1778 int index = attr->ah_attr.grh.sgid_index;
1780 status = ib_get_cached_gid(ibqp->device, port_num,
1781 index, &gid, &gid_attr);
1782 if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
1784 if (!status && gid_attr.ndev) {
1785 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
1786 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
1787 dev_put(gid_attr.ndev);
1793 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
1794 port_num, vlan, smac))
1797 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1798 MLX4_QP_OPTPAR_SCHED_QUEUE);
1801 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
1802 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr.gid_type);
1804 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
1808 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
1813 if (attr_mask & IB_QP_TIMEOUT) {
1814 context->pri_path.ackto |= attr->timeout << 3;
1815 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1818 if (attr_mask & IB_QP_ALT_PATH) {
1819 if (attr->alt_port_num == 0 ||
1820 attr->alt_port_num > dev->dev->caps.num_ports)
1823 if (attr->alt_pkey_index >=
1824 dev->dev->caps.pkey_table_len[attr->alt_port_num])
1827 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1829 attr->alt_port_num))
1832 context->alt_path.pkey_index = attr->alt_pkey_index;
1833 context->alt_path.ackto = attr->alt_timeout << 3;
1834 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1838 get_cqs(qp, &send_cq, &recv_cq);
1839 context->pd = cpu_to_be32(pd->pdn);
1840 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1841 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1842 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1844 /* Set "fast registration enabled" for all kernel QPs */
1845 if (!qp->ibqp.uobject)
1846 context->params1 |= cpu_to_be32(1 << 11);
1848 if (attr_mask & IB_QP_RNR_RETRY) {
1849 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1850 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1853 if (attr_mask & IB_QP_RETRY_CNT) {
1854 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1855 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1858 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1859 if (attr->max_rd_atomic)
1861 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1862 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1865 if (attr_mask & IB_QP_SQ_PSN)
1866 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1868 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1869 if (attr->max_dest_rd_atomic)
1871 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1872 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1875 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1876 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1877 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1881 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1883 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1884 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1885 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1887 if (attr_mask & IB_QP_RQ_PSN)
1888 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1890 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
1891 if (attr_mask & IB_QP_QKEY) {
1892 if (qp->mlx4_ib_qp_type &
1893 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1894 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1896 if (mlx4_is_mfunc(dev->dev) &&
1897 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1898 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1899 MLX4_RESERVED_QKEY_BASE) {
1900 pr_err("Cannot use reserved QKEY"
1901 " 0x%x (range 0xffff0000..0xffffffff"
1902 " is reserved)\n", attr->qkey);
1906 context->qkey = cpu_to_be32(attr->qkey);
1908 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1912 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1914 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1915 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1917 if (cur_state == IB_QPS_INIT &&
1918 new_state == IB_QPS_RTR &&
1919 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1920 ibqp->qp_type == IB_QPT_UD ||
1921 ibqp->qp_type == IB_QPT_RAW_PACKET)) {
1922 context->pri_path.sched_queue = (qp->port - 1) << 6;
1923 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1924 qp->mlx4_ib_qp_type &
1925 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
1926 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1927 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1928 context->pri_path.fl = 0x80;
1930 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1931 context->pri_path.fl = 0x80;
1932 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1934 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1935 IB_LINK_LAYER_ETHERNET) {
1936 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1937 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1938 context->pri_path.feup = 1 << 7; /* don't fsm */
1939 /* handle smac_index */
1940 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1941 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1942 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
1943 err = handle_eth_ud_smac_index(dev, qp, context);
1948 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1949 dev->qp1_proxy[qp->port - 1] = qp;
1954 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1955 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1956 MLX4_IB_LINK_TYPE_ETH;
1957 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1958 /* set QP to receive both tunneled & non-tunneled packets */
1959 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
1960 context->srqn = cpu_to_be32(7 << 28);
1964 if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1965 int is_eth = rdma_port_get_link_layer(
1966 &dev->ib_dev, qp->port) ==
1967 IB_LINK_LAYER_ETHERNET;
1969 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1970 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1975 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1976 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1981 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1982 context->rlkey_roce_mode |= (1 << 4);
1985 * Before passing a kernel QP to the HW, make sure that the
1986 * ownership bits of the send queue are set and the SQ
1987 * headroom is stamped so that the hardware doesn't start
1988 * processing stale work requests.
1990 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1991 struct mlx4_wqe_ctrl_seg *ctrl;
1994 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1995 ctrl = get_send_wqe(qp, i);
1996 ctrl->owner_opcode = cpu_to_be32(1 << 31);
1997 if (qp->sq_max_wqes_per_wr == 1)
1998 ctrl->qpn_vlan.fence_size =
1999 1 << (qp->sq.wqe_shift - 4);
2001 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
2005 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2006 to_mlx4_state(new_state), context, optpar,
2007 sqd_event, &qp->mqp);
2011 qp->state = new_state;
2013 if (attr_mask & IB_QP_ACCESS_FLAGS)
2014 qp->atomic_rd_en = attr->qp_access_flags;
2015 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2016 qp->resp_depth = attr->max_dest_rd_atomic;
2017 if (attr_mask & IB_QP_PORT) {
2018 qp->port = attr->port_num;
2019 update_mcg_macs(dev, qp);
2021 if (attr_mask & IB_QP_ALT_PATH)
2022 qp->alt_port = attr->alt_port_num;
2024 if (is_sqp(dev, qp))
2025 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2028 * If we moved QP0 to RTR, bring the IB link up; if we moved
2029 * QP0 to RESET or ERROR, bring the link back down.
2031 if (is_qp0(dev, qp)) {
2032 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
2033 if (mlx4_INIT_PORT(dev->dev, qp->port))
2034 pr_warn("INIT_PORT failed for port %d\n",
2037 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2038 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2039 mlx4_CLOSE_PORT(dev->dev, qp->port);
2043 * If we moved a kernel QP to RESET, clean up all old CQ
2044 * entries and reinitialize the QP.
2046 if (new_state == IB_QPS_RESET) {
2047 if (!ibqp->uobject) {
2048 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
2049 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2050 if (send_cq != recv_cq)
2051 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2057 qp->sq_next_wqe = 0;
2061 if (qp->flags & MLX4_IB_QP_NETIF)
2062 mlx4_ib_steer_qp_reg(dev, qp, 0);
2064 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2065 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2067 qp->pri.smac_port = 0;
2070 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2073 if (qp->pri.vid < 0x1000) {
2074 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2075 qp->pri.vid = 0xFFFF;
2076 qp->pri.candidate_vid = 0xFFFF;
2077 qp->pri.update_vid = 0;
2080 if (qp->alt.vid < 0x1000) {
2081 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2082 qp->alt.vid = 0xFFFF;
2083 qp->alt.candidate_vid = 0xFFFF;
2084 qp->alt.update_vid = 0;
2088 if (err && qp->counter_index)
2089 mlx4_ib_free_qp_counter(dev, qp);
2090 if (err && steer_qp)
2091 mlx4_ib_steer_qp_reg(dev, qp, 0);
2093 if (qp->pri.candidate_smac ||
2094 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2096 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2098 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2099 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2100 qp->pri.smac = qp->pri.candidate_smac;
2101 qp->pri.smac_index = qp->pri.candidate_smac_index;
2102 qp->pri.smac_port = qp->pri.candidate_smac_port;
2104 qp->pri.candidate_smac = 0;
2105 qp->pri.candidate_smac_index = 0;
2106 qp->pri.candidate_smac_port = 0;
2108 if (qp->alt.candidate_smac) {
2110 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2113 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2114 qp->alt.smac = qp->alt.candidate_smac;
2115 qp->alt.smac_index = qp->alt.candidate_smac_index;
2116 qp->alt.smac_port = qp->alt.candidate_smac_port;
2118 qp->alt.candidate_smac = 0;
2119 qp->alt.candidate_smac_index = 0;
2120 qp->alt.candidate_smac_port = 0;
2123 if (qp->pri.update_vid) {
2125 if (qp->pri.candidate_vid < 0x1000)
2126 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2127 qp->pri.candidate_vid);
2129 if (qp->pri.vid < 0x1000)
2130 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2132 qp->pri.vid = qp->pri.candidate_vid;
2133 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2134 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2136 qp->pri.candidate_vid = 0xFFFF;
2137 qp->pri.update_vid = 0;
2140 if (qp->alt.update_vid) {
2142 if (qp->alt.candidate_vid < 0x1000)
2143 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2144 qp->alt.candidate_vid);
2146 if (qp->alt.vid < 0x1000)
2147 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2149 qp->alt.vid = qp->alt.candidate_vid;
2150 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2151 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2153 qp->alt.candidate_vid = 0xFFFF;
2154 qp->alt.update_vid = 0;
2160 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2161 int attr_mask, struct ib_udata *udata)
2163 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2164 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2165 enum ib_qp_state cur_state, new_state;
2168 mutex_lock(&qp->mutex);
2170 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2171 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2173 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2174 ll = IB_LINK_LAYER_UNSPECIFIED;
2176 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2177 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2180 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
2182 pr_debug("qpn 0x%x: invalid attribute mask specified "
2183 "for transition %d to %d. qp_type %d,"
2184 " attr_mask 0x%x\n",
2185 ibqp->qp_num, cur_state, new_state,
2186 ibqp->qp_type, attr_mask);
2190 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2191 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2192 if ((ibqp->qp_type == IB_QPT_RC) ||
2193 (ibqp->qp_type == IB_QPT_UD) ||
2194 (ibqp->qp_type == IB_QPT_UC) ||
2195 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2196 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2197 attr->port_num = mlx4_ib_bond_next_port(dev);
2200 /* no sense in changing port_num
2201 * when ports are bonded */
2202 attr_mask &= ~IB_QP_PORT;
2206 if ((attr_mask & IB_QP_PORT) &&
2207 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
2208 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2209 "for transition %d to %d. qp_type %d\n",
2210 ibqp->qp_num, attr->port_num, cur_state,
2211 new_state, ibqp->qp_type);
2215 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2216 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2217 IB_LINK_LAYER_ETHERNET))
2220 if (attr_mask & IB_QP_PKEY_INDEX) {
2221 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2222 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2223 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2224 "for transition %d to %d. qp_type %d\n",
2225 ibqp->qp_num, attr->pkey_index, cur_state,
2226 new_state, ibqp->qp_type);
2231 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2232 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
2233 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2234 "Transition %d to %d. qp_type %d\n",
2235 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2236 new_state, ibqp->qp_type);
2240 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2241 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
2242 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2243 "Transition %d to %d. qp_type %d\n",
2244 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2245 new_state, ibqp->qp_type);
2249 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2254 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2256 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2260 mutex_unlock(&qp->mutex);
2264 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2265 int attr_mask, struct ib_udata *udata)
2267 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2270 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2272 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2273 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2276 if (sqp->roce_v2_gsi)
2277 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2279 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2285 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2288 for (i = 0; i < dev->caps.num_ports; i++) {
2289 if (qpn == dev->caps.qp0_proxy[i] ||
2290 qpn == dev->caps.qp0_tunnel[i]) {
2291 *qkey = dev->caps.qp0_qkey[i];
2298 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
2299 struct ib_ud_wr *wr,
2300 void *wqe, unsigned *mlx_seg_len)
2302 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2303 struct ib_device *ib_dev = &mdev->ib_dev;
2304 struct mlx4_wqe_mlx_seg *mlx = wqe;
2305 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2306 struct mlx4_ib_ah *ah = to_mah(wr->ah);
2315 if (wr->wr.opcode != IB_WR_SEND)
2320 for (i = 0; i < wr->wr.num_sge; ++i)
2321 send_size += wr->wr.sg_list[i].length;
2323 /* for proxy-qp0 sends, need to add in size of tunnel header */
2324 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2325 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2326 send_size += sizeof (struct mlx4_ib_tunnel_header);
2328 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
2330 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2331 sqp->ud_header.lrh.service_level =
2332 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2333 sqp->ud_header.lrh.destination_lid =
2334 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2335 sqp->ud_header.lrh.source_lid =
2336 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2339 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2341 /* force loopback */
2342 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2343 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2345 sqp->ud_header.lrh.virtual_lane = 0;
2346 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2347 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2350 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2351 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2352 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2354 sqp->ud_header.bth.destination_qpn =
2355 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
2357 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2358 if (mlx4_is_master(mdev->dev)) {
2359 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2362 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2365 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2366 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2368 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2369 sqp->ud_header.immediate_present = 0;
2371 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2374 * Inline data segments may not cross a 64 byte boundary. If
2375 * our UD header is bigger than the space available up to the
2376 * next 64 byte boundary in the WQE, use two inline data
2377 * segments to hold the UD header.
2379 spc = MLX4_INLINE_ALIGN -
2380 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2381 if (header_size <= spc) {
2382 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2383 memcpy(inl + 1, sqp->header_buf, header_size);
2386 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2387 memcpy(inl + 1, sqp->header_buf, spc);
2389 inl = (void *) (inl + 1) + spc;
2390 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2392 * Need a barrier here to make sure all the data is
2393 * visible before the byte_count field is set.
2394 * Otherwise the HCA prefetcher could grab the 64-byte
2395 * chunk with this inline segment and get a valid (!=
2396 * 0xffffffff) byte count but stale data, and end up
2397 * generating a packet with bad headers.
2399 * The first inline segment's byte_count field doesn't
2400 * need a barrier, because it comes after a
2401 * control/MLX segment and therefore is at an offset
2405 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2410 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2414 static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
2416 union sl2vl_tbl_to_u64 tmp_vltab;
2421 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
2422 vl = tmp_vltab.sl8[sl >> 1];
2430 #define MLX4_ROCEV2_QP1_SPORT 0xC000
2431 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
2432 void *wqe, unsigned *mlx_seg_len)
2434 struct ib_device *ib_dev = sqp->qp.ibqp.device;
2435 struct mlx4_wqe_mlx_seg *mlx = wqe;
2436 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
2437 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2438 struct mlx4_ib_ah *ah = to_mah(wr->ah);
2448 bool is_vlan = false;
2450 bool is_udp = false;
2454 for (i = 0; i < wr->wr.num_sge; ++i)
2455 send_size += wr->wr.sg_list[i].length;
2457 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2458 is_grh = mlx4_ib_ah_grh_present(ah);
2460 struct ib_gid_attr gid_attr;
2462 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2463 /* When multi-function is enabled, the ib_core gid
2464 * indexes don't necessarily match the hw ones, so
2465 * we must use our own cache */
2466 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2467 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2468 ah->av.ib.gid_index, &sgid.raw[0]);
2472 err = ib_get_cached_gid(ib_dev,
2473 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2474 ah->av.ib.gid_index, &sgid,
2478 dev_put(gid_attr.ndev);
2479 if (!memcmp(&sgid, &zgid, sizeof(sgid)))
2483 is_udp = gid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
2485 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
2495 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
2496 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2500 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
2501 ip_version, is_udp, 0, &sqp->ud_header);
2506 sqp->ud_header.lrh.service_level =
2507 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2508 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2509 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2512 if (is_grh || (ip_version == 6)) {
2513 sqp->ud_header.grh.traffic_class =
2514 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2515 sqp->ud_header.grh.flow_label =
2516 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2517 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
2519 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2521 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2522 /* When multi-function is enabled, the ib_core gid
2523 * indexes don't necessarily match the hw ones, so
2524 * we must use our own cache
2526 sqp->ud_header.grh.source_gid.global.subnet_prefix =
2527 cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov.
2528 demux[sqp->qp.port - 1].
2530 sqp->ud_header.grh.source_gid.global.interface_id =
2531 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2532 guid_cache[ah->av.ib.gid_index];
2534 ib_get_cached_gid(ib_dev,
2535 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2536 ah->av.ib.gid_index,
2537 &sqp->ud_header.grh.source_gid, NULL);
2540 memcpy(sqp->ud_header.grh.destination_gid.raw,
2541 ah->av.ib.dgid, 16);
2544 if (ip_version == 4) {
2545 sqp->ud_header.ip4.tos =
2546 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2547 sqp->ud_header.ip4.id = 0;
2548 sqp->ud_header.ip4.frag_off = htons(IP_DF);
2549 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
2551 memcpy(&sqp->ud_header.ip4.saddr,
2553 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
2554 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
2558 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
2559 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
2560 sqp->ud_header.udp.csum = 0;
2563 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2566 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2567 (sqp->ud_header.lrh.destination_lid ==
2568 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2569 (sqp->ud_header.lrh.service_level << 8));
2570 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2571 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
2572 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2575 switch (wr->wr.opcode) {
2577 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2578 sqp->ud_header.immediate_present = 0;
2580 case IB_WR_SEND_WITH_IMM:
2581 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2582 sqp->ud_header.immediate_present = 1;
2583 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
2590 struct in6_addr in6;
2592 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2594 ether_type = (!is_udp) ? MLX4_IB_IBOE_ETHERTYPE :
2595 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
2597 mlx->sched_prio = cpu_to_be16(pcp);
2599 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
2600 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2601 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2602 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2603 memcpy(&in6, sgid.raw, sizeof(in6));
2606 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2607 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2609 sqp->ud_header.eth.type = cpu_to_be16(ether_type);
2611 sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
2612 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2615 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 :
2616 sl_to_vl(to_mdev(ib_dev),
2617 sqp->ud_header.lrh.service_level,
2619 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
2621 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2622 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2624 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2625 if (!sqp->qp.ibqp.qp_num)
2626 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index,
2629 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index,
2634 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2635 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2636 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2637 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
2638 sqp->qkey : wr->remote_qkey);
2639 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2641 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2644 pr_err("built UD header of size %d:\n", header_size);
2645 for (i = 0; i < header_size / 4; ++i) {
2647 pr_err(" [%02x] ", i * 4);
2649 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
2650 if ((i + 1) % 8 == 0)
2657 * Inline data segments may not cross a 64 byte boundary. If
2658 * our UD header is bigger than the space available up to the
2659 * next 64 byte boundary in the WQE, use two inline data
2660 * segments to hold the UD header.
2662 spc = MLX4_INLINE_ALIGN -
2663 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2664 if (header_size <= spc) {
2665 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2666 memcpy(inl + 1, sqp->header_buf, header_size);
2669 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2670 memcpy(inl + 1, sqp->header_buf, spc);
2672 inl = (void *) (inl + 1) + spc;
2673 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2675 * Need a barrier here to make sure all the data is
2676 * visible before the byte_count field is set.
2677 * Otherwise the HCA prefetcher could grab the 64-byte
2678 * chunk with this inline segment and get a valid (!=
2679 * 0xffffffff) byte count but stale data, and end up
2680 * generating a packet with bad headers.
2682 * The first inline segment's byte_count field doesn't
2683 * need a barrier, because it comes after a
2684 * control/MLX segment and therefore is at an offset
2688 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2693 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2697 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2700 struct mlx4_ib_cq *cq;
2702 cur = wq->head - wq->tail;
2703 if (likely(cur + nreq < wq->max_post))
2707 spin_lock(&cq->lock);
2708 cur = wq->head - wq->tail;
2709 spin_unlock(&cq->lock);
2711 return cur + nreq >= wq->max_post;
2714 static __be32 convert_access(int acc)
2716 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2717 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
2718 (acc & IB_ACCESS_REMOTE_WRITE ?
2719 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2720 (acc & IB_ACCESS_REMOTE_READ ?
2721 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
2722 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
2723 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2726 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
2727 struct ib_reg_wr *wr)
2729 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
2731 fseg->flags = convert_access(wr->access);
2732 fseg->mem_key = cpu_to_be32(wr->key);
2733 fseg->buf_list = cpu_to_be64(mr->page_map);
2734 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
2735 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
2736 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
2737 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
2738 fseg->reserved[0] = 0;
2739 fseg->reserved[1] = 0;
2742 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2744 memset(iseg, 0, sizeof(*iseg));
2745 iseg->mem_key = cpu_to_be32(rkey);
2748 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2749 u64 remote_addr, u32 rkey)
2751 rseg->raddr = cpu_to_be64(remote_addr);
2752 rseg->rkey = cpu_to_be32(rkey);
2756 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
2757 struct ib_atomic_wr *wr)
2759 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2760 aseg->swap_add = cpu_to_be64(wr->swap);
2761 aseg->compare = cpu_to_be64(wr->compare_add);
2762 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2763 aseg->swap_add = cpu_to_be64(wr->compare_add);
2764 aseg->compare = cpu_to_be64(wr->compare_add_mask);
2766 aseg->swap_add = cpu_to_be64(wr->compare_add);
2772 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2773 struct ib_atomic_wr *wr)
2775 aseg->swap_add = cpu_to_be64(wr->swap);
2776 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
2777 aseg->compare = cpu_to_be64(wr->compare_add);
2778 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
2781 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
2782 struct ib_ud_wr *wr)
2784 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
2785 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
2786 dseg->qkey = cpu_to_be32(wr->remote_qkey);
2787 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
2788 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
2791 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2792 struct mlx4_wqe_datagram_seg *dseg,
2793 struct ib_ud_wr *wr,
2794 enum mlx4_ib_qp_type qpt)
2796 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
2797 struct mlx4_av sqp_av = {0};
2798 int port = *((u8 *) &av->ib.port_pd) & 0x3;
2800 /* force loopback */
2801 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2802 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2803 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2804 cpu_to_be32(0xf0000000);
2806 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
2807 if (qpt == MLX4_IB_QPT_PROXY_GSI)
2808 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2810 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
2811 /* Use QKEY from the QP context, which is set by master */
2812 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2815 static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
2817 struct mlx4_wqe_inline_seg *inl = wqe;
2818 struct mlx4_ib_tunnel_header hdr;
2819 struct mlx4_ib_ah *ah = to_mah(wr->ah);
2823 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2824 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
2825 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
2826 hdr.qkey = cpu_to_be32(wr->remote_qkey);
2827 memcpy(hdr.mac, ah->av.eth.mac, 6);
2828 hdr.vlan = ah->av.eth.vlan;
2830 spc = MLX4_INLINE_ALIGN -
2831 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2832 if (sizeof (hdr) <= spc) {
2833 memcpy(inl + 1, &hdr, sizeof (hdr));
2835 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2838 memcpy(inl + 1, &hdr, spc);
2840 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2842 inl = (void *) (inl + 1) + spc;
2843 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2845 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2850 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2853 static void set_mlx_icrc_seg(void *dseg)
2856 struct mlx4_wqe_inline_seg *iseg = dseg;
2861 * Need a barrier here before writing the byte_count field to
2862 * make sure that all the data is visible before the
2863 * byte_count field is set. Otherwise, if the segment begins
2864 * a new cacheline, the HCA prefetcher could grab the 64-byte
2865 * chunk and get a valid (!= * 0xffffffff) byte count but
2866 * stale data, and end up sending the wrong data.
2870 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2873 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2875 dseg->lkey = cpu_to_be32(sg->lkey);
2876 dseg->addr = cpu_to_be64(sg->addr);
2879 * Need a barrier here before writing the byte_count field to
2880 * make sure that all the data is visible before the
2881 * byte_count field is set. Otherwise, if the segment begins
2882 * a new cacheline, the HCA prefetcher could grab the 64-byte
2883 * chunk and get a valid (!= * 0xffffffff) byte count but
2884 * stale data, and end up sending the wrong data.
2888 dseg->byte_count = cpu_to_be32(sg->length);
2891 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2893 dseg->byte_count = cpu_to_be32(sg->length);
2894 dseg->lkey = cpu_to_be32(sg->lkey);
2895 dseg->addr = cpu_to_be64(sg->addr);
2898 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
2899 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
2900 __be32 *lso_hdr_sz, __be32 *blh)
2902 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
2904 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2905 *blh = cpu_to_be32(1 << 6);
2907 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2908 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
2911 memcpy(wqe->header, wr->header, wr->hlen);
2913 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
2914 *lso_seg_len = halign;
2918 static __be32 send_ieth(struct ib_send_wr *wr)
2920 switch (wr->opcode) {
2921 case IB_WR_SEND_WITH_IMM:
2922 case IB_WR_RDMA_WRITE_WITH_IMM:
2923 return wr->ex.imm_data;
2925 case IB_WR_SEND_WITH_INV:
2926 return cpu_to_be32(wr->ex.invalidate_rkey);
2933 static void add_zero_len_inline(void *wqe)
2935 struct mlx4_wqe_inline_seg *inl = wqe;
2937 inl->byte_count = cpu_to_be32(1 << 31);
2940 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2941 struct ib_send_wr **bad_wr)
2943 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2945 struct mlx4_wqe_ctrl_seg *ctrl;
2946 struct mlx4_wqe_data_seg *dseg;
2947 unsigned long flags;
2951 int uninitialized_var(stamp);
2952 int uninitialized_var(size);
2953 unsigned uninitialized_var(seglen);
2956 __be32 uninitialized_var(lso_hdr_sz);
2959 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
2961 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2962 struct mlx4_ib_sqp *sqp = to_msqp(qp);
2964 if (sqp->roce_v2_gsi) {
2965 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
2966 struct ib_gid_attr gid_attr;
2969 if (!ib_get_cached_gid(ibqp->device,
2970 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2971 ah->av.ib.gid_index, &gid,
2974 dev_put(gid_attr.ndev);
2975 qp = (gid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
2976 to_mqp(sqp->roce_v2_gsi) : qp;
2978 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
2979 ah->av.ib.gid_index);
2984 spin_lock_irqsave(&qp->sq.lock, flags);
2985 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2992 ind = qp->sq_next_wqe;
2994 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2998 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
3004 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3010 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
3011 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
3014 (wr->send_flags & IB_SEND_SIGNALED ?
3015 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3016 (wr->send_flags & IB_SEND_SOLICITED ?
3017 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
3018 ((wr->send_flags & IB_SEND_IP_CSUM) ?
3019 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3020 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
3023 ctrl->imm = send_ieth(wr);
3025 wqe += sizeof *ctrl;
3026 size = sizeof *ctrl / 16;
3028 switch (qp->mlx4_ib_qp_type) {
3029 case MLX4_IB_QPT_RC:
3030 case MLX4_IB_QPT_UC:
3031 switch (wr->opcode) {
3032 case IB_WR_ATOMIC_CMP_AND_SWP:
3033 case IB_WR_ATOMIC_FETCH_AND_ADD:
3034 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
3035 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3036 atomic_wr(wr)->rkey);
3037 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3039 set_atomic_seg(wqe, atomic_wr(wr));
3040 wqe += sizeof (struct mlx4_wqe_atomic_seg);
3042 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3043 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
3047 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3048 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3049 atomic_wr(wr)->rkey);
3050 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3052 set_masked_atomic_seg(wqe, atomic_wr(wr));
3053 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
3055 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3056 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
3060 case IB_WR_RDMA_READ:
3061 case IB_WR_RDMA_WRITE:
3062 case IB_WR_RDMA_WRITE_WITH_IMM:
3063 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3065 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3066 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
3069 case IB_WR_LOCAL_INV:
3070 ctrl->srcrb_flags |=
3071 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3072 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3073 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
3074 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3078 ctrl->srcrb_flags |=
3079 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3080 set_reg_seg(wqe, reg_wr(wr));
3081 wqe += sizeof(struct mlx4_wqe_fmr_seg);
3082 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3086 /* No extra segments required for sends */
3091 case MLX4_IB_QPT_TUN_SMI_OWNER:
3092 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3094 if (unlikely(err)) {
3099 size += seglen / 16;
3101 case MLX4_IB_QPT_TUN_SMI:
3102 case MLX4_IB_QPT_TUN_GSI:
3103 /* this is a UD qp used in MAD responses to slaves. */
3104 set_datagram_seg(wqe, ud_wr(wr));
3105 /* set the forced-loopback bit in the data seg av */
3106 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3107 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3108 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3110 case MLX4_IB_QPT_UD:
3111 set_datagram_seg(wqe, ud_wr(wr));
3112 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3113 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3115 if (wr->opcode == IB_WR_LSO) {
3116 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3118 if (unlikely(err)) {
3122 lso_wqe = (__be32 *) wqe;
3124 size += seglen / 16;
3128 case MLX4_IB_QPT_PROXY_SMI_OWNER:
3129 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3131 if (unlikely(err)) {
3136 size += seglen / 16;
3137 /* to start tunnel header on a cache-line boundary */
3138 add_zero_len_inline(wqe);
3141 build_tunnel_header(ud_wr(wr), wqe, &seglen);
3143 size += seglen / 16;
3145 case MLX4_IB_QPT_PROXY_SMI:
3146 case MLX4_IB_QPT_PROXY_GSI:
3147 /* If we are tunneling special qps, this is a UD qp.
3148 * In this case we first add a UD segment targeting
3149 * the tunnel qp, and then add a header with address
3151 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3153 qp->mlx4_ib_qp_type);
3154 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3155 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3156 build_tunnel_header(ud_wr(wr), wqe, &seglen);
3158 size += seglen / 16;
3161 case MLX4_IB_QPT_SMI:
3162 case MLX4_IB_QPT_GSI:
3163 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3165 if (unlikely(err)) {
3170 size += seglen / 16;
3178 * Write data segments in reverse order, so as to
3179 * overwrite cacheline stamp last within each
3180 * cacheline. This avoids issues with WQE
3185 dseg += wr->num_sge - 1;
3186 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
3188 /* Add one more inline data segment for ICRC for MLX sends */
3189 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3190 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3191 qp->mlx4_ib_qp_type &
3192 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
3193 set_mlx_icrc_seg(dseg + 1);
3194 size += sizeof (struct mlx4_wqe_data_seg) / 16;
3197 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3198 set_data_seg(dseg, wr->sg_list + i);
3201 * Possibly overwrite stamping in cacheline with LSO
3202 * segment only after making sure all data segments
3206 *lso_wqe = lso_hdr_sz;
3208 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3209 MLX4_WQE_CTRL_FENCE : 0) | size;
3212 * Make sure descriptor is fully written before
3213 * setting ownership bit (because HW can start
3214 * executing as soon as we do).
3218 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
3224 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
3225 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
3227 stamp = ind + qp->sq_spare_wqes;
3228 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3231 * We can improve latency by not stamping the last
3232 * send queue WQE until after ringing the doorbell, so
3233 * only stamp here if there are still more WQEs to post.
3235 * Same optimization applies to padding with NOP wqe
3236 * in case of WQE shrinking (used to prevent wrap-around
3237 * in the middle of WR).
3240 stamp_send_wqe(qp, stamp, size * 16);
3241 ind = pad_wraparound(qp, ind);
3247 qp->sq.head += nreq;
3250 * Make sure that descriptors are written before
3255 writel(qp->doorbell_qpn,
3256 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3259 * Make sure doorbells don't leak out of SQ spinlock
3260 * and reach the HCA out of order.
3264 stamp_send_wqe(qp, stamp, size * 16);
3266 ind = pad_wraparound(qp, ind);
3267 qp->sq_next_wqe = ind;
3270 spin_unlock_irqrestore(&qp->sq.lock, flags);
3275 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3276 struct ib_recv_wr **bad_wr)
3278 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3279 struct mlx4_wqe_data_seg *scat;
3280 unsigned long flags;
3286 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3288 max_gs = qp->rq.max_gs;
3289 spin_lock_irqsave(&qp->rq.lock, flags);
3291 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3298 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3300 for (nreq = 0; wr; ++nreq, wr = wr->next) {
3301 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3307 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3313 scat = get_recv_wqe(qp, ind);
3315 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3316 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3317 ib_dma_sync_single_for_device(ibqp->device,
3318 qp->sqp_proxy_rcv[ind].map,
3319 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3322 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3323 /* use dma lkey from upper layer entry */
3324 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3325 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3330 for (i = 0; i < wr->num_sge; ++i)
3331 __set_data_seg(scat + i, wr->sg_list + i);
3334 scat[i].byte_count = 0;
3335 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3339 qp->rq.wrid[ind] = wr->wr_id;
3341 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3346 qp->rq.head += nreq;
3349 * Make sure that descriptors are written before
3354 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3357 spin_unlock_irqrestore(&qp->rq.lock, flags);
3362 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3364 switch (mlx4_state) {
3365 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3366 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3367 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3368 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3369 case MLX4_QP_STATE_SQ_DRAINING:
3370 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3371 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3372 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3377 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3379 switch (mlx4_mig_state) {
3380 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3381 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3382 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3387 static int to_ib_qp_access_flags(int mlx4_flags)
3391 if (mlx4_flags & MLX4_QP_BIT_RRE)
3392 ib_flags |= IB_ACCESS_REMOTE_READ;
3393 if (mlx4_flags & MLX4_QP_BIT_RWE)
3394 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3395 if (mlx4_flags & MLX4_QP_BIT_RAE)
3396 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3401 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
3402 struct mlx4_qp_path *path)
3404 struct mlx4_dev *dev = ibdev->dev;
3407 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
3408 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
3410 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3413 is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3414 IB_LINK_LAYER_ETHERNET;
3416 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3417 ((path->sched_queue & 4) << 1);
3419 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3421 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
3422 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3423 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
3424 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3425 if (ib_ah_attr->ah_flags) {
3426 ib_ah_attr->grh.sgid_index = path->mgid_index;
3427 ib_ah_attr->grh.hop_limit = path->hop_limit;
3428 ib_ah_attr->grh.traffic_class =
3429 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3430 ib_ah_attr->grh.flow_label =
3431 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
3432 memcpy(ib_ah_attr->grh.dgid.raw,
3433 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3437 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3438 struct ib_qp_init_attr *qp_init_attr)
3440 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3441 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3442 struct mlx4_qp_context context;
3446 mutex_lock(&qp->mutex);
3448 if (qp->state == IB_QPS_RESET) {
3449 qp_attr->qp_state = IB_QPS_RESET;
3453 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
3459 mlx4_state = be32_to_cpu(context.flags) >> 28;
3461 qp->state = to_ib_qp_state(mlx4_state);
3462 qp_attr->qp_state = qp->state;
3463 qp_attr->path_mtu = context.mtu_msgmax >> 5;
3464 qp_attr->path_mig_state =
3465 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3466 qp_attr->qkey = be32_to_cpu(context.qkey);
3467 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3468 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
3469 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
3470 qp_attr->qp_access_flags =
3471 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3473 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3474 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3475 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
3476 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3477 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
3480 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
3481 if (qp_attr->qp_state == IB_QPS_INIT)
3482 qp_attr->port_num = qp->port;
3484 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
3486 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3487 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3489 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3491 qp_attr->max_dest_rd_atomic =
3492 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3493 qp_attr->min_rnr_timer =
3494 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3495 qp_attr->timeout = context.pri_path.ackto >> 3;
3496 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
3497 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
3498 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
3501 qp_attr->cur_qp_state = qp_attr->qp_state;
3502 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
3503 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
3505 if (!ibqp->uobject) {
3506 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
3507 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3509 qp_attr->cap.max_send_wr = 0;
3510 qp_attr->cap.max_send_sge = 0;
3514 * We don't support inline sends for kernel QPs (yet), and we
3515 * don't know what userspace's value should be.
3517 qp_attr->cap.max_inline_data = 0;
3519 qp_init_attr->cap = qp_attr->cap;
3521 qp_init_attr->create_flags = 0;
3522 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3523 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3525 if (qp->flags & MLX4_IB_QP_LSO)
3526 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3528 if (qp->flags & MLX4_IB_QP_NETIF)
3529 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3531 qp_init_attr->sq_sig_type =
3532 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3533 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3536 mutex_unlock(&qp->mutex);