1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /* QLogic qed NIC Driver
3 * Copyright (c) 2015-2017 QLogic Corporation
4 * Copyright (c) 2019-2020 Marvell International Ltd.
10 #include <linux/types.h>
12 #include <linux/bitops.h>
13 #include <linux/delay.h>
14 #include <linux/kernel.h>
15 #include <linux/list.h>
16 #include <linux/slab.h>
17 #include <linux/qed/common_hsi.h>
18 #include <linux/qed/storage_common.h>
19 #include <linux/qed/tcp_common.h>
20 #include <linux/qed/fcoe_common.h>
21 #include <linux/qed/eth_common.h>
22 #include <linux/qed/iscsi_common.h>
23 #include <linux/qed/iwarp_common.h>
24 #include <linux/qed/rdma_common.h>
25 #include <linux/qed/roce_common.h>
26 #include <linux/qed/qed_fcoe_if.h>
31 /* Opcodes for the event ring */
32 enum common_event_opcode {
33 COMMON_EVENT_PF_START,
35 COMMON_EVENT_VF_START,
37 COMMON_EVENT_VF_PF_CHANNEL,
39 COMMON_EVENT_PF_UPDATE,
40 COMMON_EVENT_MALICIOUS_VF,
41 COMMON_EVENT_RL_UPDATE,
43 MAX_COMMON_EVENT_OPCODE
46 /* Common Ramrod Command IDs */
47 enum common_ramrod_cmd_id {
49 COMMON_RAMROD_PF_START,
50 COMMON_RAMROD_PF_STOP,
51 COMMON_RAMROD_VF_START,
52 COMMON_RAMROD_VF_STOP,
53 COMMON_RAMROD_PF_UPDATE,
54 COMMON_RAMROD_RL_UPDATE,
56 MAX_COMMON_RAMROD_CMD_ID
59 /* How ll2 should deal with packet upon errors */
60 enum core_error_handle {
67 /* Opcodes for the event ring */
68 enum core_event_opcode {
69 CORE_EVENT_TX_QUEUE_START,
70 CORE_EVENT_TX_QUEUE_STOP,
71 CORE_EVENT_RX_QUEUE_START,
72 CORE_EVENT_RX_QUEUE_STOP,
73 CORE_EVENT_RX_QUEUE_FLUSH,
74 CORE_EVENT_TX_QUEUE_UPDATE,
75 CORE_EVENT_QUEUE_STATS_QUERY,
79 /* The L4 pseudo checksum mode for Core */
80 enum core_l4_pseudo_checksum_mode {
81 CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
82 CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
83 MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
86 /* Light-L2 RX Producers in Tstorm RAM */
87 struct core_ll2_port_stats {
88 struct regpair gsi_invalid_hdr;
89 struct regpair gsi_invalid_pkt_length;
90 struct regpair gsi_unsupported_pkt_typ;
91 struct regpair gsi_crcchksm_error;
94 /* LL2 TX Per Queue Stats */
95 struct core_ll2_pstorm_per_queue_stat {
96 struct regpair sent_ucast_bytes;
97 struct regpair sent_mcast_bytes;
98 struct regpair sent_bcast_bytes;
99 struct regpair sent_ucast_pkts;
100 struct regpair sent_mcast_pkts;
101 struct regpair sent_bcast_pkts;
102 struct regpair error_drop_pkts;
105 /* Light-L2 RX Producers in Tstorm RAM */
106 struct core_ll2_rx_prod {
111 struct core_ll2_tstorm_per_queue_stat {
112 struct regpair packet_too_big_discard;
113 struct regpair no_buff_discard;
116 struct core_ll2_ustorm_per_queue_stat {
117 struct regpair rcv_ucast_bytes;
118 struct regpair rcv_mcast_bytes;
119 struct regpair rcv_bcast_bytes;
120 struct regpair rcv_ucast_pkts;
121 struct regpair rcv_mcast_pkts;
122 struct regpair rcv_bcast_pkts;
125 /* Structure for doorbell data, in PWM mode, for RX producers update. */
126 struct core_pwm_prod_update_data {
127 __le16 icid; /* internal CID */
130 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3
131 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT 0
132 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK 0x3F /* Set 0 */
133 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_SHIFT 2
134 struct core_ll2_rx_prod prod; /* Producers */
137 /* Core Ramrod Command IDs (light L2) */
138 enum core_ramrod_cmd_id {
140 CORE_RAMROD_RX_QUEUE_START,
141 CORE_RAMROD_TX_QUEUE_START,
142 CORE_RAMROD_RX_QUEUE_STOP,
143 CORE_RAMROD_TX_QUEUE_STOP,
144 CORE_RAMROD_RX_QUEUE_FLUSH,
145 CORE_RAMROD_TX_QUEUE_UPDATE,
146 CORE_RAMROD_QUEUE_STATS_QUERY,
147 MAX_CORE_RAMROD_CMD_ID
150 /* Core RX CQE Type for Light L2 */
151 enum core_roce_flavor_type {
154 MAX_CORE_ROCE_FLAVOR_TYPE
157 /* Specifies how ll2 should deal with packets errors: packet_too_big and
160 struct core_rx_action_on_error {
162 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
163 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
164 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
165 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2
166 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
167 #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4
170 /* Core RX BD for Light L2 */
176 /* Core RX CM offload BD for Light L2 */
177 struct core_rx_bd_with_buff_len {
183 /* Core RX CM offload BD for Light L2 */
184 union core_rx_bd_union {
185 struct core_rx_bd rx_bd;
186 struct core_rx_bd_with_buff_len rx_bd_with_len;
189 /* Opaque Data for Light L2 RX CQE */
190 struct core_rx_cqe_opaque_data {
194 /* Core RX CQE Type for Light L2 */
195 enum core_rx_cqe_type {
196 CORE_RX_CQE_ILLEGAL_TYPE,
197 CORE_RX_CQE_TYPE_REGULAR,
198 CORE_RX_CQE_TYPE_GSI_OFFLOAD,
199 CORE_RX_CQE_TYPE_SLOW_PATH,
203 /* Core RX CQE for Light L2 */
204 struct core_rx_fast_path_cqe {
207 struct parsing_and_err_flags parse_flags;
208 __le16 packet_length;
210 struct core_rx_cqe_opaque_data opaque_data;
211 struct parsing_err_flags err_flags;
216 /* Core Rx CM offload CQE */
217 struct core_rx_gsi_offload_cqe {
219 u8 data_length_error;
220 struct parsing_and_err_flags parse_flags;
223 __le32 src_mac_addrhi;
224 __le16 src_mac_addrlo;
227 struct core_rx_cqe_opaque_data opaque_data;
231 /* Core RX CQE for Light L2 */
232 struct core_rx_slow_path_cqe {
236 struct core_rx_cqe_opaque_data opaque_data;
240 /* Core RX CM offload BD for Light L2 */
241 union core_rx_cqe_union {
242 struct core_rx_fast_path_cqe rx_cqe_fp;
243 struct core_rx_gsi_offload_cqe rx_cqe_gsi;
244 struct core_rx_slow_path_cqe rx_cqe_sp;
247 /* Ramrod data for rx queue start ramrod */
248 struct core_rx_start_ramrod_data {
249 struct regpair bd_base;
250 struct regpair cqe_pbl_addr;
255 u8 complete_event_flg;
257 __le16 num_of_pbl_pages;
258 u8 inner_vlan_stripping_en;
259 u8 report_outer_vlan;
262 u8 mf_si_bcast_accept_all;
263 u8 mf_si_mcast_accept_all;
264 struct core_rx_action_on_error action_on_error;
269 u8 wipe_inner_vlan_pri_en;
273 /* Ramrod data for rx queue stop ramrod */
274 struct core_rx_stop_ramrod_data {
276 u8 complete_event_flg;
282 /* Flags for Core TX BD */
283 struct core_tx_bd_data {
285 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
286 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
287 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
288 #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1
289 #define CORE_TX_BD_DATA_START_BD_MASK 0x1
290 #define CORE_TX_BD_DATA_START_BD_SHIFT 2
291 #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
292 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3
293 #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
294 #define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4
295 #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
296 #define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5
297 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
298 #define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6
299 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
300 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7
301 #define CORE_TX_BD_DATA_NBDS_MASK 0xF
302 #define CORE_TX_BD_DATA_NBDS_SHIFT 8
303 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
304 #define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12
305 #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
306 #define CORE_TX_BD_DATA_IP_LEN_SHIFT 13
307 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK 0x1
308 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_SHIFT 14
309 #define CORE_TX_BD_DATA_RESERVED0_MASK 0x1
310 #define CORE_TX_BD_DATA_RESERVED0_SHIFT 15
313 /* Core TX BD for Light L2 */
317 __le16 nw_vlan_or_lb_echo;
318 struct core_tx_bd_data bd_data;
320 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
321 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
322 #define CORE_TX_BD_TX_DST_MASK 0x3
323 #define CORE_TX_BD_TX_DST_SHIFT 14
326 /* Light L2 TX Destination */
330 CORE_TX_DEST_RESERVED,
335 /* Ramrod data for tx queue start ramrod */
336 struct core_tx_start_ramrod_data {
337 struct regpair pbl_base_addr;
350 u8 enforce_security_flag;
354 /* Ramrod data for tx queue stop ramrod */
355 struct core_tx_stop_ramrod_data {
359 /* Ramrod data for tx queue update ramrod */
360 struct core_tx_update_ramrod_data {
361 u8 update_qm_pq_id_flg;
367 /* Enum flag for what type of dcb data to update */
368 enum dcb_dscp_update_mode {
369 DONT_UPDATE_DCB_DSCP,
373 MAX_DCB_DSCP_UPDATE_MODE
376 /* The core storm context for the Ystorm */
377 struct ystorm_core_conn_st_ctx {
381 /* The core storm context for the Pstorm */
382 struct pstorm_core_conn_st_ctx {
386 /* Core Slowpath Connection storm context of Xstorm */
387 struct xstorm_core_conn_st_ctx {
390 struct regpair consolid_base_addr;
392 __le16 consolid_cons;
393 __le32 reserved0[55];
396 struct e4_xstorm_core_conn_ag_ctx {
400 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
401 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
402 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
403 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
404 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
405 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
406 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
407 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
408 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
409 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
410 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
411 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
412 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1
413 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
414 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1
415 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
417 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1
418 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
419 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1
420 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
421 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1
422 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
423 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1
424 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
425 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1
426 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
427 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1
428 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
429 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
430 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
431 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
432 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
434 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
435 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
436 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
437 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
438 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
439 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
440 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
441 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
443 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
444 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
445 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
446 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
447 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
448 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
449 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
450 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
452 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
453 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
454 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
455 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
456 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
457 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
458 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
459 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
461 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
462 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
463 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
464 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
465 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
466 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
467 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
468 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
470 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
471 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
472 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
473 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
474 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
475 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
476 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
477 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
479 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
480 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
481 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
482 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
483 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
484 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
485 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
486 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
487 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
488 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
490 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
491 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
492 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
493 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
494 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
495 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
496 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
497 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
498 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
499 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
500 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
501 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
502 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
503 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
504 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
505 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
507 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
508 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
509 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1
510 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
511 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1
512 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
513 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1
514 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
515 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1
516 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
517 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1
518 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
519 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1
520 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
521 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
522 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
524 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
525 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
526 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
527 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
528 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
529 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
530 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1
531 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
532 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
533 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
534 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1
535 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
536 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1
537 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
538 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1
539 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
541 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1
542 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
543 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1
544 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
545 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
546 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
547 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
548 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
549 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
550 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
551 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
552 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
553 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
554 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
555 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1
556 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
558 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1
559 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
560 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1
561 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
562 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
563 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
564 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
565 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
566 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1
567 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
568 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1
569 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
570 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1
571 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
572 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1
573 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
575 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1
576 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
577 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1
578 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
579 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
580 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
581 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
582 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
583 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
584 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
585 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
586 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
587 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
588 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
589 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
590 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
592 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1
593 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
594 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1
595 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
596 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1
597 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
598 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1
599 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
600 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1
601 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
602 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1
603 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
604 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
605 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
608 __le16 consolid_prod;
611 __le16 tx_bd_or_spq_prod;
612 __le16 updated_qm_pq_id;
659 struct e4_tstorm_core_conn_ag_ctx {
663 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
664 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
665 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
666 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
667 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1
668 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
669 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1
670 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
671 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1
672 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
673 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1
674 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
675 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
676 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
678 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
679 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
680 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
681 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
682 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
683 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
684 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
685 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
687 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
688 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
689 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
690 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
691 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
692 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
693 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
694 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
696 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
697 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
698 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
699 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
700 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
701 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
702 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
703 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
704 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
705 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
706 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
707 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
709 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
710 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
711 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
712 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
713 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
714 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
715 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
716 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
717 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
718 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
719 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
720 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
721 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
722 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
723 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
724 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
726 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
727 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
728 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
729 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
730 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
731 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
732 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
733 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
734 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
735 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
736 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
737 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
738 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
739 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
740 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
741 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
763 struct e4_ustorm_core_conn_ag_ctx {
767 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
768 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
769 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
770 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
771 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
772 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
773 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
774 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
775 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
776 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
778 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
779 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
780 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
781 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
782 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
783 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
784 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
785 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
787 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
788 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
789 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
790 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
791 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
792 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
793 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
794 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
795 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
796 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
797 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
798 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
799 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
800 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
801 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
802 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
804 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
805 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
806 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
807 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
808 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
809 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
810 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
811 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
812 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
813 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
814 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
815 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
816 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
817 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
818 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
819 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
832 /* The core storm context for the Mstorm */
833 struct mstorm_core_conn_st_ctx {
837 /* The core storm context for the Ustorm */
838 struct ustorm_core_conn_st_ctx {
842 /* The core storm context for the Tstorm */
843 struct tstorm_core_conn_st_ctx {
847 /* core connection context */
848 struct e4_core_conn_context {
849 struct ystorm_core_conn_st_ctx ystorm_st_context;
850 struct regpair ystorm_st_padding[2];
851 struct pstorm_core_conn_st_ctx pstorm_st_context;
852 struct regpair pstorm_st_padding[2];
853 struct xstorm_core_conn_st_ctx xstorm_st_context;
854 struct e4_xstorm_core_conn_ag_ctx xstorm_ag_context;
855 struct e4_tstorm_core_conn_ag_ctx tstorm_ag_context;
856 struct e4_ustorm_core_conn_ag_ctx ustorm_ag_context;
857 struct mstorm_core_conn_st_ctx mstorm_st_context;
858 struct ustorm_core_conn_st_ctx ustorm_st_context;
859 struct regpair ustorm_st_padding[2];
860 struct tstorm_core_conn_st_ctx tstorm_st_context;
861 struct regpair tstorm_st_padding[2];
864 struct eth_mstorm_per_pf_stat {
865 struct regpair gre_discard_pkts;
866 struct regpair vxlan_discard_pkts;
867 struct regpair geneve_discard_pkts;
868 struct regpair lb_discard_pkts;
871 struct eth_mstorm_per_queue_stat {
872 struct regpair ttl0_discard;
873 struct regpair packet_too_big_discard;
874 struct regpair no_buff_discard;
875 struct regpair not_active_discard;
876 struct regpair tpa_coalesced_pkts;
877 struct regpair tpa_coalesced_events;
878 struct regpair tpa_aborts_num;
879 struct regpair tpa_coalesced_bytes;
882 /* Ethernet TX Per PF */
883 struct eth_pstorm_per_pf_stat {
884 struct regpair sent_lb_ucast_bytes;
885 struct regpair sent_lb_mcast_bytes;
886 struct regpair sent_lb_bcast_bytes;
887 struct regpair sent_lb_ucast_pkts;
888 struct regpair sent_lb_mcast_pkts;
889 struct regpair sent_lb_bcast_pkts;
890 struct regpair sent_gre_bytes;
891 struct regpair sent_vxlan_bytes;
892 struct regpair sent_geneve_bytes;
893 struct regpair sent_mpls_bytes;
894 struct regpair sent_gre_mpls_bytes;
895 struct regpair sent_udp_mpls_bytes;
896 struct regpair sent_gre_pkts;
897 struct regpair sent_vxlan_pkts;
898 struct regpair sent_geneve_pkts;
899 struct regpair sent_mpls_pkts;
900 struct regpair sent_gre_mpls_pkts;
901 struct regpair sent_udp_mpls_pkts;
902 struct regpair gre_drop_pkts;
903 struct regpair vxlan_drop_pkts;
904 struct regpair geneve_drop_pkts;
905 struct regpair mpls_drop_pkts;
906 struct regpair gre_mpls_drop_pkts;
907 struct regpair udp_mpls_drop_pkts;
910 /* Ethernet TX Per Queue Stats */
911 struct eth_pstorm_per_queue_stat {
912 struct regpair sent_ucast_bytes;
913 struct regpair sent_mcast_bytes;
914 struct regpair sent_bcast_bytes;
915 struct regpair sent_ucast_pkts;
916 struct regpair sent_mcast_pkts;
917 struct regpair sent_bcast_pkts;
918 struct regpair error_drop_pkts;
921 /* ETH Rx producers data */
922 struct eth_rx_rate_limit {
930 /* Update RSS indirection table entry command */
931 struct eth_tstorm_rss_update_data {
936 __le16 ind_table_value;
940 struct eth_ustorm_per_pf_stat {
941 struct regpair rcv_lb_ucast_bytes;
942 struct regpair rcv_lb_mcast_bytes;
943 struct regpair rcv_lb_bcast_bytes;
944 struct regpair rcv_lb_ucast_pkts;
945 struct regpair rcv_lb_mcast_pkts;
946 struct regpair rcv_lb_bcast_pkts;
947 struct regpair rcv_gre_bytes;
948 struct regpair rcv_vxlan_bytes;
949 struct regpair rcv_geneve_bytes;
950 struct regpair rcv_gre_pkts;
951 struct regpair rcv_vxlan_pkts;
952 struct regpair rcv_geneve_pkts;
955 struct eth_ustorm_per_queue_stat {
956 struct regpair rcv_ucast_bytes;
957 struct regpair rcv_mcast_bytes;
958 struct regpair rcv_bcast_bytes;
959 struct regpair rcv_ucast_pkts;
960 struct regpair rcv_mcast_pkts;
961 struct regpair rcv_bcast_pkts;
964 /* Event Ring VF-PF Channel data */
965 struct vf_pf_channel_eqe_data {
966 struct regpair msg_addr;
969 /* Event Ring malicious VF data */
970 struct malicious_vf_eqe_data {
976 /* Event Ring initial cleanup data */
977 struct initial_cleanup_eqe_data {
982 /* Event Data Union */
983 union event_ring_data {
985 struct vf_pf_channel_eqe_data vf_pf_channel;
986 struct iscsi_eqe_data iscsi_info;
987 struct iscsi_connect_done_results iscsi_conn_done_info;
988 union rdma_eqe_data rdma_data;
989 struct malicious_vf_eqe_data malicious_vf;
990 struct initial_cleanup_eqe_data vf_init_cleanup;
993 /* Event Ring Entry */
994 struct event_ring_entry {
1002 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1
1003 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0
1004 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
1005 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
1006 union event_ring_data data;
1009 /* Event Ring Next Page Address */
1010 struct event_ring_next_addr {
1011 struct regpair addr;
1015 /* Event Ring Element */
1016 union event_ring_element {
1017 struct event_ring_entry entry;
1018 struct event_ring_next_addr next_addr;
1022 enum fw_flow_ctrl_mode {
1025 MAX_FW_FLOW_CTRL_MODE
1028 /* GFT profile type */
1029 enum gft_profile_type {
1030 GFT_PROFILE_TYPE_4_TUPLE,
1031 GFT_PROFILE_TYPE_L4_DST_PORT,
1032 GFT_PROFILE_TYPE_IP_DST_ADDR,
1033 GFT_PROFILE_TYPE_IP_SRC_ADDR,
1034 GFT_PROFILE_TYPE_TUNNEL_TYPE,
1035 MAX_GFT_PROFILE_TYPE
1038 /* Major and Minor hsi Versions */
1039 struct hsi_fp_ver_struct {
1040 u8 minor_ver_arr[2];
1041 u8 major_ver_arr[2];
1044 enum iwarp_ll2_tx_queues {
1045 IWARP_LL2_IN_ORDER_TX_QUEUE = 1,
1046 IWARP_LL2_ALIGNED_TX_QUEUE,
1047 IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE,
1049 MAX_IWARP_LL2_TX_QUEUES
1052 /* Malicious VF error ID */
1053 enum malicious_vf_error_id {
1054 MALICIOUS_VF_NO_ERROR,
1055 VF_PF_CHANNEL_NOT_READY,
1056 VF_ZONE_MSG_NOT_VALID,
1057 VF_ZONE_FUNC_NOT_ENABLED,
1058 ETH_PACKET_TOO_SMALL,
1059 ETH_ILLEGAL_VLAN_MODE,
1061 ETH_ILLEGAL_INBAND_TAGS,
1062 ETH_VLAN_INSERT_AND_INBAND_VLAN,
1064 ETH_FIRST_BD_WO_SOP,
1065 ETH_INSUFFICIENT_BDS,
1066 ETH_ILLEGAL_LSO_HDR_NBDS,
1067 ETH_ILLEGAL_LSO_MSS,
1069 ETH_ILLEGAL_LSO_HDR_LEN,
1070 ETH_INSUFFICIENT_PAYLOAD,
1071 ETH_EDPM_OUT_OF_SYNC,
1072 ETH_TUNN_IPV6_EXT_NBD_ERR,
1073 ETH_CONTROL_PACKET_VIOLATION,
1074 ETH_ANTI_SPOOFING_ERR,
1075 ETH_PACKET_SIZE_TOO_LARGE,
1076 CORE_ILLEGAL_VLAN_MODE,
1078 CORE_FIRST_BD_WO_SOP,
1079 CORE_INSUFFICIENT_BDS,
1080 CORE_PACKET_TOO_SMALL,
1081 CORE_ILLEGAL_INBAND_TAGS,
1082 CORE_VLAN_INSERT_AND_INBAND_VLAN,
1084 CORE_CONTROL_PACKET_VIOLATION,
1085 CORE_ANTI_SPOOFING_ERR,
1086 CORE_PACKET_SIZE_TOO_LARGE,
1087 CORE_ILLEGAL_BD_FLAGS,
1088 CORE_GSI_PACKET_VIOLATION,
1089 MAX_MALICIOUS_VF_ERROR_ID,
1092 /* Mstorm non-triggering VF zone */
1093 struct mstorm_non_trigger_vf_zone {
1094 struct eth_mstorm_per_queue_stat eth_queue_stat;
1095 struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
1098 /* Mstorm VF zone */
1099 struct mstorm_vf_zone {
1100 struct mstorm_non_trigger_vf_zone non_trigger;
1103 /* vlan header including TPID and TCI fields */
1104 struct vlan_header {
1109 /* outer tag configurations */
1110 struct outer_tag_config_struct {
1111 u8 enable_stag_pri_change;
1114 struct vlan_header outer_tag;
1115 u8 inner_to_outer_pri_map[8];
1118 /* personality per PF */
1119 enum personality_type {
1120 BAD_PERSONALITY_TYP,
1123 PERSONALITY_RDMA_AND_ETH,
1127 PERSONALITY_RESERVED,
1128 MAX_PERSONALITY_TYPE
1131 /* tunnel configuration */
1132 struct pf_start_tunnel_config {
1133 u8 set_vxlan_udp_port_flg;
1134 u8 set_geneve_udp_port_flg;
1135 u8 set_no_inner_l2_vxlan_udp_port_flg;
1136 u8 tunnel_clss_vxlan;
1137 u8 tunnel_clss_l2geneve;
1138 u8 tunnel_clss_ipgeneve;
1139 u8 tunnel_clss_l2gre;
1140 u8 tunnel_clss_ipgre;
1141 __le16 vxlan_udp_port;
1142 __le16 geneve_udp_port;
1143 __le16 no_inner_l2_vxlan_udp_port;
1147 /* Ramrod data for PF start ramrod */
1148 struct pf_start_ramrod_data {
1149 struct regpair event_ring_pbl_addr;
1150 struct regpair consolid_q_pbl_addr;
1151 struct pf_start_tunnel_config tunnel_config;
1152 __le16 event_ring_sb_id;
1155 u8 event_ring_num_pages;
1156 u8 event_ring_sb_index;
1158 u8 warning_as_error;
1159 u8 dont_log_ramrods;
1161 __le16 log_type_mask;
1164 u8 allow_npar_tx_switching;
1166 struct hsi_fp_ver_struct hsi_fp_ver;
1167 struct outer_tag_config_struct outer_tag_config;
1170 /* Data for port update ramrod */
1171 struct protocol_dcb_data {
1173 u8 dscp_enable_flag;
1177 u8 dcb_dont_add_vlan0;
1180 /* Update tunnel configuration */
1181 struct pf_update_tunnel_config {
1182 u8 update_rx_pf_clss;
1183 u8 update_rx_def_ucast_clss;
1184 u8 update_rx_def_non_ucast_clss;
1185 u8 set_vxlan_udp_port_flg;
1186 u8 set_geneve_udp_port_flg;
1187 u8 set_no_inner_l2_vxlan_udp_port_flg;
1188 u8 tunnel_clss_vxlan;
1189 u8 tunnel_clss_l2geneve;
1190 u8 tunnel_clss_ipgeneve;
1191 u8 tunnel_clss_l2gre;
1192 u8 tunnel_clss_ipgre;
1194 __le16 vxlan_udp_port;
1195 __le16 geneve_udp_port;
1196 __le16 no_inner_l2_vxlan_udp_port;
1197 __le16 reserved1[3];
1200 /* Data for port update ramrod */
1201 struct pf_update_ramrod_data {
1202 u8 update_eth_dcb_data_mode;
1203 u8 update_fcoe_dcb_data_mode;
1204 u8 update_iscsi_dcb_data_mode;
1205 u8 update_roce_dcb_data_mode;
1206 u8 update_rroce_dcb_data_mode;
1207 u8 update_iwarp_dcb_data_mode;
1208 u8 update_mf_vlan_flag;
1209 u8 update_enable_stag_pri_change;
1210 struct protocol_dcb_data eth_dcb_data;
1211 struct protocol_dcb_data fcoe_dcb_data;
1212 struct protocol_dcb_data iscsi_dcb_data;
1213 struct protocol_dcb_data roce_dcb_data;
1214 struct protocol_dcb_data rroce_dcb_data;
1215 struct protocol_dcb_data iwarp_dcb_data;
1217 u8 enable_stag_pri_change;
1219 struct pf_update_tunnel_config tunnel_config;
1232 /* use to index in hsi_fp_[major|minor]_ver_arr per protocol */
1233 enum protocol_version_array_key {
1236 MAX_PROTOCOL_VERSION_ARRAY_KEY
1240 struct rdma_sent_stats {
1241 struct regpair sent_bytes;
1242 struct regpair sent_pkts;
1245 /* Pstorm non-triggering VF zone */
1246 struct pstorm_non_trigger_vf_zone {
1247 struct eth_pstorm_per_queue_stat eth_queue_stat;
1248 struct rdma_sent_stats rdma_stats;
1251 /* Pstorm VF zone */
1252 struct pstorm_vf_zone {
1253 struct pstorm_non_trigger_vf_zone non_trigger;
1254 struct regpair reserved[7];
1257 /* Ramrod Header of SPQE */
1258 struct ramrod_header {
1266 struct rdma_rcv_stats {
1267 struct regpair rcv_bytes;
1268 struct regpair rcv_pkts;
1271 /* Data for update QCN/DCQCN RL ramrod */
1272 struct rl_update_ramrod_data {
1273 u8 qcn_update_param_flg;
1274 u8 dcqcn_update_param_flg;
1281 u8 dcqcn_reset_alpha_on_idle;
1283 u8 rl_timer_stage_th;
1291 __le32 dcqcn_timeuot_us;
1292 __le32 qcn_timeuot_us;
1296 /* Slowpath Element (SPQE) */
1297 struct slow_path_element {
1298 struct ramrod_header hdr;
1299 struct regpair data_ptr;
1302 /* Tstorm non-triggering VF zone */
1303 struct tstorm_non_trigger_vf_zone {
1304 struct rdma_rcv_stats rdma_stats;
1307 struct tstorm_per_port_stat {
1308 struct regpair trunc_error_discard;
1309 struct regpair mac_error_discard;
1310 struct regpair mftag_filter_discard;
1311 struct regpair eth_mac_filter_discard;
1312 struct regpair ll2_mac_filter_discard;
1313 struct regpair ll2_conn_disabled_discard;
1314 struct regpair iscsi_irregular_pkt;
1315 struct regpair fcoe_irregular_pkt;
1316 struct regpair roce_irregular_pkt;
1317 struct regpair iwarp_irregular_pkt;
1318 struct regpair eth_irregular_pkt;
1319 struct regpair toe_irregular_pkt;
1320 struct regpair preroce_irregular_pkt;
1321 struct regpair eth_gre_tunn_filter_discard;
1322 struct regpair eth_vxlan_tunn_filter_discard;
1323 struct regpair eth_geneve_tunn_filter_discard;
1324 struct regpair eth_gft_drop_pkt;
1327 /* Tstorm VF zone */
1328 struct tstorm_vf_zone {
1329 struct tstorm_non_trigger_vf_zone non_trigger;
1332 /* Tunnel classification scheme */
1334 TUNNEL_CLSS_MAC_VLAN = 0,
1335 TUNNEL_CLSS_MAC_VNI,
1336 TUNNEL_CLSS_INNER_MAC_VLAN,
1337 TUNNEL_CLSS_INNER_MAC_VNI,
1338 TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
1342 /* Ustorm non-triggering VF zone */
1343 struct ustorm_non_trigger_vf_zone {
1344 struct eth_ustorm_per_queue_stat eth_queue_stat;
1345 struct regpair vf_pf_msg_addr;
1348 /* Ustorm triggering VF zone */
1349 struct ustorm_trigger_vf_zone {
1354 /* Ustorm VF zone */
1355 struct ustorm_vf_zone {
1356 struct ustorm_non_trigger_vf_zone non_trigger;
1357 struct ustorm_trigger_vf_zone trigger;
1360 /* VF-PF channel data */
1361 struct vf_pf_channel_data {
1368 /* Ramrod data for VF start ramrod */
1369 struct vf_start_ramrod_data {
1375 struct hsi_fp_ver_struct hsi_fp_ver;
1379 /* Ramrod data for VF start ramrod */
1380 struct vf_stop_ramrod_data {
1387 /* VF zone size mode */
1388 enum vf_zone_size_mode {
1389 VF_ZONE_SIZE_MODE_DEFAULT,
1390 VF_ZONE_SIZE_MODE_DOUBLE,
1391 VF_ZONE_SIZE_MODE_QUAD,
1392 MAX_VF_ZONE_SIZE_MODE
1395 /* Xstorm non-triggering VF zone */
1396 struct xstorm_non_trigger_vf_zone {
1397 struct regpair non_edpm_ack_pkts;
1400 /* Tstorm VF zone */
1401 struct xstorm_vf_zone {
1402 struct xstorm_non_trigger_vf_zone non_trigger;
1405 /* Attentions status block */
1406 struct atten_status_block {
1417 #define DMAE_CMD_SRC_MASK 0x1
1418 #define DMAE_CMD_SRC_SHIFT 0
1419 #define DMAE_CMD_DST_MASK 0x3
1420 #define DMAE_CMD_DST_SHIFT 1
1421 #define DMAE_CMD_C_DST_MASK 0x1
1422 #define DMAE_CMD_C_DST_SHIFT 3
1423 #define DMAE_CMD_CRC_RESET_MASK 0x1
1424 #define DMAE_CMD_CRC_RESET_SHIFT 4
1425 #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
1426 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5
1427 #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
1428 #define DMAE_CMD_DST_ADDR_RESET_SHIFT 6
1429 #define DMAE_CMD_COMP_FUNC_MASK 0x1
1430 #define DMAE_CMD_COMP_FUNC_SHIFT 7
1431 #define DMAE_CMD_COMP_WORD_EN_MASK 0x1
1432 #define DMAE_CMD_COMP_WORD_EN_SHIFT 8
1433 #define DMAE_CMD_COMP_CRC_EN_MASK 0x1
1434 #define DMAE_CMD_COMP_CRC_EN_SHIFT 9
1435 #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7
1436 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
1437 #define DMAE_CMD_RESERVED1_MASK 0x1
1438 #define DMAE_CMD_RESERVED1_SHIFT 13
1439 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
1440 #define DMAE_CMD_ENDIANITY_MODE_SHIFT 14
1441 #define DMAE_CMD_ERR_HANDLING_MASK 0x3
1442 #define DMAE_CMD_ERR_HANDLING_SHIFT 16
1443 #define DMAE_CMD_PORT_ID_MASK 0x3
1444 #define DMAE_CMD_PORT_ID_SHIFT 18
1445 #define DMAE_CMD_SRC_PF_ID_MASK 0xF
1446 #define DMAE_CMD_SRC_PF_ID_SHIFT 20
1447 #define DMAE_CMD_DST_PF_ID_MASK 0xF
1448 #define DMAE_CMD_DST_PF_ID_SHIFT 24
1449 #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1
1450 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
1451 #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1
1452 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
1453 #define DMAE_CMD_RESERVED2_MASK 0x3
1454 #define DMAE_CMD_RESERVED2_SHIFT 30
1461 #define DMAE_CMD_SRC_VF_ID_MASK 0xFF
1462 #define DMAE_CMD_SRC_VF_ID_SHIFT 0
1463 #define DMAE_CMD_DST_VF_ID_MASK 0xFF
1464 #define DMAE_CMD_DST_VF_ID_SHIFT 8
1465 __le32 comp_addr_lo;
1466 __le32 comp_addr_hi;
1473 __le16 error_bit_reserved;
1474 #define DMAE_CMD_ERROR_BIT_MASK 0x1
1475 #define DMAE_CMD_ERROR_BIT_SHIFT 0
1476 #define DMAE_CMD_RESERVED_MASK 0x7FFF
1477 #define DMAE_CMD_RESERVED_SHIFT 1
1482 enum dmae_cmd_comp_crc_en_enum {
1483 dmae_cmd_comp_crc_disabled,
1484 dmae_cmd_comp_crc_enabled,
1485 MAX_DMAE_CMD_COMP_CRC_EN_ENUM
1488 enum dmae_cmd_comp_func_enum {
1489 dmae_cmd_comp_func_to_src,
1490 dmae_cmd_comp_func_to_dst,
1491 MAX_DMAE_CMD_COMP_FUNC_ENUM
1494 enum dmae_cmd_comp_word_en_enum {
1495 dmae_cmd_comp_word_disabled,
1496 dmae_cmd_comp_word_enabled,
1497 MAX_DMAE_CMD_COMP_WORD_EN_ENUM
1500 enum dmae_cmd_c_dst_enum {
1501 dmae_cmd_c_dst_pcie,
1503 MAX_DMAE_CMD_C_DST_ENUM
1506 enum dmae_cmd_dst_enum {
1507 dmae_cmd_dst_none_0,
1510 dmae_cmd_dst_none_3,
1511 MAX_DMAE_CMD_DST_ENUM
1514 enum dmae_cmd_error_handling_enum {
1515 dmae_cmd_error_handling_send_regular_comp,
1516 dmae_cmd_error_handling_send_comp_with_err,
1517 dmae_cmd_error_handling_dont_send_comp,
1518 MAX_DMAE_CMD_ERROR_HANDLING_ENUM
1521 enum dmae_cmd_src_enum {
1524 MAX_DMAE_CMD_SRC_ENUM
1527 struct e4_mstorm_core_conn_ag_ctx {
1531 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1532 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1533 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1534 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
1535 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1536 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
1537 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1538 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
1539 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1540 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
1542 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1543 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1544 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1545 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
1546 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1547 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
1548 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1549 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
1550 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1551 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
1552 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1553 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
1554 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1555 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
1556 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1557 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
1564 struct e4_ystorm_core_conn_ag_ctx {
1568 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1569 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1570 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1571 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
1572 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1573 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
1574 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1575 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
1576 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1577 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
1579 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1580 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1581 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1582 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
1583 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1584 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
1585 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1586 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3
1587 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1588 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4
1589 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1590 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5
1591 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1592 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6
1593 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1594 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7
1608 /* DMAE parameters */
1609 struct qed_dmae_params {
1611 /* If QED_DMAE_PARAMS_RW_REPL_SRC flag is set and the
1612 * source is a block of length DMAE_MAX_RW_SIZE and the
1613 * destination is larger, the source block will be duplicated as
1614 * many times as required to fill the destination block. This is
1615 * used mostly to write a zeroed buffer to destination address
1618 #define QED_DMAE_PARAMS_RW_REPL_SRC_MASK 0x1
1619 #define QED_DMAE_PARAMS_RW_REPL_SRC_SHIFT 0
1620 #define QED_DMAE_PARAMS_SRC_VF_VALID_MASK 0x1
1621 #define QED_DMAE_PARAMS_SRC_VF_VALID_SHIFT 1
1622 #define QED_DMAE_PARAMS_DST_VF_VALID_MASK 0x1
1623 #define QED_DMAE_PARAMS_DST_VF_VALID_SHIFT 2
1624 #define QED_DMAE_PARAMS_COMPLETION_DST_MASK 0x1
1625 #define QED_DMAE_PARAMS_COMPLETION_DST_SHIFT 3
1626 #define QED_DMAE_PARAMS_PORT_VALID_MASK 0x1
1627 #define QED_DMAE_PARAMS_PORT_VALID_SHIFT 4
1628 #define QED_DMAE_PARAMS_SRC_PF_VALID_MASK 0x1
1629 #define QED_DMAE_PARAMS_SRC_PF_VALID_SHIFT 5
1630 #define QED_DMAE_PARAMS_DST_PF_VALID_MASK 0x1
1631 #define QED_DMAE_PARAMS_DST_PF_VALID_SHIFT 6
1632 #define QED_DMAE_PARAMS_RESERVED_MASK 0x1FFFFFF
1633 #define QED_DMAE_PARAMS_RESERVED_SHIFT 7
1643 /* IGU cleanup command */
1644 struct igu_cleanup {
1645 __le32 sb_id_and_flags;
1646 #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF
1647 #define IGU_CLEANUP_RESERVED0_SHIFT 0
1648 #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1
1649 #define IGU_CLEANUP_CLEANUP_SET_SHIFT 27
1650 #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7
1651 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
1652 #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1
1653 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
1657 /* IGU firmware driver command */
1659 struct igu_prod_cons_update prod_cons_update;
1660 struct igu_cleanup cleanup;
1663 /* IGU firmware driver command */
1664 struct igu_command_reg_ctrl {
1666 __le16 igu_command_reg_ctrl_fields;
1667 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF
1668 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
1669 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7
1670 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12
1671 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
1672 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
1675 /* IGU mapping line structure */
1676 struct igu_mapping_line {
1677 __le32 igu_mapping_line_fields;
1678 #define IGU_MAPPING_LINE_VALID_MASK 0x1
1679 #define IGU_MAPPING_LINE_VALID_SHIFT 0
1680 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF
1681 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1
1682 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF
1683 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
1684 #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1
1685 #define IGU_MAPPING_LINE_PF_VALID_SHIFT 17
1686 #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F
1687 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18
1688 #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF
1689 #define IGU_MAPPING_LINE_RESERVED_SHIFT 24
1692 /* IGU MSIX line structure */
1693 struct igu_msix_vector {
1694 struct regpair address;
1696 __le32 msix_vector_fields;
1697 #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
1698 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0
1699 #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF
1700 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1
1701 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF
1702 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16
1703 #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF
1704 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24
1706 /* per encapsulation type enabling flags */
1707 struct prs_reg_encapsulation_type_en {
1709 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
1710 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0
1711 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
1712 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1
1713 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
1714 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2
1715 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
1716 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3
1717 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
1718 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
1719 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
1720 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5
1721 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
1722 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6
1725 enum pxp_tph_st_hint {
1727 TPH_ST_HINT_REQUESTER,
1729 TPH_ST_HINT_TARGET_PRIO,
1733 /* QM hardware structure of enable bypass credit mask */
1734 struct qm_rf_bypass_mask {
1736 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
1737 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0
1738 #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
1739 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1
1740 #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
1741 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2
1742 #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
1743 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3
1744 #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
1745 #define QM_RF_BYPASS_MASK_PFRL_SHIFT 4
1746 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
1747 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5
1748 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
1749 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6
1750 #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
1751 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
1754 /* QM hardware structure of opportunistic credit mask */
1755 struct qm_rf_opportunistic_mask {
1757 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
1758 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0
1759 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
1760 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1
1761 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
1762 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2
1763 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
1764 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3
1765 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
1766 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4
1767 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
1768 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5
1769 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
1770 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6
1771 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
1772 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7
1773 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
1774 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8
1775 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F
1776 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9
1779 /* QM hardware structure of QM map memory */
1780 struct qm_rf_pq_map_e4 {
1782 #define QM_RF_PQ_MAP_E4_PQ_VALID_MASK 0x1
1783 #define QM_RF_PQ_MAP_E4_PQ_VALID_SHIFT 0
1784 #define QM_RF_PQ_MAP_E4_RL_ID_MASK 0xFF
1785 #define QM_RF_PQ_MAP_E4_RL_ID_SHIFT 1
1786 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_MASK 0x1FF
1787 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_SHIFT 9
1788 #define QM_RF_PQ_MAP_E4_VOQ_MASK 0x1F
1789 #define QM_RF_PQ_MAP_E4_VOQ_SHIFT 18
1790 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_MASK 0x3
1791 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_SHIFT 23
1792 #define QM_RF_PQ_MAP_E4_RL_VALID_MASK 0x1
1793 #define QM_RF_PQ_MAP_E4_RL_VALID_SHIFT 25
1794 #define QM_RF_PQ_MAP_E4_RESERVED_MASK 0x3F
1795 #define QM_RF_PQ_MAP_E4_RESERVED_SHIFT 26
1798 /* Completion params for aggregated interrupt completion */
1799 struct sdm_agg_int_comp_params {
1801 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F
1802 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0
1803 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1
1804 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
1805 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF
1806 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7
1809 /* SDM operation gen command (generate aggregative interrupt) */
1812 #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF
1813 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
1814 #define SDM_OP_GEN_COMP_TYPE_MASK 0xF
1815 #define SDM_OP_GEN_COMP_TYPE_SHIFT 16
1816 #define SDM_OP_GEN_RESERVED_MASK 0xFFF
1817 #define SDM_OP_GEN_RESERVED_SHIFT 20
1820 /* Physical memory descriptor */
1821 struct phys_mem_desc {
1822 dma_addr_t phys_addr;
1824 u32 size; /* In bytes */
1827 /* Virtual memory descriptor */
1828 struct virt_mem_desc {
1830 u32 size; /* In bytes */
1833 /****************************************/
1834 /* Debug Tools HSI constants and macros */
1835 /****************************************/
1925 BLOCK_NIG_LB_FC_PLLH,
1926 BLOCK_NIG_TX_FC_PLLH,
1928 BLOCK_NIG_RX_FC_PLLH,
1933 /* binary debug buffer types */
1934 enum bin_dbg_buffer_type {
1935 BIN_BUF_DBG_MODE_TREE,
1936 BIN_BUF_DBG_DUMP_REG,
1937 BIN_BUF_DBG_DUMP_MEM,
1938 BIN_BUF_DBG_IDLE_CHK_REGS,
1939 BIN_BUF_DBG_IDLE_CHK_IMMS,
1940 BIN_BUF_DBG_IDLE_CHK_RULES,
1941 BIN_BUF_DBG_IDLE_CHK_PARSING_DATA,
1942 BIN_BUF_DBG_ATTN_BLOCKS,
1943 BIN_BUF_DBG_ATTN_REGS,
1944 BIN_BUF_DBG_ATTN_INDEXES,
1945 BIN_BUF_DBG_ATTN_NAME_OFFSETS,
1947 BIN_BUF_DBG_BLOCKS_CHIP_DATA,
1948 BIN_BUF_DBG_BUS_LINES,
1949 BIN_BUF_DBG_BLOCKS_USER_DATA,
1950 BIN_BUF_DBG_BLOCKS_CHIP_USER_DATA,
1951 BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS,
1952 BIN_BUF_DBG_RESET_REGS,
1953 BIN_BUF_DBG_PARSING_STRINGS,
1954 MAX_BIN_DBG_BUFFER_TYPE
1958 /* Attention bit mapping */
1959 struct dbg_attn_bit_mapping {
1961 #define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF
1962 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0
1963 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1
1964 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15
1967 /* Attention block per-type data */
1968 struct dbg_attn_block_type_data {
1977 /* Block attentions */
1978 struct dbg_attn_block {
1979 struct dbg_attn_block_type_data per_type_data[2];
1982 /* Attention register result */
1983 struct dbg_attn_reg_result {
1985 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF
1986 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0
1987 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF
1988 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT 24
1989 u16 block_attn_offset;
1995 /* Attention block result */
1996 struct dbg_attn_block_result {
1999 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3
2000 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0
2001 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F
2002 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2
2004 struct dbg_attn_reg_result reg_results[15];
2008 struct dbg_mode_hdr {
2010 #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1
2011 #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0
2012 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF
2013 #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1
2016 /* Attention register */
2017 struct dbg_attn_reg {
2018 struct dbg_mode_hdr mode;
2019 u16 block_attn_offset;
2021 #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF
2022 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0
2023 #define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF
2024 #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24
2025 u32 sts_clr_address;
2029 /* Attention types */
2030 enum dbg_attn_type {
2031 ATTN_TYPE_INTERRUPT,
2036 /* Block debug data */
2039 u8 associated_storm_letter;
2042 /* Chip-specific block debug data */
2043 struct dbg_block_chip {
2045 #define DBG_BLOCK_CHIP_IS_REMOVED_MASK 0x1
2046 #define DBG_BLOCK_CHIP_IS_REMOVED_SHIFT 0
2047 #define DBG_BLOCK_CHIP_HAS_RESET_REG_MASK 0x1
2048 #define DBG_BLOCK_CHIP_HAS_RESET_REG_SHIFT 1
2049 #define DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP_MASK 0x1
2050 #define DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP_SHIFT 2
2051 #define DBG_BLOCK_CHIP_HAS_DBG_BUS_MASK 0x1
2052 #define DBG_BLOCK_CHIP_HAS_DBG_BUS_SHIFT 3
2053 #define DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS_MASK 0x1
2054 #define DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS_SHIFT 4
2055 #define DBG_BLOCK_CHIP_RESERVED0_MASK 0x7
2056 #define DBG_BLOCK_CHIP_RESERVED0_SHIFT 5
2059 u8 reset_reg_bit_offset;
2060 struct dbg_mode_hdr dbg_bus_mode;
2063 u8 num_of_dbg_bus_lines;
2064 u16 dbg_bus_lines_offset;
2065 u32 dbg_select_reg_addr;
2066 u32 dbg_dword_enable_reg_addr;
2067 u32 dbg_shift_reg_addr;
2068 u32 dbg_force_valid_reg_addr;
2069 u32 dbg_force_frame_reg_addr;
2072 /* Chip-specific block user debug data */
2073 struct dbg_block_chip_user {
2074 u8 num_of_dbg_bus_lines;
2075 u8 has_latency_events;
2079 /* Block user debug data */
2080 struct dbg_block_user {
2084 /* Block Debug line data */
2085 struct dbg_bus_line {
2087 #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF
2088 #define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0
2089 #define DBG_BUS_LINE_IS_256B_MASK 0x1
2090 #define DBG_BUS_LINE_IS_256B_SHIFT 4
2091 #define DBG_BUS_LINE_RESERVED_MASK 0x7
2092 #define DBG_BUS_LINE_RESERVED_SHIFT 5
2096 /* Condition header for registers dump */
2097 struct dbg_dump_cond_hdr {
2098 struct dbg_mode_hdr mode; /* Mode header */
2099 u8 block_id; /* block ID */
2100 u8 data_size; /* size in dwords of the data following this header */
2103 /* Memory data for registers dump */
2104 struct dbg_dump_mem {
2106 #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF
2107 #define DBG_DUMP_MEM_ADDRESS_SHIFT 0
2108 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF
2109 #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24
2111 #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF
2112 #define DBG_DUMP_MEM_LENGTH_SHIFT 0
2113 #define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1
2114 #define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24
2115 #define DBG_DUMP_MEM_RESERVED_MASK 0x7F
2116 #define DBG_DUMP_MEM_RESERVED_SHIFT 25
2119 /* Register data for registers dump */
2120 struct dbg_dump_reg {
2122 #define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF
2123 #define DBG_DUMP_REG_ADDRESS_SHIFT 0
2124 #define DBG_DUMP_REG_WIDE_BUS_MASK 0x1
2125 #define DBG_DUMP_REG_WIDE_BUS_SHIFT 23
2126 #define DBG_DUMP_REG_LENGTH_MASK 0xFF
2127 #define DBG_DUMP_REG_LENGTH_SHIFT 24
2130 /* Split header for registers dump */
2131 struct dbg_dump_split_hdr {
2133 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF
2134 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0
2135 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF
2136 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24
2139 /* Condition header for idle check */
2140 struct dbg_idle_chk_cond_hdr {
2141 struct dbg_mode_hdr mode; /* Mode header */
2142 u16 data_size; /* size in dwords of the data following this header */
2145 /* Idle Check condition register */
2146 struct dbg_idle_chk_cond_reg {
2148 #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF
2149 #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0
2150 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1
2151 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23
2152 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF
2153 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24
2159 /* Idle Check info register */
2160 struct dbg_idle_chk_info_reg {
2162 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF
2163 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0
2164 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1
2165 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23
2166 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF
2167 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24
2168 u16 size; /* register size in dwords */
2169 struct dbg_mode_hdr mode; /* Mode header */
2172 /* Idle Check register */
2173 union dbg_idle_chk_reg {
2174 struct dbg_idle_chk_cond_reg cond_reg; /* condition register */
2175 struct dbg_idle_chk_info_reg info_reg; /* info register */
2178 /* Idle Check result header */
2179 struct dbg_idle_chk_result_hdr {
2180 u16 rule_id; /* Failing rule index */
2181 u16 mem_entry_id; /* Failing memory entry index */
2182 u8 num_dumped_cond_regs; /* number of dumped condition registers */
2183 u8 num_dumped_info_regs; /* number of dumped condition registers */
2184 u8 severity; /* from dbg_idle_chk_severity_types enum */
2188 /* Idle Check result register header */
2189 struct dbg_idle_chk_result_reg_hdr {
2191 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1
2192 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0
2193 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F
2194 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1
2195 u8 start_entry; /* index of the first checked entry */
2196 u16 size; /* register size in dwords */
2199 /* Idle Check rule */
2200 struct dbg_idle_chk_rule {
2201 u16 rule_id; /* Idle Check rule ID */
2202 u8 severity; /* value from dbg_idle_chk_severity_types enum */
2203 u8 cond_id; /* Condition ID */
2204 u8 num_cond_regs; /* number of condition registers */
2205 u8 num_info_regs; /* number of info registers */
2206 u8 num_imms; /* number of immediates in the condition */
2208 u16 reg_offset; /* offset of this rules registers in the idle check
2209 * register array (in dbg_idle_chk_reg units).
2211 u16 imm_offset; /* offset of this rules immediate values in the
2212 * immediate values array (in dwords).
2216 /* Idle Check rule parsing data */
2217 struct dbg_idle_chk_rule_parsing_data {
2219 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1
2220 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0
2221 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF
2222 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1
2225 /* Idle check severity types */
2226 enum dbg_idle_chk_severity_types {
2227 /* idle check failure should cause an error */
2228 IDLE_CHK_SEVERITY_ERROR,
2229 /* idle check failure should cause an error only if theres no traffic */
2230 IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
2231 /* idle check failure should cause a warning */
2232 IDLE_CHK_SEVERITY_WARNING,
2233 MAX_DBG_IDLE_CHK_SEVERITY_TYPES
2236 /* Reset register */
2237 struct dbg_reset_reg {
2239 #define DBG_RESET_REG_ADDR_MASK 0xFFFFFF
2240 #define DBG_RESET_REG_ADDR_SHIFT 0
2241 #define DBG_RESET_REG_IS_REMOVED_MASK 0x1
2242 #define DBG_RESET_REG_IS_REMOVED_SHIFT 24
2243 #define DBG_RESET_REG_RESERVED_MASK 0x7F
2244 #define DBG_RESET_REG_RESERVED_SHIFT 25
2247 /* Debug Bus block data */
2248 struct dbg_bus_block_data {
2251 u8 force_valid_mask;
2252 u8 force_frame_mask;
2257 #define DBG_BUS_BLOCK_DATA_IS_256B_LINE_MASK 0x1
2258 #define DBG_BUS_BLOCK_DATA_IS_256B_LINE_SHIFT 0
2259 #define DBG_BUS_BLOCK_DATA_RESERVED_MASK 0x7F
2260 #define DBG_BUS_BLOCK_DATA_RESERVED_SHIFT 1
2263 enum dbg_bus_clients {
2264 DBG_BUS_CLIENT_RBCN,
2265 DBG_BUS_CLIENT_RBCP,
2266 DBG_BUS_CLIENT_RBCR,
2267 DBG_BUS_CLIENT_RBCT,
2268 DBG_BUS_CLIENT_RBCU,
2269 DBG_BUS_CLIENT_RBCF,
2270 DBG_BUS_CLIENT_RBCX,
2271 DBG_BUS_CLIENT_RBCS,
2272 DBG_BUS_CLIENT_RBCH,
2273 DBG_BUS_CLIENT_RBCZ,
2274 DBG_BUS_CLIENT_OTHER_ENGINE,
2275 DBG_BUS_CLIENT_TIMESTAMP,
2277 DBG_BUS_CLIENT_RBCY,
2278 DBG_BUS_CLIENT_RBCQ,
2279 DBG_BUS_CLIENT_RBCM,
2280 DBG_BUS_CLIENT_RBCB,
2281 DBG_BUS_CLIENT_RBCW,
2282 DBG_BUS_CLIENT_RBCV,
2286 /* Debug Bus constraint operation types */
2287 enum dbg_bus_constraint_ops {
2288 DBG_BUS_CONSTRAINT_OP_EQ,
2289 DBG_BUS_CONSTRAINT_OP_NE,
2290 DBG_BUS_CONSTRAINT_OP_LT,
2291 DBG_BUS_CONSTRAINT_OP_LTC,
2292 DBG_BUS_CONSTRAINT_OP_LE,
2293 DBG_BUS_CONSTRAINT_OP_LEC,
2294 DBG_BUS_CONSTRAINT_OP_GT,
2295 DBG_BUS_CONSTRAINT_OP_GTC,
2296 DBG_BUS_CONSTRAINT_OP_GE,
2297 DBG_BUS_CONSTRAINT_OP_GEC,
2298 MAX_DBG_BUS_CONSTRAINT_OPS
2301 /* Debug Bus trigger state data */
2302 struct dbg_bus_trigger_state_data {
2304 u8 constraint_dword_mask;
2309 /* Debug Bus memory address */
2310 struct dbg_bus_mem_addr {
2315 /* Debug Bus PCI buffer data */
2316 struct dbg_bus_pci_buf_data {
2317 struct dbg_bus_mem_addr phys_addr; /* PCI buffer physical address */
2318 struct dbg_bus_mem_addr virt_addr; /* PCI buffer virtual address */
2319 u32 size; /* PCI buffer size in bytes */
2322 /* Debug Bus Storm EID range filter params */
2323 struct dbg_bus_storm_eid_range_params {
2324 u8 min; /* Minimal event ID to filter on */
2325 u8 max; /* Maximal event ID to filter on */
2328 /* Debug Bus Storm EID mask filter params */
2329 struct dbg_bus_storm_eid_mask_params {
2330 u8 val; /* Event ID value */
2331 u8 mask; /* Event ID mask. 1s in the mask = dont care bits. */
2334 /* Debug Bus Storm EID filter params */
2335 union dbg_bus_storm_eid_params {
2336 struct dbg_bus_storm_eid_range_params range;
2337 struct dbg_bus_storm_eid_mask_params mask;
2340 /* Debug Bus Storm data */
2341 struct dbg_bus_storm_data {
2346 u8 eid_range_not_mask;
2348 union dbg_bus_storm_eid_params eid_filter_params;
2352 /* Debug Bus data */
2353 struct dbg_bus_data {
2357 u8 num_enabled_blocks;
2358 u8 num_enabled_storms;
2362 u8 timestamp_input_en;
2365 u8 filter_pre_trigger;
2366 u8 filter_post_trigger;
2368 u8 filter_constraint_dword_mask;
2369 u8 next_trigger_state;
2370 u8 next_constraint_id;
2371 struct dbg_bus_trigger_state_data trigger_states[3];
2373 u8 rcv_from_other_engine;
2374 u8 blocks_dword_mask;
2375 u8 blocks_dword_overlap;
2377 struct dbg_bus_pci_buf_data pci_buf;
2378 struct dbg_bus_block_data blocks[132];
2379 struct dbg_bus_storm_data storms[6];
2382 /* Debug bus states */
2383 enum dbg_bus_states {
2385 DBG_BUS_STATE_READY,
2386 DBG_BUS_STATE_RECORDING,
2387 DBG_BUS_STATE_STOPPED,
2391 /* Debug Bus Storm modes */
2392 enum dbg_bus_storm_modes {
2393 DBG_BUS_STORM_MODE_PRINTF,
2394 DBG_BUS_STORM_MODE_PRAM_ADDR,
2395 DBG_BUS_STORM_MODE_DRA_RW,
2396 DBG_BUS_STORM_MODE_DRA_W,
2397 DBG_BUS_STORM_MODE_LD_ST_ADDR,
2398 DBG_BUS_STORM_MODE_DRA_FSM,
2399 DBG_BUS_STORM_MODE_FAST_DBGMUX,
2400 DBG_BUS_STORM_MODE_RH,
2401 DBG_BUS_STORM_MODE_RH_WITH_STORE,
2402 DBG_BUS_STORM_MODE_FOC,
2403 DBG_BUS_STORM_MODE_EXT_STORE,
2404 MAX_DBG_BUS_STORM_MODES
2407 /* Debug bus target IDs */
2408 enum dbg_bus_targets {
2409 DBG_BUS_TARGET_ID_INT_BUF,
2410 DBG_BUS_TARGET_ID_NIG,
2411 DBG_BUS_TARGET_ID_PCI,
2416 struct dbg_grc_data {
2417 u8 params_initialized;
2423 /* Debug GRC params */
2424 enum dbg_grc_params {
2425 DBG_GRC_PARAM_DUMP_TSTORM,
2426 DBG_GRC_PARAM_DUMP_MSTORM,
2427 DBG_GRC_PARAM_DUMP_USTORM,
2428 DBG_GRC_PARAM_DUMP_XSTORM,
2429 DBG_GRC_PARAM_DUMP_YSTORM,
2430 DBG_GRC_PARAM_DUMP_PSTORM,
2431 DBG_GRC_PARAM_DUMP_REGS,
2432 DBG_GRC_PARAM_DUMP_RAM,
2433 DBG_GRC_PARAM_DUMP_PBUF,
2434 DBG_GRC_PARAM_DUMP_IOR,
2435 DBG_GRC_PARAM_DUMP_VFC,
2436 DBG_GRC_PARAM_DUMP_CM_CTX,
2437 DBG_GRC_PARAM_DUMP_PXP,
2438 DBG_GRC_PARAM_DUMP_RSS,
2439 DBG_GRC_PARAM_DUMP_CAU,
2440 DBG_GRC_PARAM_DUMP_QM,
2441 DBG_GRC_PARAM_DUMP_MCP,
2442 DBG_GRC_PARAM_DUMP_DORQ,
2443 DBG_GRC_PARAM_DUMP_CFC,
2444 DBG_GRC_PARAM_DUMP_IGU,
2445 DBG_GRC_PARAM_DUMP_BRB,
2446 DBG_GRC_PARAM_DUMP_BTB,
2447 DBG_GRC_PARAM_DUMP_BMB,
2448 DBG_GRC_PARAM_RESERVD1,
2449 DBG_GRC_PARAM_DUMP_MULD,
2450 DBG_GRC_PARAM_DUMP_PRS,
2451 DBG_GRC_PARAM_DUMP_DMAE,
2452 DBG_GRC_PARAM_DUMP_TM,
2453 DBG_GRC_PARAM_DUMP_SDM,
2454 DBG_GRC_PARAM_DUMP_DIF,
2455 DBG_GRC_PARAM_DUMP_STATIC,
2456 DBG_GRC_PARAM_UNSTALL,
2457 DBG_GRC_PARAM_RESERVED2,
2458 DBG_GRC_PARAM_MCP_TRACE_META_SIZE,
2459 DBG_GRC_PARAM_EXCLUDE_ALL,
2460 DBG_GRC_PARAM_CRASH,
2461 DBG_GRC_PARAM_PARITY_SAFE,
2462 DBG_GRC_PARAM_DUMP_CM,
2463 DBG_GRC_PARAM_DUMP_PHY,
2464 DBG_GRC_PARAM_NO_MCP,
2465 DBG_GRC_PARAM_NO_FW_VER,
2466 DBG_GRC_PARAM_RESERVED3,
2467 DBG_GRC_PARAM_DUMP_MCP_HW_DUMP,
2468 DBG_GRC_PARAM_DUMP_ILT_CDUC,
2469 DBG_GRC_PARAM_DUMP_ILT_CDUT,
2470 DBG_GRC_PARAM_DUMP_CAU_EXT,
2474 /* Debug status codes */
2477 DBG_STATUS_APP_VERSION_NOT_SET,
2478 DBG_STATUS_UNSUPPORTED_APP_VERSION,
2479 DBG_STATUS_DBG_BLOCK_NOT_RESET,
2480 DBG_STATUS_INVALID_ARGS,
2481 DBG_STATUS_OUTPUT_ALREADY_SET,
2482 DBG_STATUS_INVALID_PCI_BUF_SIZE,
2483 DBG_STATUS_PCI_BUF_ALLOC_FAILED,
2484 DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
2485 DBG_STATUS_INVALID_FILTER_TRIGGER_DWORDS,
2486 DBG_STATUS_NO_MATCHING_FRAMING_MODE,
2487 DBG_STATUS_VFC_READ_ERROR,
2488 DBG_STATUS_STORM_ALREADY_ENABLED,
2489 DBG_STATUS_STORM_NOT_ENABLED,
2490 DBG_STATUS_BLOCK_ALREADY_ENABLED,
2491 DBG_STATUS_BLOCK_NOT_ENABLED,
2492 DBG_STATUS_NO_INPUT_ENABLED,
2493 DBG_STATUS_NO_FILTER_TRIGGER_256B,
2494 DBG_STATUS_FILTER_ALREADY_ENABLED,
2495 DBG_STATUS_TRIGGER_ALREADY_ENABLED,
2496 DBG_STATUS_TRIGGER_NOT_ENABLED,
2497 DBG_STATUS_CANT_ADD_CONSTRAINT,
2498 DBG_STATUS_TOO_MANY_TRIGGER_STATES,
2499 DBG_STATUS_TOO_MANY_CONSTRAINTS,
2500 DBG_STATUS_RECORDING_NOT_STARTED,
2501 DBG_STATUS_DATA_DIDNT_TRIGGER,
2502 DBG_STATUS_NO_DATA_RECORDED,
2503 DBG_STATUS_DUMP_BUF_TOO_SMALL,
2504 DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
2505 DBG_STATUS_UNKNOWN_CHIP,
2506 DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
2507 DBG_STATUS_BLOCK_IN_RESET,
2508 DBG_STATUS_INVALID_TRACE_SIGNATURE,
2509 DBG_STATUS_INVALID_NVRAM_BUNDLE,
2510 DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
2511 DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
2512 DBG_STATUS_NVRAM_READ_FAILED,
2513 DBG_STATUS_IDLE_CHK_PARSE_FAILED,
2514 DBG_STATUS_MCP_TRACE_BAD_DATA,
2515 DBG_STATUS_MCP_TRACE_NO_META,
2516 DBG_STATUS_MCP_COULD_NOT_HALT,
2517 DBG_STATUS_MCP_COULD_NOT_RESUME,
2518 DBG_STATUS_RESERVED0,
2519 DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
2520 DBG_STATUS_IGU_FIFO_BAD_DATA,
2521 DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
2522 DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
2523 DBG_STATUS_REG_FIFO_BAD_DATA,
2524 DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
2525 DBG_STATUS_DBG_ARRAY_NOT_SET,
2526 DBG_STATUS_RESERVED1,
2527 DBG_STATUS_NON_MATCHING_LINES,
2528 DBG_STATUS_INSUFFICIENT_HW_IDS,
2529 DBG_STATUS_DBG_BUS_IN_USE,
2530 DBG_STATUS_INVALID_STORM_DBG_MODE,
2531 DBG_STATUS_OTHER_ENGINE_BB_ONLY,
2532 DBG_STATUS_FILTER_SINGLE_HW_ID,
2533 DBG_STATUS_TRIGGER_SINGLE_HW_ID,
2534 DBG_STATUS_MISSING_TRIGGER_STATE_STORM,
2538 /* Debug Storms IDs */
2549 /* Idle Check data */
2550 struct idle_chk_data {
2557 struct pretend_params {
2563 /* Debug Tools data (per HW function)
2565 struct dbg_tools_data {
2566 struct dbg_grc_data grc;
2567 struct dbg_bus_data bus;
2568 struct idle_chk_data idle_chk;
2570 u8 block_in_reset[132];
2574 u8 num_pfs_per_port;
2579 struct pretend_params pretend;
2596 /********************************/
2597 /* HSI Init Functions constants */
2598 /********************************/
2600 /* Number of VLAN priorities */
2601 #define NUM_OF_VLAN_PRIORITIES 8
2603 /* BRB RAM init requirements */
2604 struct init_brb_ram_req {
2605 u32 guranteed_per_tc;
2606 u32 headroom_per_tc;
2608 u32 max_ports_per_engine;
2609 u8 num_active_tcs[MAX_NUM_PORTS];
2612 /* ETS per-TC init requirements */
2613 struct init_ets_tc_req {
2619 /* ETS init requirements */
2620 struct init_ets_req {
2622 struct init_ets_tc_req tc_req[NUM_OF_TCS];
2625 /* NIG LB RL init requirements */
2626 struct init_nig_lb_rl_req {
2630 u16 tc_rate[NUM_OF_PHYS_TCS];
2633 /* NIG TC mapping for each priority */
2634 struct init_nig_pri_tc_map_entry {
2639 /* NIG priority to TC map init requirements */
2640 struct init_nig_pri_tc_map_req {
2641 struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
2644 /* QM per global RL init parameters */
2645 struct init_qm_global_rl_params {
2649 /* QM per-port init parameters */
2650 struct init_qm_port_params {
2651 u16 active_phys_tcs;
2652 u16 num_pbf_cmd_lines;
2658 /* QM per-PQ init parameters */
2659 struct init_qm_pq_params {
2669 /* QM per-vport init parameters */
2670 struct init_qm_vport_params {
2672 u16 first_tx_pq_id[NUM_OF_TCS];
2675 /**************************************/
2676 /* Init Tool HSI constants and macros */
2677 /**************************************/
2679 /* Width of GRC address in bits (addresses are specified in dwords) */
2680 #define GRC_ADDR_BITS 23
2681 #define MAX_GRC_ADDR (BIT(GRC_ADDR_BITS) - 1)
2683 /* indicates an init that should be applied to any phase ID */
2684 #define ANY_PHASE_ID 0xffff
2686 /* Max size in dwords of a zipped array */
2687 #define MAX_ZIPPED_SIZE 8192
2694 struct fw_asserts_ram_section {
2695 __le16 section_ram_line_offset;
2696 __le16 section_ram_line_size;
2697 u8 list_dword_offset;
2698 u8 list_element_dword_size;
2699 u8 list_num_elements;
2700 u8 list_next_index_dword_offset;
2710 struct fw_ver_info {
2714 struct fw_ver_num num;
2720 struct fw_ver_info ver;
2721 struct fw_asserts_ram_section fw_asserts_section;
2724 struct fw_info_location {
2741 MODE_PORTS_PER_ENG_1,
2742 MODE_PORTS_PER_ENG_2,
2743 MODE_PORTS_PER_ENG_4,
2759 enum init_split_types {
2765 MAX_INIT_SPLIT_TYPES
2768 /* Binary buffer header */
2769 struct bin_buffer_hdr {
2774 /* Binary init buffer types */
2775 enum bin_init_buffer_type {
2776 BIN_BUF_INIT_FW_VER_INFO,
2779 BIN_BUF_INIT_MODE_TREE,
2781 BIN_BUF_INIT_OVERLAYS,
2782 MAX_BIN_INIT_BUFFER_TYPE
2785 /* FW overlay buffer header */
2786 struct fw_overlay_buf_hdr {
2788 #define FW_OVERLAY_BUF_HDR_STORM_ID_MASK 0xFF
2789 #define FW_OVERLAY_BUF_HDR_STORM_ID_SHIFT 0
2790 #define FW_OVERLAY_BUF_HDR_BUF_SIZE_MASK 0xFFFFFF
2791 #define FW_OVERLAY_BUF_HDR_BUF_SIZE_SHIFT 8
2794 /* init array header: raw */
2795 struct init_array_raw_hdr {
2797 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
2798 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
2799 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
2800 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
2803 /* init array header: standard */
2804 struct init_array_standard_hdr {
2806 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
2807 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
2808 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
2809 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
2812 /* init array header: zipped */
2813 struct init_array_zipped_hdr {
2815 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
2816 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
2817 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
2818 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
2821 /* init array header: pattern */
2822 struct init_array_pattern_hdr {
2824 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
2825 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
2826 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
2827 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
2828 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
2829 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
2832 /* init array header union */
2833 union init_array_hdr {
2834 struct init_array_raw_hdr raw;
2835 struct init_array_standard_hdr standard;
2836 struct init_array_zipped_hdr zipped;
2837 struct init_array_pattern_hdr pattern;
2840 /* init array types */
2841 enum init_array_types {
2845 MAX_INIT_ARRAY_TYPES
2848 /* init operation: callback */
2849 struct init_callback_op {
2851 #define INIT_CALLBACK_OP_OP_MASK 0xF
2852 #define INIT_CALLBACK_OP_OP_SHIFT 0
2853 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
2854 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4
2859 /* init operation: delay */
2860 struct init_delay_op {
2862 #define INIT_DELAY_OP_OP_MASK 0xF
2863 #define INIT_DELAY_OP_OP_SHIFT 0
2864 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
2865 #define INIT_DELAY_OP_RESERVED_SHIFT 4
2869 /* init operation: if_mode */
2870 struct init_if_mode_op {
2872 #define INIT_IF_MODE_OP_OP_MASK 0xF
2873 #define INIT_IF_MODE_OP_OP_SHIFT 0
2874 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
2875 #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
2876 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
2877 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
2879 __le16 modes_buf_offset;
2882 /* init operation: if_phase */
2883 struct init_if_phase_op {
2885 #define INIT_IF_PHASE_OP_OP_MASK 0xF
2886 #define INIT_IF_PHASE_OP_OP_SHIFT 0
2887 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0xFFF
2888 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 4
2889 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
2890 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
2892 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF
2893 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0
2894 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
2895 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
2896 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF
2897 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
2900 /* init mode operators */
2901 enum init_mode_ops {
2908 /* init operation: raw */
2909 struct init_raw_op {
2911 #define INIT_RAW_OP_OP_MASK 0xF
2912 #define INIT_RAW_OP_OP_SHIFT 0
2913 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF
2914 #define INIT_RAW_OP_PARAM1_SHIFT 4
2918 /* init array params */
2919 struct init_op_array_params {
2924 /* Write init operation arguments */
2925 union init_write_args {
2928 __le32 array_offset;
2929 struct init_op_array_params runtime;
2932 /* init operation: write */
2933 struct init_write_op {
2935 #define INIT_WRITE_OP_OP_MASK 0xF
2936 #define INIT_WRITE_OP_OP_SHIFT 0
2937 #define INIT_WRITE_OP_SOURCE_MASK 0x7
2938 #define INIT_WRITE_OP_SOURCE_SHIFT 4
2939 #define INIT_WRITE_OP_RESERVED_MASK 0x1
2940 #define INIT_WRITE_OP_RESERVED_SHIFT 7
2941 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
2942 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
2943 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
2944 #define INIT_WRITE_OP_ADDRESS_SHIFT 9
2945 union init_write_args args;
2948 /* init operation: read */
2949 struct init_read_op {
2951 #define INIT_READ_OP_OP_MASK 0xF
2952 #define INIT_READ_OP_OP_SHIFT 0
2953 #define INIT_READ_OP_POLL_TYPE_MASK 0xF
2954 #define INIT_READ_OP_POLL_TYPE_SHIFT 4
2955 #define INIT_READ_OP_RESERVED_MASK 0x1
2956 #define INIT_READ_OP_RESERVED_SHIFT 8
2957 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
2958 #define INIT_READ_OP_ADDRESS_SHIFT 9
2959 __le32 expected_val;
2962 /* Init operations union */
2964 struct init_raw_op raw;
2965 struct init_write_op write;
2966 struct init_read_op read;
2967 struct init_if_mode_op if_mode;
2968 struct init_if_phase_op if_phase;
2969 struct init_callback_op callback;
2970 struct init_delay_op delay;
2973 /* Init command operation types */
2974 enum init_op_types {
2984 /* init polling types */
2985 enum init_poll_types {
2993 /* init source types */
2994 enum init_source_types {
2999 MAX_INIT_SOURCE_TYPES
3002 /* Internal RAM Offsets macro data */
3011 /***************************** Public Functions *******************************/
3014 * @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug
3017 * @param p_hwfn - HW device data
3018 * @param bin_ptr - a pointer to the binary data with debug arrays.
3020 enum dbg_status qed_dbg_set_bin_ptr(struct qed_hwfn *p_hwfn,
3021 const u8 * const bin_ptr);
3024 * @brief qed_read_regs - Reads registers into a buffer (using GRC).
3026 * @param p_hwfn - HW device data
3027 * @param p_ptt - Ptt window used for writing the registers.
3028 * @param buf - Destination buffer.
3029 * @param addr - Source GRC address in dwords.
3030 * @param len - Number of registers to read.
3032 void qed_read_regs(struct qed_hwfn *p_hwfn,
3033 struct qed_ptt *p_ptt, u32 *buf, u32 addr, u32 len);
3036 * @brief qed_read_fw_info - Reads FW info from the chip.
3038 * The FW info contains FW-related information, such as the FW version,
3039 * FW image (main/L2B/kuku), FW timestamp, etc.
3040 * The FW info is read from the internal RAM of the first Storm that is not in
3043 * @param p_hwfn - HW device data
3044 * @param p_ptt - Ptt window used for writing the registers.
3045 * @param fw_info - Out: a pointer to write the FW info into.
3047 * @return true if the FW info was read successfully from one of the Storms,
3048 * or false if all Storms are in reset.
3050 bool qed_read_fw_info(struct qed_hwfn *p_hwfn,
3051 struct qed_ptt *p_ptt, struct fw_info *fw_info);
3053 * @brief qed_dbg_grc_config - Sets the value of a GRC parameter.
3055 * @param p_hwfn - HW device data
3056 * @param grc_param - GRC parameter
3057 * @param val - Value to set.
3059 * @return error if one of the following holds:
3060 * - the version wasn't set
3061 * - grc_param is invalid
3062 * - val is outside the allowed boundaries
3064 enum dbg_status qed_dbg_grc_config(struct qed_hwfn *p_hwfn,
3065 enum dbg_grc_params grc_param, u32 val);
3068 * @brief qed_dbg_grc_set_params_default - Reverts all GRC parameters to their
3071 * @param p_hwfn - HW device data
3073 void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn);
3075 * @brief qed_dbg_grc_get_dump_buf_size - Returns the required buffer size for
3078 * @param p_hwfn - HW device data
3079 * @param p_ptt - Ptt window used for writing the registers.
3080 * @param buf_size - OUT: required buffer size (in dwords) for the GRC Dump
3083 * @return error if one of the following holds:
3084 * - the version wasn't set
3085 * Otherwise, returns ok.
3087 enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3088 struct qed_ptt *p_ptt,
3092 * @brief qed_dbg_grc_dump - Dumps GRC data into the specified buffer.
3094 * @param p_hwfn - HW device data
3095 * @param p_ptt - Ptt window used for writing the registers.
3096 * @param dump_buf - Pointer to write the collected GRC data into.
3097 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3098 * @param num_dumped_dwords - OUT: number of dumped dwords.
3100 * @return error if one of the following holds:
3101 * - the version wasn't set
3102 * - the specified dump buffer is too small
3103 * Otherwise, returns ok.
3105 enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn,
3106 struct qed_ptt *p_ptt,
3108 u32 buf_size_in_dwords,
3109 u32 *num_dumped_dwords);
3112 * @brief qed_dbg_idle_chk_get_dump_buf_size - Returns the required buffer size
3113 * for idle check results.
3115 * @param p_hwfn - HW device data
3116 * @param p_ptt - Ptt window used for writing the registers.
3117 * @param buf_size - OUT: required buffer size (in dwords) for the idle check
3120 * @return error if one of the following holds:
3121 * - the version wasn't set
3122 * Otherwise, returns ok.
3124 enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3125 struct qed_ptt *p_ptt,
3129 * @brief qed_dbg_idle_chk_dump - Performs idle check and writes the results
3130 * into the specified buffer.
3132 * @param p_hwfn - HW device data
3133 * @param p_ptt - Ptt window used for writing the registers.
3134 * @param dump_buf - Pointer to write the idle check data into.
3135 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3136 * @param num_dumped_dwords - OUT: number of dumped dwords.
3138 * @return error if one of the following holds:
3139 * - the version wasn't set
3140 * - the specified buffer is too small
3141 * Otherwise, returns ok.
3143 enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn,
3144 struct qed_ptt *p_ptt,
3146 u32 buf_size_in_dwords,
3147 u32 *num_dumped_dwords);
3150 * @brief qed_dbg_mcp_trace_get_dump_buf_size - Returns the required buffer size
3151 * for mcp trace results.
3153 * @param p_hwfn - HW device data
3154 * @param p_ptt - Ptt window used for writing the registers.
3155 * @param buf_size - OUT: required buffer size (in dwords) for mcp trace data.
3157 * @return error if one of the following holds:
3158 * - the version wasn't set
3159 * - the trace data in MCP scratchpad contain an invalid signature
3160 * - the bundle ID in NVRAM is invalid
3161 * - the trace meta data cannot be found (in NVRAM or image file)
3162 * Otherwise, returns ok.
3164 enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3165 struct qed_ptt *p_ptt,
3169 * @brief qed_dbg_mcp_trace_dump - Performs mcp trace and writes the results
3170 * into the specified buffer.
3172 * @param p_hwfn - HW device data
3173 * @param p_ptt - Ptt window used for writing the registers.
3174 * @param dump_buf - Pointer to write the mcp trace data into.
3175 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3176 * @param num_dumped_dwords - OUT: number of dumped dwords.
3178 * @return error if one of the following holds:
3179 * - the version wasn't set
3180 * - the specified buffer is too small
3181 * - the trace data in MCP scratchpad contain an invalid signature
3182 * - the bundle ID in NVRAM is invalid
3183 * - the trace meta data cannot be found (in NVRAM or image file)
3184 * - the trace meta data cannot be read (from NVRAM or image file)
3185 * Otherwise, returns ok.
3187 enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn,
3188 struct qed_ptt *p_ptt,
3190 u32 buf_size_in_dwords,
3191 u32 *num_dumped_dwords);
3194 * @brief qed_dbg_reg_fifo_get_dump_buf_size - Returns the required buffer size
3195 * for grc trace fifo results.
3197 * @param p_hwfn - HW device data
3198 * @param p_ptt - Ptt window used for writing the registers.
3199 * @param buf_size - OUT: required buffer size (in dwords) for reg fifo data.
3201 * @return error if one of the following holds:
3202 * - the version wasn't set
3203 * Otherwise, returns ok.
3205 enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3206 struct qed_ptt *p_ptt,
3210 * @brief qed_dbg_reg_fifo_dump - Reads the reg fifo and writes the results into
3211 * the specified buffer.
3213 * @param p_hwfn - HW device data
3214 * @param p_ptt - Ptt window used for writing the registers.
3215 * @param dump_buf - Pointer to write the reg fifo data into.
3216 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3217 * @param num_dumped_dwords - OUT: number of dumped dwords.
3219 * @return error if one of the following holds:
3220 * - the version wasn't set
3221 * - the specified buffer is too small
3222 * - DMAE transaction failed
3223 * Otherwise, returns ok.
3225 enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn,
3226 struct qed_ptt *p_ptt,
3228 u32 buf_size_in_dwords,
3229 u32 *num_dumped_dwords);
3232 * @brief qed_dbg_igu_fifo_get_dump_buf_size - Returns the required buffer size
3233 * for the IGU fifo results.
3235 * @param p_hwfn - HW device data
3236 * @param p_ptt - Ptt window used for writing the registers.
3237 * @param buf_size - OUT: required buffer size (in dwords) for the IGU fifo
3240 * @return error if one of the following holds:
3241 * - the version wasn't set
3242 * Otherwise, returns ok.
3244 enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3245 struct qed_ptt *p_ptt,
3249 * @brief qed_dbg_igu_fifo_dump - Reads the IGU fifo and writes the results into
3250 * the specified buffer.
3252 * @param p_hwfn - HW device data
3253 * @param p_ptt - Ptt window used for writing the registers.
3254 * @param dump_buf - Pointer to write the IGU fifo data into.
3255 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3256 * @param num_dumped_dwords - OUT: number of dumped dwords.
3258 * @return error if one of the following holds:
3259 * - the version wasn't set
3260 * - the specified buffer is too small
3261 * - DMAE transaction failed
3262 * Otherwise, returns ok.
3264 enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn,
3265 struct qed_ptt *p_ptt,
3267 u32 buf_size_in_dwords,
3268 u32 *num_dumped_dwords);
3271 * @brief qed_dbg_protection_override_get_dump_buf_size - Returns the required
3272 * buffer size for protection override window results.
3274 * @param p_hwfn - HW device data
3275 * @param p_ptt - Ptt window used for writing the registers.
3276 * @param buf_size - OUT: required buffer size (in dwords) for protection
3279 * @return error if one of the following holds:
3280 * - the version wasn't set
3281 * Otherwise, returns ok.
3284 qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3285 struct qed_ptt *p_ptt,
3288 * @brief qed_dbg_protection_override_dump - Reads protection override window
3289 * entries and writes the results into the specified buffer.
3291 * @param p_hwfn - HW device data
3292 * @param p_ptt - Ptt window used for writing the registers.
3293 * @param dump_buf - Pointer to write the protection override data into.
3294 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3295 * @param num_dumped_dwords - OUT: number of dumped dwords.
3297 * @return error if one of the following holds:
3298 * - the version wasn't set
3299 * - the specified buffer is too small
3300 * - DMAE transaction failed
3301 * Otherwise, returns ok.
3303 enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn,
3304 struct qed_ptt *p_ptt,
3306 u32 buf_size_in_dwords,
3307 u32 *num_dumped_dwords);
3309 * @brief qed_dbg_fw_asserts_get_dump_buf_size - Returns the required buffer
3310 * size for FW Asserts results.
3312 * @param p_hwfn - HW device data
3313 * @param p_ptt - Ptt window used for writing the registers.
3314 * @param buf_size - OUT: required buffer size (in dwords) for FW Asserts data.
3316 * @return error if one of the following holds:
3317 * - the version wasn't set
3318 * Otherwise, returns ok.
3320 enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3321 struct qed_ptt *p_ptt,
3324 * @brief qed_dbg_fw_asserts_dump - Reads the FW Asserts and writes the results
3325 * into the specified buffer.
3327 * @param p_hwfn - HW device data
3328 * @param p_ptt - Ptt window used for writing the registers.
3329 * @param dump_buf - Pointer to write the FW Asserts data into.
3330 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3331 * @param num_dumped_dwords - OUT: number of dumped dwords.
3333 * @return error if one of the following holds:
3334 * - the version wasn't set
3335 * - the specified buffer is too small
3336 * Otherwise, returns ok.
3338 enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn,
3339 struct qed_ptt *p_ptt,
3341 u32 buf_size_in_dwords,
3342 u32 *num_dumped_dwords);
3345 * @brief qed_dbg_read_attn - Reads the attention registers of the specified
3346 * block and type, and writes the results into the specified buffer.
3348 * @param p_hwfn - HW device data
3349 * @param p_ptt - Ptt window used for writing the registers.
3350 * @param block - Block ID.
3351 * @param attn_type - Attention type.
3352 * @param clear_status - Indicates if the attention status should be cleared.
3353 * @param results - OUT: Pointer to write the read results into
3355 * @return error if one of the following holds:
3356 * - the version wasn't set
3357 * Otherwise, returns ok.
3359 enum dbg_status qed_dbg_read_attn(struct qed_hwfn *p_hwfn,
3360 struct qed_ptt *p_ptt,
3361 enum block_id block,
3362 enum dbg_attn_type attn_type,
3364 struct dbg_attn_block_result *results);
3367 * @brief qed_dbg_print_attn - Prints attention registers values in the
3368 * specified results struct.
3371 * @param results - Pointer to the attention read results
3373 * @return error if one of the following holds:
3374 * - the version wasn't set
3375 * Otherwise, returns ok.
3377 enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn,
3378 struct dbg_attn_block_result *results);
3380 /******************************* Data Types **********************************/
3382 struct mcp_trace_format {
3384 #define MCP_TRACE_FORMAT_MODULE_MASK 0x0000ffff
3385 #define MCP_TRACE_FORMAT_MODULE_OFFSET 0
3386 #define MCP_TRACE_FORMAT_LEVEL_MASK 0x00030000
3387 #define MCP_TRACE_FORMAT_LEVEL_OFFSET 16
3388 #define MCP_TRACE_FORMAT_P1_SIZE_MASK 0x000c0000
3389 #define MCP_TRACE_FORMAT_P1_SIZE_OFFSET 18
3390 #define MCP_TRACE_FORMAT_P2_SIZE_MASK 0x00300000
3391 #define MCP_TRACE_FORMAT_P2_SIZE_OFFSET 20
3392 #define MCP_TRACE_FORMAT_P3_SIZE_MASK 0x00c00000
3393 #define MCP_TRACE_FORMAT_P3_SIZE_OFFSET 22
3394 #define MCP_TRACE_FORMAT_LEN_MASK 0xff000000
3395 #define MCP_TRACE_FORMAT_LEN_OFFSET 24
3400 /* MCP Trace Meta data structure */
3401 struct mcp_trace_meta {
3405 struct mcp_trace_format *formats;
3409 /* Debug Tools user data */
3410 struct dbg_tools_user_data {
3411 struct mcp_trace_meta mcp_trace_meta;
3412 const u32 *mcp_trace_user_meta_buf;
3415 /******************************** Constants **********************************/
3417 #define MAX_NAME_LEN 16
3419 /***************************** Public Functions *******************************/
3422 * @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with
3425 * @param p_hwfn - HW device data
3426 * @param bin_ptr - a pointer to the binary data with debug arrays.
3428 enum dbg_status qed_dbg_user_set_bin_ptr(struct qed_hwfn *p_hwfn,
3429 const u8 * const bin_ptr);
3432 * @brief qed_dbg_alloc_user_data - Allocates user debug data.
3434 * @param p_hwfn - HW device data
3435 * @param user_data_ptr - OUT: a pointer to the allocated memory.
3437 enum dbg_status qed_dbg_alloc_user_data(struct qed_hwfn *p_hwfn,
3438 void **user_data_ptr);
3441 * @brief qed_dbg_get_status_str - Returns a string for the specified status.
3443 * @param status - a debug status code.
3445 * @return a string for the specified status
3447 const char *qed_dbg_get_status_str(enum dbg_status status);
3450 * @brief qed_get_idle_chk_results_buf_size - Returns the required buffer size
3451 * for idle check results (in bytes).
3453 * @param p_hwfn - HW device data
3454 * @param dump_buf - idle check dump buffer.
3455 * @param num_dumped_dwords - number of dwords that were dumped.
3456 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3459 * @return error if the parsing fails, ok otherwise.
3461 enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn,
3463 u32 num_dumped_dwords,
3464 u32 *results_buf_size);
3466 * @brief qed_print_idle_chk_results - Prints idle check results
3468 * @param p_hwfn - HW device data
3469 * @param dump_buf - idle check dump buffer.
3470 * @param num_dumped_dwords - number of dwords that were dumped.
3471 * @param results_buf - buffer for printing the idle check results.
3472 * @param num_errors - OUT: number of errors found in idle check.
3473 * @param num_warnings - OUT: number of warnings found in idle check.
3475 * @return error if the parsing fails, ok otherwise.
3477 enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn,
3479 u32 num_dumped_dwords,
3485 * @brief qed_dbg_mcp_trace_set_meta_data - Sets the MCP Trace meta data.
3487 * Needed in case the MCP Trace dump doesn't contain the meta data (e.g. due to
3490 * @param data - pointer to MCP Trace meta data
3491 * @param size - size of MCP Trace meta data in dwords
3493 void qed_dbg_mcp_trace_set_meta_data(struct qed_hwfn *p_hwfn,
3494 const u32 *meta_buf);
3497 * @brief qed_get_mcp_trace_results_buf_size - Returns the required buffer size
3498 * for MCP Trace results (in bytes).
3500 * @param p_hwfn - HW device data
3501 * @param dump_buf - MCP Trace dump buffer.
3502 * @param num_dumped_dwords - number of dwords that were dumped.
3503 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3506 * @return error if the parsing fails, ok otherwise.
3508 enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn,
3510 u32 num_dumped_dwords,
3511 u32 *results_buf_size);
3514 * @brief qed_print_mcp_trace_results - Prints MCP Trace results
3516 * @param p_hwfn - HW device data
3517 * @param dump_buf - mcp trace dump buffer, starting from the header.
3518 * @param num_dumped_dwords - number of dwords that were dumped.
3519 * @param results_buf - buffer for printing the mcp trace results.
3521 * @return error if the parsing fails, ok otherwise.
3523 enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn,
3525 u32 num_dumped_dwords,
3529 * @brief qed_print_mcp_trace_results_cont - Prints MCP Trace results, and
3530 * keeps the MCP trace meta data allocated, to support continuous MCP Trace
3531 * parsing. After the continuous parsing ends, mcp_trace_free_meta_data should
3532 * be called to free the meta data.
3534 * @param p_hwfn - HW device data
3535 * @param dump_buf - mcp trace dump buffer, starting from the header.
3536 * @param results_buf - buffer for printing the mcp trace results.
3538 * @return error if the parsing fails, ok otherwise.
3540 enum dbg_status qed_print_mcp_trace_results_cont(struct qed_hwfn *p_hwfn,
3545 * @brief print_mcp_trace_line - Prints MCP Trace results for a single line
3547 * @param p_hwfn - HW device data
3548 * @param dump_buf - mcp trace dump buffer, starting from the header.
3549 * @param num_dumped_bytes - number of bytes that were dumped.
3550 * @param results_buf - buffer for printing the mcp trace results.
3552 * @return error if the parsing fails, ok otherwise.
3554 enum dbg_status qed_print_mcp_trace_line(struct qed_hwfn *p_hwfn,
3556 u32 num_dumped_bytes,
3560 * @brief mcp_trace_free_meta_data - Frees the MCP Trace meta data.
3561 * Should be called after continuous MCP Trace parsing.
3563 * @param p_hwfn - HW device data
3565 void qed_mcp_trace_free_meta_data(struct qed_hwfn *p_hwfn);
3568 * @brief qed_get_reg_fifo_results_buf_size - Returns the required buffer size
3569 * for reg_fifo results (in bytes).
3571 * @param p_hwfn - HW device data
3572 * @param dump_buf - reg fifo dump buffer.
3573 * @param num_dumped_dwords - number of dwords that were dumped.
3574 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3577 * @return error if the parsing fails, ok otherwise.
3579 enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3581 u32 num_dumped_dwords,
3582 u32 *results_buf_size);
3585 * @brief qed_print_reg_fifo_results - Prints reg fifo results
3587 * @param p_hwfn - HW device data
3588 * @param dump_buf - reg fifo dump buffer, starting from the header.
3589 * @param num_dumped_dwords - number of dwords that were dumped.
3590 * @param results_buf - buffer for printing the reg fifo results.
3592 * @return error if the parsing fails, ok otherwise.
3594 enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn,
3596 u32 num_dumped_dwords,
3600 * @brief qed_get_igu_fifo_results_buf_size - Returns the required buffer size
3601 * for igu_fifo results (in bytes).
3603 * @param p_hwfn - HW device data
3604 * @param dump_buf - IGU fifo dump buffer.
3605 * @param num_dumped_dwords - number of dwords that were dumped.
3606 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3609 * @return error if the parsing fails, ok otherwise.
3611 enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3613 u32 num_dumped_dwords,
3614 u32 *results_buf_size);
3617 * @brief qed_print_igu_fifo_results - Prints IGU fifo results
3619 * @param p_hwfn - HW device data
3620 * @param dump_buf - IGU fifo dump buffer, starting from the header.
3621 * @param num_dumped_dwords - number of dwords that were dumped.
3622 * @param results_buf - buffer for printing the IGU fifo results.
3624 * @return error if the parsing fails, ok otherwise.
3626 enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn,
3628 u32 num_dumped_dwords,
3632 * @brief qed_get_protection_override_results_buf_size - Returns the required
3633 * buffer size for protection override results (in bytes).
3635 * @param p_hwfn - HW device data
3636 * @param dump_buf - protection override dump buffer.
3637 * @param num_dumped_dwords - number of dwords that were dumped.
3638 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3641 * @return error if the parsing fails, ok otherwise.
3644 qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn,
3646 u32 num_dumped_dwords,
3647 u32 *results_buf_size);
3650 * @brief qed_print_protection_override_results - Prints protection override
3653 * @param p_hwfn - HW device data
3654 * @param dump_buf - protection override dump buffer, starting from the header.
3655 * @param num_dumped_dwords - number of dwords that were dumped.
3656 * @param results_buf - buffer for printing the reg fifo results.
3658 * @return error if the parsing fails, ok otherwise.
3660 enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn,
3662 u32 num_dumped_dwords,
3666 * @brief qed_get_fw_asserts_results_buf_size - Returns the required buffer size
3667 * for FW Asserts results (in bytes).
3669 * @param p_hwfn - HW device data
3670 * @param dump_buf - FW Asserts dump buffer.
3671 * @param num_dumped_dwords - number of dwords that were dumped.
3672 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3675 * @return error if the parsing fails, ok otherwise.
3677 enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn,
3679 u32 num_dumped_dwords,
3680 u32 *results_buf_size);
3683 * @brief qed_print_fw_asserts_results - Prints FW Asserts results
3685 * @param p_hwfn - HW device data
3686 * @param dump_buf - FW Asserts dump buffer, starting from the header.
3687 * @param num_dumped_dwords - number of dwords that were dumped.
3688 * @param results_buf - buffer for printing the FW Asserts results.
3690 * @return error if the parsing fails, ok otherwise.
3692 enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn,
3694 u32 num_dumped_dwords,
3698 * @brief qed_dbg_parse_attn - Parses and prints attention registers values in
3699 * the specified results struct.
3701 * @param p_hwfn - HW device data
3702 * @param results - Pointer to the attention read results
3704 * @return error if one of the following holds:
3705 * - the version wasn't set
3706 * Otherwise, returns ok.
3708 enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn,
3709 struct dbg_attn_block_result *results);
3712 #define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL
3715 #define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL
3718 #define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL
3721 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL
3724 #define GTT_BAR0_MAP_REG_MSDM_RAM_2048 0x013000UL
3727 #define GTT_BAR0_MAP_REG_USDM_RAM 0x014000UL
3730 #define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x015000UL
3733 #define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x016000UL
3736 #define GTT_BAR0_MAP_REG_XSDM_RAM 0x017000UL
3739 #define GTT_BAR0_MAP_REG_XSDM_RAM_1024 0x018000UL
3742 #define GTT_BAR0_MAP_REG_YSDM_RAM 0x019000UL
3745 #define GTT_BAR0_MAP_REG_PSDM_RAM 0x01a000UL
3748 * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
3750 * Returns the required host memory size in 4KB units.
3751 * Must be called before all QM init HSI functions.
3753 * @param num_pf_cids - number of connections used by this PF
3754 * @param num_vf_cids - number of connections used by VFs of this PF
3755 * @param num_tids - number of tasks used by this PF
3756 * @param num_pf_pqs - number of PQs used by this PF
3757 * @param num_vf_pqs - number of PQs used by VFs of this PF
3759 * @return The required host memory size in 4KB units.
3761 u32 qed_qm_pf_mem_size(u32 num_pf_cids,
3763 u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);
3765 struct qed_qm_common_rt_init_params {
3766 u8 max_ports_per_engine;
3767 u8 max_phys_tcs_per_port;
3772 struct init_qm_port_params *port_params;
3775 int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
3776 struct qed_qm_common_rt_init_params *p_params);
3778 struct qed_qm_pf_rt_init_params {
3781 u8 max_phys_tcs_per_port;
3793 struct init_qm_pq_params *pq_params;
3794 struct init_qm_vport_params *vport_params;
3797 int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
3798 struct qed_ptt *p_ptt,
3799 struct qed_qm_pf_rt_init_params *p_params);
3802 * @brief qed_init_pf_wfq - Initializes the WFQ weight of the specified PF
3805 * @param p_ptt - ptt window used for writing the registers
3806 * @param pf_id - PF ID
3807 * @param pf_wfq - WFQ weight. Must be non-zero.
3809 * @return 0 on success, -1 on error.
3811 int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
3812 struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq);
3815 * @brief qed_init_pf_rl - Initializes the rate limit of the specified PF
3818 * @param p_ptt - ptt window used for writing the registers
3819 * @param pf_id - PF ID
3820 * @param pf_rl - rate limit in Mb/sec units
3822 * @return 0 on success, -1 on error.
3824 int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
3825 struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl);
3828 * @brief qed_init_vport_wfq Initializes the WFQ weight of the specified VPORT
3831 * @param p_ptt - ptt window used for writing the registers
3832 * @param first_tx_pq_id- An array containing the first Tx PQ ID associated
3833 * with the VPORT for each TC. This array is filled by
3835 * @param vport_wfq - WFQ weight. Must be non-zero.
3837 * @return 0 on success, -1 on error.
3839 int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
3840 struct qed_ptt *p_ptt,
3841 u16 first_tx_pq_id[NUM_OF_TCS], u16 wfq);
3844 * @brief qed_init_global_rl - Initializes the rate limit of the specified
3848 * @param p_ptt - ptt window used for writing the registers
3849 * @param rl_id - RL ID
3850 * @param rate_limit - rate limit in Mb/sec units
3852 * @return 0 on success, -1 on error.
3854 int qed_init_global_rl(struct qed_hwfn *p_hwfn,
3855 struct qed_ptt *p_ptt,
3856 u16 rl_id, u32 rate_limit);
3859 * @brief qed_send_qm_stop_cmd Sends a stop command to the QM
3863 * @param is_release_cmd - true for release, false for stop.
3864 * @param is_tx_pq - true for Tx PQs, false for Other PQs.
3865 * @param start_pq - first PQ ID to stop
3866 * @param num_pqs - Number of PQs to stop, starting from start_pq.
3868 * @return bool, true if successful, false if timeout occurred while waiting for
3871 bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
3872 struct qed_ptt *p_ptt,
3873 bool is_release_cmd,
3874 bool is_tx_pq, u16 start_pq, u16 num_pqs);
3877 * @brief qed_set_vxlan_dest_port - initializes vxlan tunnel destination udp port
3880 * @param p_ptt - ptt window used for writing the registers.
3881 * @param dest_port - vxlan destination udp port.
3883 void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
3884 struct qed_ptt *p_ptt, u16 dest_port);
3887 * @brief qed_set_vxlan_enable - enable or disable VXLAN tunnel in HW
3890 * @param p_ptt - ptt window used for writing the registers.
3891 * @param vxlan_enable - vxlan enable flag.
3893 void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
3894 struct qed_ptt *p_ptt, bool vxlan_enable);
3897 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
3900 * @param p_ptt - ptt window used for writing the registers.
3901 * @param eth_gre_enable - eth GRE enable enable flag.
3902 * @param ip_gre_enable - IP GRE enable enable flag.
3904 void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
3905 struct qed_ptt *p_ptt,
3906 bool eth_gre_enable, bool ip_gre_enable);
3909 * @brief qed_set_geneve_dest_port - initializes geneve tunnel destination udp port
3912 * @param p_ptt - ptt window used for writing the registers.
3913 * @param dest_port - geneve destination udp port.
3915 void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
3916 struct qed_ptt *p_ptt, u16 dest_port);
3919 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
3921 * @param p_ptt - ptt window used for writing the registers.
3922 * @param eth_geneve_enable - eth GENEVE enable enable flag.
3923 * @param ip_geneve_enable - IP GENEVE enable enable flag.
3925 void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
3926 struct qed_ptt *p_ptt,
3927 bool eth_geneve_enable, bool ip_geneve_enable);
3929 void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn,
3930 struct qed_ptt *p_ptt, bool enable);
3933 * @brief qed_gft_disable - Disable GFT
3936 * @param p_ptt - ptt window used for writing the registers.
3937 * @param pf_id - pf on which to disable GFT.
3939 void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id);
3942 * @brief qed_gft_config - Enable and configure HW for GFT
3944 * @param p_hwfn - HW device data
3945 * @param p_ptt - ptt window used for writing the registers.
3946 * @param pf_id - pf on which to enable GFT.
3947 * @param tcp - set profile tcp packets.
3948 * @param udp - set profile udp packet.
3949 * @param ipv4 - set profile ipv4 packet.
3950 * @param ipv6 - set profile ipv6 packet.
3951 * @param profile_type - define packet same fields. Use enum gft_profile_type.
3953 void qed_gft_config(struct qed_hwfn *p_hwfn,
3954 struct qed_ptt *p_ptt,
3958 bool ipv4, bool ipv6, enum gft_profile_type profile_type);
3961 * @brief qed_enable_context_validation - Enable and configure context
3965 * @param p_ptt - ptt window used for writing the registers.
3967 void qed_enable_context_validation(struct qed_hwfn *p_hwfn,
3968 struct qed_ptt *p_ptt);
3971 * @brief qed_calc_session_ctx_validation - Calcualte validation byte for
3974 * @param p_ctx_mem - pointer to context memory.
3975 * @param ctx_size - context size.
3976 * @param ctx_type - context type.
3977 * @param cid - context cid.
3979 void qed_calc_session_ctx_validation(void *p_ctx_mem,
3980 u16 ctx_size, u8 ctx_type, u32 cid);
3983 * @brief qed_calc_task_ctx_validation - Calcualte validation byte for task
3986 * @param p_ctx_mem - pointer to context memory.
3987 * @param ctx_size - context size.
3988 * @param ctx_type - context type.
3989 * @param tid - context tid.
3991 void qed_calc_task_ctx_validation(void *p_ctx_mem,
3992 u16 ctx_size, u8 ctx_type, u32 tid);
3995 * @brief qed_memset_session_ctx - Memset session context to 0 while
3996 * preserving validation bytes.
3999 * @param p_ctx_mem - pointer to context memory.
4000 * @param ctx_size - size to initialzie.
4001 * @param ctx_type - context type.
4003 void qed_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type);
4006 * @brief qed_memset_task_ctx - Memset task context to 0 while preserving
4009 * @param p_ctx_mem - pointer to context memory.
4010 * @param ctx_size - size to initialzie.
4011 * @param ctx_type - context type.
4013 void qed_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type);
4015 #define NUM_STORMS 6
4018 * @brief qed_set_rdma_error_level - Sets the RDMA assert level.
4019 * If the severity of the error will be
4020 * above the level, the FW will assert.
4021 * @param p_hwfn - HW device data
4022 * @param p_ptt - ptt window used for writing the registers
4023 * @param assert_level - An array of assert levels for each storm.
4026 void qed_set_rdma_error_level(struct qed_hwfn *p_hwfn,
4027 struct qed_ptt *p_ptt,
4028 u8 assert_level[NUM_STORMS]);
4030 * @brief qed_fw_overlay_mem_alloc - Allocates and fills the FW overlay memory.
4032 * @param p_hwfn - HW device data
4033 * @param fw_overlay_in_buf - the input FW overlay buffer.
4034 * @param buf_size - the size of the input FW overlay buffer in bytes.
4035 * must be aligned to dwords.
4036 * @param fw_overlay_out_mem - OUT: a pointer to the allocated overlays memory.
4038 * @return a pointer to the allocated overlays memory,
4039 * or NULL in case of failures.
4041 struct phys_mem_desc *
4042 qed_fw_overlay_mem_alloc(struct qed_hwfn *p_hwfn,
4043 const u32 * const fw_overlay_in_buf,
4044 u32 buf_size_in_bytes);
4047 * @brief qed_fw_overlay_init_ram - Initializes the FW overlay RAM.
4049 * @param p_hwfn - HW device data.
4050 * @param p_ptt - ptt window used for writing the registers.
4051 * @param fw_overlay_mem - the allocated FW overlay memory.
4053 void qed_fw_overlay_init_ram(struct qed_hwfn *p_hwfn,
4054 struct qed_ptt *p_ptt,
4055 struct phys_mem_desc *fw_overlay_mem);
4058 * @brief qed_fw_overlay_mem_free - Frees the FW overlay memory.
4060 * @param p_hwfn - HW device data.
4061 * @param fw_overlay_mem - the allocated FW overlay memory to free.
4063 void qed_fw_overlay_mem_free(struct qed_hwfn *p_hwfn,
4064 struct phys_mem_desc *fw_overlay_mem);
4066 /* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
4067 #define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
4068 #define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
4070 /* Tstorm port statistics */
4071 #define TSTORM_PORT_STAT_OFFSET(port_id) \
4072 (IRO[1].base + ((port_id) * IRO[1].m1))
4073 #define TSTORM_PORT_STAT_SIZE (IRO[1].size)
4075 /* Tstorm ll2 port statistics */
4076 #define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
4077 (IRO[2].base + ((port_id) * IRO[2].m1))
4078 #define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size)
4080 /* Ustorm VF-PF Channel ready flag */
4081 #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
4082 (IRO[3].base + ((vf_id) * IRO[3].m1))
4083 #define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)
4085 /* Ustorm Final flr cleanup ack */
4086 #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \
4087 (IRO[4].base + ((pf_id) * IRO[4].m1))
4088 #define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size)
4090 /* Ustorm Event ring consumer */
4091 #define USTORM_EQE_CONS_OFFSET(pf_id) \
4092 (IRO[5].base + ((pf_id) * IRO[5].m1))
4093 #define USTORM_EQE_CONS_SIZE (IRO[5].size)
4095 /* Ustorm eth queue zone */
4096 #define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \
4097 (IRO[6].base + ((queue_zone_id) * IRO[6].m1))
4098 #define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[6].size)
4100 /* Ustorm Common Queue ring consumer */
4101 #define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \
4102 (IRO[7].base + ((queue_zone_id) * IRO[7].m1))
4103 #define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size)
4105 /* Xstorm common PQ info */
4106 #define XSTORM_PQ_INFO_OFFSET(pq_id) \
4107 (IRO[8].base + ((pq_id) * IRO[8].m1))
4108 #define XSTORM_PQ_INFO_SIZE (IRO[8].size)
4110 /* Xstorm Integration Test Data */
4111 #define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[9].base)
4112 #define XSTORM_INTEG_TEST_DATA_SIZE (IRO[9].size)
4114 /* Ystorm Integration Test Data */
4115 #define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[10].base)
4116 #define YSTORM_INTEG_TEST_DATA_SIZE (IRO[10].size)
4118 /* Pstorm Integration Test Data */
4119 #define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[11].base)
4120 #define PSTORM_INTEG_TEST_DATA_SIZE (IRO[11].size)
4122 /* Tstorm Integration Test Data */
4123 #define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[12].base)
4124 #define TSTORM_INTEG_TEST_DATA_SIZE (IRO[12].size)
4126 /* Mstorm Integration Test Data */
4127 #define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[13].base)
4128 #define MSTORM_INTEG_TEST_DATA_SIZE (IRO[13].size)
4130 /* Ustorm Integration Test Data */
4131 #define USTORM_INTEG_TEST_DATA_OFFSET (IRO[14].base)
4132 #define USTORM_INTEG_TEST_DATA_SIZE (IRO[14].size)
4134 /* Xstorm overlay buffer host address */
4135 #define XSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[15].base)
4136 #define XSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[15].size)
4138 /* Ystorm overlay buffer host address */
4139 #define YSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[16].base)
4140 #define YSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[16].size)
4142 /* Pstorm overlay buffer host address */
4143 #define PSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[17].base)
4144 #define PSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[17].size)
4146 /* Tstorm overlay buffer host address */
4147 #define TSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[18].base)
4148 #define TSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[18].size)
4150 /* Mstorm overlay buffer host address */
4151 #define MSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[19].base)
4152 #define MSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[19].size)
4154 /* Ustorm overlay buffer host address */
4155 #define USTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[20].base)
4156 #define USTORM_OVERLAY_BUF_ADDR_SIZE (IRO[20].size)
4158 /* Tstorm producers */
4159 #define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
4160 (IRO[21].base + ((core_rx_queue_id) * IRO[21].m1))
4161 #define TSTORM_LL2_RX_PRODS_SIZE (IRO[21].size)
4163 /* Tstorm LightL2 queue statistics */
4164 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
4165 (IRO[22].base + ((core_rx_queue_id) * IRO[22].m1))
4166 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[22].size)
4168 /* Ustorm LiteL2 queue statistics */
4169 #define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
4170 (IRO[23].base + ((core_rx_queue_id) * IRO[23].m1))
4171 #define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[23].size)
4173 /* Pstorm LiteL2 queue statistics */
4174 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
4175 (IRO[24].base + ((core_tx_stats_id) * IRO[24].m1))
4176 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[24].size)
4178 /* Mstorm queue statistics */
4179 #define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4180 (IRO[25].base + ((stat_counter_id) * IRO[25].m1))
4181 #define MSTORM_QUEUE_STAT_SIZE (IRO[25].size)
4183 /* TPA agregation timeout in us resolution (on ASIC) */
4184 #define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[26].base)
4185 #define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[26].size)
4187 /* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone size
4190 #define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
4191 (IRO[27].base + ((vf_id) * IRO[27].m1) + ((vf_queue_id) * IRO[27].m2))
4192 #define MSTORM_ETH_VF_PRODS_SIZE (IRO[27].size)
4194 /* Mstorm ETH PF queues producers */
4195 #define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \
4196 (IRO[28].base + ((queue_id) * IRO[28].m1))
4197 #define MSTORM_ETH_PF_PRODS_SIZE (IRO[28].size)
4199 /* Mstorm pf statistics */
4200 #define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
4201 (IRO[29].base + ((pf_id) * IRO[29].m1))
4202 #define MSTORM_ETH_PF_STAT_SIZE (IRO[29].size)
4204 /* Ustorm queue statistics */
4205 #define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4206 (IRO[30].base + ((stat_counter_id) * IRO[30].m1))
4207 #define USTORM_QUEUE_STAT_SIZE (IRO[30].size)
4209 /* Ustorm pf statistics */
4210 #define USTORM_ETH_PF_STAT_OFFSET(pf_id) \
4211 (IRO[31].base + ((pf_id) * IRO[31].m1))
4212 #define USTORM_ETH_PF_STAT_SIZE (IRO[31].size)
4214 /* Pstorm queue statistics */
4215 #define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4216 (IRO[32].base + ((stat_counter_id) * IRO[32].m1))
4217 #define PSTORM_QUEUE_STAT_SIZE (IRO[32].size)
4219 /* Pstorm pf statistics */
4220 #define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
4221 (IRO[33].base + ((pf_id) * IRO[33].m1))
4222 #define PSTORM_ETH_PF_STAT_SIZE (IRO[33].size)
4224 /* Control frame's EthType configuration for TX control frame security */
4225 #define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(eth_type_id) \
4226 (IRO[34].base + ((eth_type_id) * IRO[34].m1))
4227 #define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[34].size)
4229 /* Tstorm last parser message */
4230 #define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[35].base)
4231 #define TSTORM_ETH_PRS_INPUT_SIZE (IRO[35].size)
4233 /* Tstorm Eth limit Rx rate */
4234 #define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
4235 (IRO[36].base + ((pf_id) * IRO[36].m1))
4236 #define ETH_RX_RATE_LIMIT_SIZE (IRO[36].size)
4238 /* RSS indirection table entry update command per PF offset in TSTORM PF BAR0.
4239 * Use eth_tstorm_rss_update_data for update
4241 #define TSTORM_ETH_RSS_UPDATE_OFFSET(pf_id) \
4242 (IRO[37].base + ((pf_id) * IRO[37].m1))
4243 #define TSTORM_ETH_RSS_UPDATE_SIZE (IRO[37].size)
4245 /* Xstorm queue zone */
4246 #define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
4247 (IRO[38].base + ((queue_id) * IRO[38].m1))
4248 #define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[38].size)
4250 /* Ystorm cqe producer */
4251 #define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \
4252 (IRO[39].base + ((rss_id) * IRO[39].m1))
4253 #define YSTORM_TOE_CQ_PROD_SIZE (IRO[39].size)
4255 /* Ustorm cqe producer */
4256 #define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \
4257 (IRO[40].base + ((rss_id) * IRO[40].m1))
4258 #define USTORM_TOE_CQ_PROD_SIZE (IRO[40].size)
4260 /* Ustorm grq producer */
4261 #define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) \
4262 (IRO[41].base + ((pf_id) * IRO[41].m1))
4263 #define USTORM_TOE_GRQ_PROD_SIZE (IRO[41].size)
4265 /* Tstorm cmdq-cons of given command queue-id */
4266 #define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
4267 (IRO[42].base + ((cmdq_queue_id) * IRO[42].m1))
4268 #define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[42].size)
4270 /* Tstorm (reflects M-Storm) bdq-external-producer of given function ID,
4273 #define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(storage_func_id, bdq_id) \
4274 (IRO[43].base + ((storage_func_id) * IRO[43].m1) + \
4275 ((bdq_id) * IRO[43].m2))
4276 #define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[43].size)
4278 /* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */
4279 #define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(storage_func_id, bdq_id) \
4280 (IRO[44].base + ((storage_func_id) * IRO[44].m1) + \
4281 ((bdq_id) * IRO[44].m2))
4282 #define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[44].size)
4284 /* Tstorm iSCSI RX stats */
4285 #define TSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
4286 (IRO[45].base + ((storage_func_id) * IRO[45].m1))
4287 #define TSTORM_ISCSI_RX_STATS_SIZE (IRO[45].size)
4289 /* Mstorm iSCSI RX stats */
4290 #define MSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
4291 (IRO[46].base + ((storage_func_id) * IRO[46].m1))
4292 #define MSTORM_ISCSI_RX_STATS_SIZE (IRO[46].size)
4294 /* Ustorm iSCSI RX stats */
4295 #define USTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
4296 (IRO[47].base + ((storage_func_id) * IRO[47].m1))
4297 #define USTORM_ISCSI_RX_STATS_SIZE (IRO[47].size)
4299 /* Xstorm iSCSI TX stats */
4300 #define XSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
4301 (IRO[48].base + ((storage_func_id) * IRO[48].m1))
4302 #define XSTORM_ISCSI_TX_STATS_SIZE (IRO[48].size)
4304 /* Ystorm iSCSI TX stats */
4305 #define YSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
4306 (IRO[49].base + ((storage_func_id) * IRO[49].m1))
4307 #define YSTORM_ISCSI_TX_STATS_SIZE (IRO[49].size)
4309 /* Pstorm iSCSI TX stats */
4310 #define PSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
4311 (IRO[50].base + ((storage_func_id) * IRO[50].m1))
4312 #define PSTORM_ISCSI_TX_STATS_SIZE (IRO[50].size)
4314 /* Tstorm FCoE RX stats */
4315 #define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
4316 (IRO[51].base + ((pf_id) * IRO[51].m1))
4317 #define TSTORM_FCOE_RX_STATS_SIZE (IRO[51].size)
4319 /* Pstorm FCoE TX stats */
4320 #define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
4321 (IRO[52].base + ((pf_id) * IRO[52].m1))
4322 #define PSTORM_FCOE_TX_STATS_SIZE (IRO[52].size)
4324 /* Pstorm RDMA queue statistics */
4325 #define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
4326 (IRO[53].base + ((rdma_stat_counter_id) * IRO[53].m1))
4327 #define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[53].size)
4329 /* Tstorm RDMA queue statistics */
4330 #define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
4331 (IRO[54].base + ((rdma_stat_counter_id) * IRO[54].m1))
4332 #define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[54].size)
4334 /* Xstorm error level for assert */
4335 #define XSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4336 (IRO[55].base + ((pf_id) * IRO[55].m1))
4337 #define XSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[55].size)
4339 /* Ystorm error level for assert */
4340 #define YSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4341 (IRO[56].base + ((pf_id) * IRO[56].m1))
4342 #define YSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[56].size)
4344 /* Pstorm error level for assert */
4345 #define PSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4346 (IRO[57].base + ((pf_id) * IRO[57].m1))
4347 #define PSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[57].size)
4349 /* Tstorm error level for assert */
4350 #define TSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4351 (IRO[58].base + ((pf_id) * IRO[58].m1))
4352 #define TSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[58].size)
4354 /* Mstorm error level for assert */
4355 #define MSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4356 (IRO[59].base + ((pf_id) * IRO[59].m1))
4357 #define MSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[59].size)
4359 /* Ustorm error level for assert */
4360 #define USTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4361 (IRO[60].base + ((pf_id) * IRO[60].m1))
4362 #define USTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[60].size)
4364 /* Xstorm iWARP rxmit stats */
4365 #define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) \
4366 (IRO[61].base + ((pf_id) * IRO[61].m1))
4367 #define XSTORM_IWARP_RXMIT_STATS_SIZE (IRO[61].size)
4369 /* Tstorm RoCE Event Statistics */
4370 #define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) \
4371 (IRO[62].base + ((roce_pf_id) * IRO[62].m1))
4372 #define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[62].size)
4374 /* DCQCN Received Statistics */
4375 #define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id)\
4376 (IRO[63].base + ((roce_pf_id) * IRO[63].m1))
4377 #define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE (IRO[63].size)
4379 /* RoCE Error Statistics */
4380 #define YSTORM_ROCE_ERROR_STATS_OFFSET(roce_pf_id) \
4381 (IRO[64].base + ((roce_pf_id) * IRO[64].m1))
4382 #define YSTORM_ROCE_ERROR_STATS_SIZE (IRO[64].size)
4384 /* DCQCN Sent Statistics */
4385 #define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) \
4386 (IRO[65].base + ((roce_pf_id) * IRO[65].m1))
4387 #define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE (IRO[65].size)
4389 /* RoCE CQEs Statistics */
4390 #define USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id) \
4391 (IRO[66].base + ((roce_pf_id) * IRO[66].m1))
4392 #define USTORM_ROCE_CQE_STATS_SIZE (IRO[66].size)
4394 /* Runtime array offsets */
4395 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
4396 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
4397 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
4398 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
4399 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
4400 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
4401 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
4402 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
4403 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
4404 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
4405 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
4406 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
4407 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
4408 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
4409 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
4410 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
4411 #define DORQ_REG_VF_ICID_BIT_SHIFT_NORM_RT_OFFSET 16
4412 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 17
4413 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 18
4414 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET 19
4415 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET 20
4416 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 21
4417 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 22
4418 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 23
4419 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 24
4420 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 25
4421 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 26
4422 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
4423 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 762
4424 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
4425 #define CAU_REG_PI_MEMORY_RT_OFFSET 1498
4426 #define CAU_REG_PI_MEMORY_RT_SIZE 4416
4427 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 5914
4428 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 5915
4429 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 5916
4430 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 5917
4431 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 5918
4432 #define PRS_REG_SEARCH_TCP_RT_OFFSET 5919
4433 #define PRS_REG_SEARCH_FCOE_RT_OFFSET 5920
4434 #define PRS_REG_SEARCH_ROCE_RT_OFFSET 5921
4435 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 5922
4436 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 5923
4437 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 5924
4438 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 5925
4439 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 5926
4440 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 5927
4441 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 5928
4442 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 5929
4443 #define SRC_REG_FIRSTFREE_RT_OFFSET 5930
4444 #define SRC_REG_FIRSTFREE_RT_SIZE 2
4445 #define SRC_REG_LASTFREE_RT_OFFSET 5932
4446 #define SRC_REG_LASTFREE_RT_SIZE 2
4447 #define SRC_REG_COUNTFREE_RT_OFFSET 5934
4448 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 5935
4449 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 5936
4450 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 5937
4451 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 5938
4452 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 5939
4453 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 5940
4454 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 5941
4455 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 5942
4456 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 5943
4457 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 5944
4458 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 5945
4459 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 5946
4460 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 5947
4461 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 5948
4462 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 5949
4463 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 5950
4464 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 5951
4465 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 5952
4466 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 5953
4467 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5954
4468 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5955
4469 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5956
4470 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 5957
4471 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 5958
4472 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 5959
4473 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 5960
4474 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 5961
4475 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 5962
4476 #define PSWRQ2_REG_VF_BASE_RT_OFFSET 5963
4477 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 5964
4478 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 5965
4479 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 5966
4480 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 5967
4481 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
4482 #define PGLUE_REG_B_VF_BASE_RT_OFFSET 27967
4483 #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 27968
4484 #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 27969
4485 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 27970
4486 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 27971
4487 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 27972
4488 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 27973
4489 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET 27974
4490 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET 27975
4491 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET 27976
4492 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 27977
4493 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 27978
4494 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 27979
4495 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
4496 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 28395
4497 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512
4498 #define QM_REG_MAXPQSIZE_0_RT_OFFSET 28907
4499 #define QM_REG_MAXPQSIZE_1_RT_OFFSET 28908
4500 #define QM_REG_MAXPQSIZE_2_RT_OFFSET 28909
4501 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 28910
4502 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 28911
4503 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 28912
4504 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 28913
4505 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 28914
4506 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 28915
4507 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 28916
4508 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 28917
4509 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 28918
4510 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 28919
4511 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 28920
4512 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 28921
4513 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 28922
4514 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 28923
4515 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 28924
4516 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 28925
4517 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 28926
4518 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 28927
4519 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 28928
4520 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 28929
4521 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 28930
4522 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 28931
4523 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 28932
4524 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 28933
4525 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 28934
4526 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 28935
4527 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 28936
4528 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 28937
4529 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 28938
4530 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 28939
4531 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 28940
4532 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 28941
4533 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 28942
4534 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 28943
4535 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 28944
4536 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 28945
4537 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 28946
4538 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 28947
4539 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 28948
4540 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 28949
4541 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 28950
4542 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 28951
4543 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 28952
4544 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 28953
4545 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 28954
4546 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 28955
4547 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 28956
4548 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 28957
4549 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 28958
4550 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 28959
4551 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 28960
4552 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 28961
4553 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 28962
4554 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 28963
4555 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 28964
4556 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 28965
4557 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 28966
4558 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 28967
4559 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 28968
4560 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 28969
4561 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 28970
4562 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 28971
4563 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 28972
4564 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 28973
4565 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 28974
4566 #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
4567 #define QM_REG_PTRTBLOTHER_RT_OFFSET 29102
4568 #define QM_REG_PTRTBLOTHER_RT_SIZE 256
4569 #define QM_REG_VOQCRDLINE_RT_OFFSET 29358
4570 #define QM_REG_VOQCRDLINE_RT_SIZE 20
4571 #define QM_REG_VOQINITCRDLINE_RT_OFFSET 29378
4572 #define QM_REG_VOQINITCRDLINE_RT_SIZE 20
4573 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29398
4574 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29399
4575 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29400
4576 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29401
4577 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29402
4578 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29403
4579 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29404
4580 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29405
4581 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29406
4582 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29407
4583 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29408
4584 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29409
4585 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29410
4586 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29411
4587 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29412
4588 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29413
4589 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29414
4590 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29415
4591 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29416
4592 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29417
4593 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29418
4594 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29419
4595 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29420
4596 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29421
4597 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29422
4598 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29423
4599 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29424
4600 #define QM_REG_PQTX2PF_0_RT_OFFSET 29425
4601 #define QM_REG_PQTX2PF_1_RT_OFFSET 29426
4602 #define QM_REG_PQTX2PF_2_RT_OFFSET 29427
4603 #define QM_REG_PQTX2PF_3_RT_OFFSET 29428
4604 #define QM_REG_PQTX2PF_4_RT_OFFSET 29429
4605 #define QM_REG_PQTX2PF_5_RT_OFFSET 29430
4606 #define QM_REG_PQTX2PF_6_RT_OFFSET 29431
4607 #define QM_REG_PQTX2PF_7_RT_OFFSET 29432
4608 #define QM_REG_PQTX2PF_8_RT_OFFSET 29433
4609 #define QM_REG_PQTX2PF_9_RT_OFFSET 29434
4610 #define QM_REG_PQTX2PF_10_RT_OFFSET 29435
4611 #define QM_REG_PQTX2PF_11_RT_OFFSET 29436
4612 #define QM_REG_PQTX2PF_12_RT_OFFSET 29437
4613 #define QM_REG_PQTX2PF_13_RT_OFFSET 29438
4614 #define QM_REG_PQTX2PF_14_RT_OFFSET 29439
4615 #define QM_REG_PQTX2PF_15_RT_OFFSET 29440
4616 #define QM_REG_PQTX2PF_16_RT_OFFSET 29441
4617 #define QM_REG_PQTX2PF_17_RT_OFFSET 29442
4618 #define QM_REG_PQTX2PF_18_RT_OFFSET 29443
4619 #define QM_REG_PQTX2PF_19_RT_OFFSET 29444
4620 #define QM_REG_PQTX2PF_20_RT_OFFSET 29445
4621 #define QM_REG_PQTX2PF_21_RT_OFFSET 29446
4622 #define QM_REG_PQTX2PF_22_RT_OFFSET 29447
4623 #define QM_REG_PQTX2PF_23_RT_OFFSET 29448
4624 #define QM_REG_PQTX2PF_24_RT_OFFSET 29449
4625 #define QM_REG_PQTX2PF_25_RT_OFFSET 29450
4626 #define QM_REG_PQTX2PF_26_RT_OFFSET 29451
4627 #define QM_REG_PQTX2PF_27_RT_OFFSET 29452
4628 #define QM_REG_PQTX2PF_28_RT_OFFSET 29453
4629 #define QM_REG_PQTX2PF_29_RT_OFFSET 29454
4630 #define QM_REG_PQTX2PF_30_RT_OFFSET 29455
4631 #define QM_REG_PQTX2PF_31_RT_OFFSET 29456
4632 #define QM_REG_PQTX2PF_32_RT_OFFSET 29457
4633 #define QM_REG_PQTX2PF_33_RT_OFFSET 29458
4634 #define QM_REG_PQTX2PF_34_RT_OFFSET 29459
4635 #define QM_REG_PQTX2PF_35_RT_OFFSET 29460
4636 #define QM_REG_PQTX2PF_36_RT_OFFSET 29461
4637 #define QM_REG_PQTX2PF_37_RT_OFFSET 29462
4638 #define QM_REG_PQTX2PF_38_RT_OFFSET 29463
4639 #define QM_REG_PQTX2PF_39_RT_OFFSET 29464
4640 #define QM_REG_PQTX2PF_40_RT_OFFSET 29465
4641 #define QM_REG_PQTX2PF_41_RT_OFFSET 29466
4642 #define QM_REG_PQTX2PF_42_RT_OFFSET 29467
4643 #define QM_REG_PQTX2PF_43_RT_OFFSET 29468
4644 #define QM_REG_PQTX2PF_44_RT_OFFSET 29469
4645 #define QM_REG_PQTX2PF_45_RT_OFFSET 29470
4646 #define QM_REG_PQTX2PF_46_RT_OFFSET 29471
4647 #define QM_REG_PQTX2PF_47_RT_OFFSET 29472
4648 #define QM_REG_PQTX2PF_48_RT_OFFSET 29473
4649 #define QM_REG_PQTX2PF_49_RT_OFFSET 29474
4650 #define QM_REG_PQTX2PF_50_RT_OFFSET 29475
4651 #define QM_REG_PQTX2PF_51_RT_OFFSET 29476
4652 #define QM_REG_PQTX2PF_52_RT_OFFSET 29477
4653 #define QM_REG_PQTX2PF_53_RT_OFFSET 29478
4654 #define QM_REG_PQTX2PF_54_RT_OFFSET 29479
4655 #define QM_REG_PQTX2PF_55_RT_OFFSET 29480
4656 #define QM_REG_PQTX2PF_56_RT_OFFSET 29481
4657 #define QM_REG_PQTX2PF_57_RT_OFFSET 29482
4658 #define QM_REG_PQTX2PF_58_RT_OFFSET 29483
4659 #define QM_REG_PQTX2PF_59_RT_OFFSET 29484
4660 #define QM_REG_PQTX2PF_60_RT_OFFSET 29485
4661 #define QM_REG_PQTX2PF_61_RT_OFFSET 29486
4662 #define QM_REG_PQTX2PF_62_RT_OFFSET 29487
4663 #define QM_REG_PQTX2PF_63_RT_OFFSET 29488
4664 #define QM_REG_PQOTHER2PF_0_RT_OFFSET 29489
4665 #define QM_REG_PQOTHER2PF_1_RT_OFFSET 29490
4666 #define QM_REG_PQOTHER2PF_2_RT_OFFSET 29491
4667 #define QM_REG_PQOTHER2PF_3_RT_OFFSET 29492
4668 #define QM_REG_PQOTHER2PF_4_RT_OFFSET 29493
4669 #define QM_REG_PQOTHER2PF_5_RT_OFFSET 29494
4670 #define QM_REG_PQOTHER2PF_6_RT_OFFSET 29495
4671 #define QM_REG_PQOTHER2PF_7_RT_OFFSET 29496
4672 #define QM_REG_PQOTHER2PF_8_RT_OFFSET 29497
4673 #define QM_REG_PQOTHER2PF_9_RT_OFFSET 29498
4674 #define QM_REG_PQOTHER2PF_10_RT_OFFSET 29499
4675 #define QM_REG_PQOTHER2PF_11_RT_OFFSET 29500
4676 #define QM_REG_PQOTHER2PF_12_RT_OFFSET 29501
4677 #define QM_REG_PQOTHER2PF_13_RT_OFFSET 29502
4678 #define QM_REG_PQOTHER2PF_14_RT_OFFSET 29503
4679 #define QM_REG_PQOTHER2PF_15_RT_OFFSET 29504
4680 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29505
4681 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29506
4682 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29507
4683 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29508
4684 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29509
4685 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29510
4686 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29511
4687 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29512
4688 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29513
4689 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29514
4690 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29515
4691 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29516
4692 #define QM_REG_RLGLBLINCVAL_RT_OFFSET 29517
4693 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256
4694 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 29773
4695 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
4696 #define QM_REG_RLGLBLCRD_RT_OFFSET 30029
4697 #define QM_REG_RLGLBLCRD_RT_SIZE 256
4698 #define QM_REG_RLGLBLENABLE_RT_OFFSET 30285
4699 #define QM_REG_RLPFPERIOD_RT_OFFSET 30286
4700 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30287
4701 #define QM_REG_RLPFINCVAL_RT_OFFSET 30288
4702 #define QM_REG_RLPFINCVAL_RT_SIZE 16
4703 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30304
4704 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
4705 #define QM_REG_RLPFCRD_RT_OFFSET 30320
4706 #define QM_REG_RLPFCRD_RT_SIZE 16
4707 #define QM_REG_RLPFENABLE_RT_OFFSET 30336
4708 #define QM_REG_RLPFVOQENABLE_RT_OFFSET 30337
4709 #define QM_REG_WFQPFWEIGHT_RT_OFFSET 30338
4710 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16
4711 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30354
4712 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
4713 #define QM_REG_WFQPFCRD_RT_OFFSET 30370
4714 #define QM_REG_WFQPFCRD_RT_SIZE 160
4715 #define QM_REG_WFQPFENABLE_RT_OFFSET 30530
4716 #define QM_REG_WFQVPENABLE_RT_OFFSET 30531
4717 #define QM_REG_BASEADDRTXPQ_RT_OFFSET 30532
4718 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512
4719 #define QM_REG_TXPQMAP_RT_OFFSET 31044
4720 #define QM_REG_TXPQMAP_RT_SIZE 512
4721 #define QM_REG_WFQVPWEIGHT_RT_OFFSET 31556
4722 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512
4723 #define QM_REG_WFQVPCRD_RT_OFFSET 32068
4724 #define QM_REG_WFQVPCRD_RT_SIZE 512
4725 #define QM_REG_WFQVPMAP_RT_OFFSET 32580
4726 #define QM_REG_WFQVPMAP_RT_SIZE 512
4727 #define QM_REG_PTRTBLTX_RT_OFFSET 33092
4728 #define QM_REG_PTRTBLTX_RT_SIZE 1024
4729 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 34116
4730 #define QM_REG_WFQPFCRD_MSB_RT_SIZE 160
4731 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 34276
4732 #define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 34277
4733 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 34278
4734 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 34279
4735 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 34280
4736 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 34281
4737 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 34282
4738 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 34283
4739 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
4740 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 34287
4741 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
4742 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 34291
4743 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
4744 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 34323
4745 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
4746 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 34339
4747 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
4748 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 34355
4749 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
4750 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 34371
4751 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
4752 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 34387
4753 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 34388
4754 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE 8
4755 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 34396
4756 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 34397
4757 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 34398
4758 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 34399
4759 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 34400
4760 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 34401
4761 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 34402
4762 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 34403
4763 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 34404
4764 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 34405
4765 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 34406
4766 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 34407
4767 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 34408
4768 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 34409
4769 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 34410
4770 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 34411
4771 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 34412
4772 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 34413
4773 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 34414
4774 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 34415
4775 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 34416
4776 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 34417
4777 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 34418
4778 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 34419
4779 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 34420
4780 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 34421
4781 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 34422
4782 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 34423
4783 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 34424
4784 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 34425
4785 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 34426
4786 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 34427
4787 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 34428
4788 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 34429
4789 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 34430
4790 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 34431
4791 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 34432
4792 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 34433
4793 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 34434
4794 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 34435
4795 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 34436
4796 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 34437
4797 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 34438
4798 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 34439
4799 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 34440
4800 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 34441
4801 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 34442
4802 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 34443
4803 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 34444
4804 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 34445
4805 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 34446
4806 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 34447
4807 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 34448
4808 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 34449
4809 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 34450
4810 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 34451
4811 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 34452
4812 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 34453
4813 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 34454
4814 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 34455
4815 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 34456
4816 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 34457
4817 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 34458
4818 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 34459
4819 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 34460
4820 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 34461
4821 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 34462
4822 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 34463
4823 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 34464
4824 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 34465
4825 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 34466
4826 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 34467
4827 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 34468
4828 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 34469
4829 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 34470
4830 #define XCM_REG_CON_PHY_Q3_RT_OFFSET 34471
4832 #define RUNTIME_ARRAY_SIZE 34472
4834 /* Init Callbacks */
4835 #define DMAE_READY_CB 0
4837 /* The eth storm context for the Tstorm */
4838 struct tstorm_eth_conn_st_ctx {
4842 /* The eth storm context for the Pstorm */
4843 struct pstorm_eth_conn_st_ctx {
4847 /* The eth storm context for the Xstorm */
4848 struct xstorm_eth_conn_st_ctx {
4849 __le32 reserved[60];
4852 struct e4_xstorm_eth_conn_ag_ctx {
4856 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
4857 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
4858 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
4859 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
4860 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
4861 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
4862 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
4863 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
4864 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
4865 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
4866 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
4867 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
4868 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
4869 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
4870 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
4871 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
4873 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
4874 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
4875 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
4876 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
4877 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
4878 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
4879 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
4880 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
4881 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
4882 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_SHIFT 4
4883 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
4884 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_SHIFT 5
4885 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
4886 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
4887 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
4888 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
4890 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
4891 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
4892 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
4893 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
4894 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4895 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
4896 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
4897 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
4899 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
4900 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
4901 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
4902 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
4903 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
4904 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
4905 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
4906 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
4908 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
4909 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
4910 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
4911 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
4912 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
4913 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
4914 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
4915 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
4917 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
4918 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
4919 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
4920 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
4921 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
4922 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
4923 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
4924 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
4926 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
4927 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
4928 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
4929 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
4930 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
4931 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
4932 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
4933 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
4935 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
4936 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
4937 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
4938 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
4939 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
4940 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
4941 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
4942 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
4943 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
4944 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
4946 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4947 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
4948 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
4949 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
4950 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
4951 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
4952 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
4953 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
4954 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
4955 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
4956 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
4957 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
4958 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
4959 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
4960 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
4961 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
4963 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
4964 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
4965 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
4966 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
4967 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
4968 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
4969 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
4970 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
4971 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
4972 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
4973 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
4974 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
4975 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
4976 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
4977 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
4978 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
4980 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
4981 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
4982 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
4983 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
4984 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
4985 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
4986 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
4987 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
4988 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
4989 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
4990 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
4991 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
4992 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
4993 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
4994 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
4995 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
4997 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
4998 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
4999 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
5000 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
5001 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
5002 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
5003 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
5004 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
5005 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
5006 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
5007 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
5008 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
5009 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
5010 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
5011 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
5012 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
5014 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
5015 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
5016 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
5017 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
5018 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
5019 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
5020 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
5021 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
5022 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
5023 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
5024 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
5025 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
5026 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
5027 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
5028 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
5029 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
5031 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
5032 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
5033 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
5034 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
5035 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
5036 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
5037 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
5038 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
5039 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
5040 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
5041 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
5042 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
5043 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
5044 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
5045 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
5046 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
5048 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
5049 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
5050 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
5051 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
5052 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
5053 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
5054 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
5055 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
5056 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
5057 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
5058 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
5059 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
5060 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
5061 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
5064 __le16 e5_reserved1;
5065 __le16 edpm_num_bds;
5068 __le16 updated_qm_pq_id;
5115 /* The eth storm context for the Ystorm */
5116 struct ystorm_eth_conn_st_ctx {
5120 struct e4_ystorm_eth_conn_ag_ctx {
5124 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
5125 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
5126 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
5127 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
5128 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
5129 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
5130 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3
5131 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
5132 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
5133 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
5135 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
5136 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
5137 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
5138 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
5139 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
5140 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
5141 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
5142 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
5143 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
5144 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
5145 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
5146 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
5147 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
5148 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
5149 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
5150 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
5151 u8 tx_q0_int_coallecing_timeset;
5154 __le32 terminate_spqe;
5156 __le16 tx_bd_cons_upd;
5164 struct e4_tstorm_eth_conn_ag_ctx {
5168 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
5169 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
5170 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
5171 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
5172 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1
5173 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
5174 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1
5175 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
5176 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1
5177 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
5178 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1
5179 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
5180 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
5181 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
5183 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
5184 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
5185 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
5186 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
5187 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
5188 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
5189 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
5190 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
5192 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
5193 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
5194 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
5195 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
5196 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
5197 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
5198 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
5199 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
5201 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
5202 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
5203 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
5204 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
5205 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
5206 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
5207 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
5208 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
5209 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
5210 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
5211 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
5212 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
5214 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
5215 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
5216 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
5217 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
5218 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
5219 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
5220 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
5221 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
5222 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
5223 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
5224 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
5225 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
5226 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
5227 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
5228 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
5229 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
5231 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
5232 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
5233 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
5234 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
5235 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
5236 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
5237 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
5238 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
5239 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
5240 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
5241 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1
5242 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
5243 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
5244 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
5245 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
5246 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
5268 struct e4_ustorm_eth_conn_ag_ctx {
5272 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
5273 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
5274 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
5275 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
5276 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
5277 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
5278 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
5279 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
5280 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
5281 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
5283 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
5284 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
5285 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
5286 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
5287 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
5288 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
5289 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
5290 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
5292 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
5293 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
5294 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
5295 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
5296 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
5297 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
5298 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
5299 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
5300 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
5301 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
5302 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
5303 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
5304 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
5305 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
5306 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
5307 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
5309 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
5310 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
5311 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
5312 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
5313 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
5314 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
5315 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
5316 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
5317 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
5318 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
5319 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
5320 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
5321 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
5322 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
5323 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
5324 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
5332 __le32 tx_int_coallecing_timeset;
5333 __le16 tx_drv_bd_cons;
5334 __le16 rx_drv_cqe_cons;
5337 /* The eth storm context for the Ustorm */
5338 struct ustorm_eth_conn_st_ctx {
5339 __le32 reserved[40];
5342 /* The eth storm context for the Mstorm */
5343 struct mstorm_eth_conn_st_ctx {
5347 /* eth connection context */
5348 struct e4_eth_conn_context {
5349 struct tstorm_eth_conn_st_ctx tstorm_st_context;
5350 struct regpair tstorm_st_padding[2];
5351 struct pstorm_eth_conn_st_ctx pstorm_st_context;
5352 struct xstorm_eth_conn_st_ctx xstorm_st_context;
5353 struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context;
5354 struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context;
5355 struct ystorm_eth_conn_st_ctx ystorm_st_context;
5356 struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context;
5357 struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context;
5358 struct ustorm_eth_conn_st_ctx ustorm_st_context;
5359 struct mstorm_eth_conn_st_ctx mstorm_st_context;
5362 /* Ethernet filter types: mac/vlan/pair */
5363 enum eth_error_code {
5365 ETH_FILTERS_MAC_ADD_FAIL_FULL,
5366 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2,
5367 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2,
5368 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2,
5369 ETH_FILTERS_MAC_DEL_FAIL_NOF,
5370 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2,
5371 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2,
5372 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC,
5373 ETH_FILTERS_VLAN_ADD_FAIL_FULL,
5374 ETH_FILTERS_VLAN_ADD_FAIL_DUP,
5375 ETH_FILTERS_VLAN_DEL_FAIL_NOF,
5376 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1,
5377 ETH_FILTERS_PAIR_ADD_FAIL_DUP,
5378 ETH_FILTERS_PAIR_ADD_FAIL_FULL,
5379 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC,
5380 ETH_FILTERS_PAIR_DEL_FAIL_NOF,
5381 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1,
5382 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC,
5383 ETH_FILTERS_VNI_ADD_FAIL_FULL,
5384 ETH_FILTERS_VNI_ADD_FAIL_DUP,
5385 ETH_FILTERS_GFT_UPDATE_FAIL,
5386 ETH_RX_QUEUE_FAIL_LOAD_VF_DATA,
5387 ETH_FILTERS_GFS_ADD_FILTER_FAIL_MAX_HOPS,
5388 ETH_FILTERS_GFS_ADD_FILTER_FAIL_NO_FREE_ENRTY,
5389 ETH_FILTERS_GFS_ADD_FILTER_FAIL_ALREADY_EXISTS,
5390 ETH_FILTERS_GFS_ADD_FILTER_FAIL_PCI_ERROR,
5391 ETH_FILTERS_GFS_ADD_FINLER_FAIL_MAGIC_NUM_ERROR,
5392 ETH_FILTERS_GFS_DEL_FILTER_FAIL_MAX_HOPS,
5393 ETH_FILTERS_GFS_DEL_FILTER_FAIL_NO_MATCH_ENRTY,
5394 ETH_FILTERS_GFS_DEL_FILTER_FAIL_PCI_ERROR,
5395 ETH_FILTERS_GFS_DEL_FILTER_FAIL_MAGIC_NUM_ERROR,
5399 /* Opcodes for the event ring */
5400 enum eth_event_opcode {
5402 ETH_EVENT_VPORT_START,
5403 ETH_EVENT_VPORT_UPDATE,
5404 ETH_EVENT_VPORT_STOP,
5405 ETH_EVENT_TX_QUEUE_START,
5406 ETH_EVENT_TX_QUEUE_STOP,
5407 ETH_EVENT_RX_QUEUE_START,
5408 ETH_EVENT_RX_QUEUE_UPDATE,
5409 ETH_EVENT_RX_QUEUE_STOP,
5410 ETH_EVENT_FILTERS_UPDATE,
5411 ETH_EVENT_RX_ADD_OPENFLOW_FILTER,
5412 ETH_EVENT_RX_DELETE_OPENFLOW_FILTER,
5413 ETH_EVENT_RX_CREATE_OPENFLOW_ACTION,
5414 ETH_EVENT_RX_ADD_UDP_FILTER,
5415 ETH_EVENT_RX_DELETE_UDP_FILTER,
5416 ETH_EVENT_RX_CREATE_GFT_ACTION,
5417 ETH_EVENT_RX_GFT_UPDATE_FILTER,
5418 ETH_EVENT_TX_QUEUE_UPDATE,
5419 ETH_EVENT_RGFS_ADD_FILTER,
5420 ETH_EVENT_RGFS_DEL_FILTER,
5421 ETH_EVENT_TGFS_ADD_FILTER,
5422 ETH_EVENT_TGFS_DEL_FILTER,
5423 ETH_EVENT_GFS_COUNTERS_REPORT_REQUEST,
5424 MAX_ETH_EVENT_OPCODE
5427 /* Classify rule types in E2/E3 */
5428 enum eth_filter_action {
5429 ETH_FILTER_ACTION_UNUSED,
5430 ETH_FILTER_ACTION_REMOVE,
5431 ETH_FILTER_ACTION_ADD,
5432 ETH_FILTER_ACTION_REMOVE_ALL,
5433 MAX_ETH_FILTER_ACTION
5436 /* Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ */
5437 struct eth_filter_cmd {
5449 /* $$KEEP_ENDIANNESS$$ */
5450 struct eth_filter_cmd_header {
5458 /* Ethernet filter types: mac/vlan/pair */
5459 enum eth_filter_type {
5460 ETH_FILTER_TYPE_UNUSED,
5461 ETH_FILTER_TYPE_MAC,
5462 ETH_FILTER_TYPE_VLAN,
5463 ETH_FILTER_TYPE_PAIR,
5464 ETH_FILTER_TYPE_INNER_MAC,
5465 ETH_FILTER_TYPE_INNER_VLAN,
5466 ETH_FILTER_TYPE_INNER_PAIR,
5467 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
5468 ETH_FILTER_TYPE_MAC_VNI_PAIR,
5469 ETH_FILTER_TYPE_VNI,
5473 /* inner to inner vlan priority translation configurations */
5474 struct eth_in_to_in_pri_map_cfg {
5475 u8 inner_vlan_pri_remap_en;
5477 u8 non_rdma_in_to_in_pri_map[8];
5478 u8 rdma_in_to_in_pri_map[8];
5481 /* Eth IPv4 Fragment Type */
5482 enum eth_ipv4_frag_type {
5484 ETH_IPV4_FIRST_FRAG,
5485 ETH_IPV4_NON_FIRST_FRAG,
5486 MAX_ETH_IPV4_FRAG_TYPE
5489 /* eth IPv4 Fragment Type */
5496 /* Ethernet Ramrod Command IDs */
5497 enum eth_ramrod_cmd_id {
5499 ETH_RAMROD_VPORT_START,
5500 ETH_RAMROD_VPORT_UPDATE,
5501 ETH_RAMROD_VPORT_STOP,
5502 ETH_RAMROD_RX_QUEUE_START,
5503 ETH_RAMROD_RX_QUEUE_STOP,
5504 ETH_RAMROD_TX_QUEUE_START,
5505 ETH_RAMROD_TX_QUEUE_STOP,
5506 ETH_RAMROD_FILTERS_UPDATE,
5507 ETH_RAMROD_RX_QUEUE_UPDATE,
5508 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
5509 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
5510 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
5511 ETH_RAMROD_RX_ADD_UDP_FILTER,
5512 ETH_RAMROD_RX_DELETE_UDP_FILTER,
5513 ETH_RAMROD_RX_CREATE_GFT_ACTION,
5514 ETH_RAMROD_GFT_UPDATE_FILTER,
5515 ETH_RAMROD_TX_QUEUE_UPDATE,
5516 ETH_RAMROD_RGFS_FILTER_ADD,
5517 ETH_RAMROD_RGFS_FILTER_DEL,
5518 ETH_RAMROD_TGFS_FILTER_ADD,
5519 ETH_RAMROD_TGFS_FILTER_DEL,
5520 ETH_RAMROD_GFS_COUNTERS_REPORT_REQUEST,
5521 MAX_ETH_RAMROD_CMD_ID
5524 /* Return code from eth sp ramrods */
5525 struct eth_return_code {
5527 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x3F
5528 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
5529 #define ETH_RETURN_CODE_RESERVED_MASK 0x1
5530 #define ETH_RETURN_CODE_RESERVED_SHIFT 6
5531 #define ETH_RETURN_CODE_RX_TX_MASK 0x1
5532 #define ETH_RETURN_CODE_RX_TX_SHIFT 7
5535 /* tx destination enum */
5536 enum eth_tx_dst_mode_config_enum {
5537 ETH_TX_DST_MODE_CONFIG_DISABLE,
5538 ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_BD,
5539 ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_VPORT,
5540 MAX_ETH_TX_DST_MODE_CONFIG_ENUM
5543 /* What to do in case an error occurs */
5546 ETH_TX_ERR_ASSERT_MALICIOUS,
5550 /* Array of the different error type behaviors */
5551 struct eth_tx_err_vals {
5553 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
5554 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
5555 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
5556 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1
5557 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
5558 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2
5559 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
5560 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3
5561 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
5562 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
5563 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
5564 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5
5565 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
5566 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6
5567 #define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_MASK 0x1
5568 #define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_SHIFT 7
5569 #define ETH_TX_ERR_VALS_RESERVED_MASK 0xFF
5570 #define ETH_TX_ERR_VALS_RESERVED_SHIFT 8
5573 /* vport rss configuration data */
5574 struct eth_vport_rss_config {
5575 __le16 capabilities;
5576 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
5577 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
5578 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
5579 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1
5580 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
5581 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2
5582 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
5583 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3
5584 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
5585 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4
5586 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
5587 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5
5588 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
5589 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
5590 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
5591 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7
5595 u8 update_rss_ind_table;
5596 u8 update_rss_capabilities;
5598 __le32 reserved2[2];
5599 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
5600 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
5601 __le32 reserved3[2];
5604 /* eth vport RSS mode */
5605 enum eth_vport_rss_mode {
5606 ETH_VPORT_RSS_MODE_DISABLED,
5607 ETH_VPORT_RSS_MODE_REGULAR,
5608 MAX_ETH_VPORT_RSS_MODE
5611 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
5612 struct eth_vport_rx_mode {
5614 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
5615 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
5616 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
5617 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
5618 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
5619 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
5620 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
5621 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3
5622 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
5623 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4
5624 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
5625 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5
5626 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_MASK 0x1
5627 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_SHIFT 6
5628 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x1FF
5629 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 7
5632 /* Command for setting tpa parameters */
5633 struct eth_vport_tpa_param {
5636 u8 tpa_ipv4_tunn_en_flg;
5637 u8 tpa_ipv6_tunn_en_flg;
5638 u8 tpa_pkt_split_flg;
5639 u8 tpa_hdr_data_split_flg;
5640 u8 tpa_gro_consistent_flg;
5642 u8 tpa_max_aggs_num;
5644 __le16 tpa_max_size;
5645 __le16 tpa_min_size_to_start;
5647 __le16 tpa_min_size_to_cont;
5652 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
5653 struct eth_vport_tx_mode {
5655 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
5656 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
5657 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
5658 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
5659 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
5660 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2
5661 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
5662 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
5663 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
5664 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
5665 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
5666 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5
5669 /* GFT filter update action type */
5670 enum gft_filter_update_action {
5673 MAX_GFT_FILTER_UPDATE_ACTION
5676 /* Ramrod data for rx add openflow filter */
5677 struct rx_add_openflow_filter_data {
5693 u8 tenant_id_exists;
5694 __le32 ipv4_dst_addr;
5695 __le32 ipv4_src_addr;
5700 /* Ramrod data for rx create gft action */
5701 struct rx_create_gft_action_data {
5706 /* Ramrod data for rx create openflow action */
5707 struct rx_create_openflow_action_data {
5712 /* Ramrod data for rx queue start ramrod */
5713 struct rx_queue_start_ramrod_data {
5715 __le16 num_of_pbl_pages;
5716 __le16 bd_max_bytes;
5720 u8 default_rss_queue_flg;
5721 u8 complete_cqe_flg;
5722 u8 complete_event_flg;
5723 u8 stats_counter_id;
5725 u8 pxp_tph_valid_bd;
5726 u8 pxp_tph_valid_pkt;
5729 __le16 pxp_st_index;
5735 u8 vf_rx_prod_index;
5736 u8 vf_rx_prod_use_zone_a;
5739 struct regpair cqe_pbl_addr;
5740 struct regpair bd_base;
5741 struct regpair reserved2;
5744 /* Ramrod data for rx queue stop ramrod */
5745 struct rx_queue_stop_ramrod_data {
5747 u8 complete_cqe_flg;
5748 u8 complete_event_flg;
5753 /* Ramrod data for rx queue update ramrod */
5754 struct rx_queue_update_ramrod_data {
5756 u8 complete_cqe_flg;
5757 u8 complete_event_flg;
5759 u8 set_default_rss_queue;
5766 struct regpair reserved6;
5769 /* Ramrod data for rx Add UDP Filter */
5770 struct rx_udp_filter_data {
5774 u8 tenant_id_exists;
5776 __le32 ip_dst_addr[4];
5777 __le32 ip_src_addr[4];
5778 __le16 udp_dst_port;
5779 __le16 udp_src_port;
5783 /* Add or delete GFT filter - filter is packet header of type of packet wished
5784 * to pass certain FW flow.
5786 struct rx_update_gft_filter_data {
5787 struct regpair pkt_hdr_addr;
5788 __le16 pkt_hdr_length;
5793 u8 action_icid_valid;
5798 u8 inner_vlan_removal_en;
5801 /* Ramrod data for tx queue start ramrod */
5802 struct tx_queue_start_ramrod_data {
5807 u8 stats_counter_id;
5810 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
5811 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
5812 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
5813 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
5814 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
5815 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 2
5816 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
5817 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 3
5818 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
5819 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 4
5820 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x7
5821 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 5
5823 u8 pxp_tph_valid_bd;
5824 u8 pxp_tph_valid_pkt;
5825 __le16 pxp_st_index;
5826 __le16 comp_agg_size;
5827 __le16 queue_zone_id;
5831 __le16 same_as_last_id;
5833 struct regpair pbl_base_addr;
5834 struct regpair bd_cons_address;
5837 /* Ramrod data for tx queue stop ramrod */
5838 struct tx_queue_stop_ramrod_data {
5842 /* Ramrod data for tx queue update ramrod */
5843 struct tx_queue_update_ramrod_data {
5844 __le16 update_qm_pq_id_flg;
5847 struct regpair reserved1[5];
5850 /* Inner to Inner VLAN priority map update mode */
5851 enum update_in_to_in_pri_map_mode_enum {
5852 ETH_IN_TO_IN_PRI_MAP_UPDATE_DISABLED,
5853 ETH_IN_TO_IN_PRI_MAP_UPDATE_NON_RDMA_TBL,
5854 ETH_IN_TO_IN_PRI_MAP_UPDATE_RDMA_TBL,
5855 MAX_UPDATE_IN_TO_IN_PRI_MAP_MODE_ENUM
5858 /* Ramrod data for vport update ramrod */
5859 struct vport_filter_update_ramrod_data {
5860 struct eth_filter_cmd_header filter_cmd_hdr;
5861 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
5864 /* Ramrod data for vport start ramrod */
5865 struct vport_start_ramrod_data {
5870 u8 inner_vlan_removal_en;
5871 struct eth_vport_rx_mode rx_mode;
5872 struct eth_vport_tx_mode tx_mode;
5873 struct eth_vport_tpa_param tpa_param;
5874 __le16 default_vlan;
5876 u8 anti_spoofing_en;
5879 u8 silent_vlan_removal_en;
5881 struct eth_tx_err_vals tx_err_behav;
5882 u8 zero_placement_offset;
5883 u8 ctl_frame_mac_check_en;
5884 u8 ctl_frame_ethtype_check_en;
5887 u8 tx_dst_port_mode_config;
5889 u8 tx_dst_port_mode;
5890 u8 dst_vport_id_valid;
5891 u8 wipe_inner_vlan_pri_en;
5893 struct eth_in_to_in_pri_map_cfg in_to_in_vlan_pri_map_cfg;
5896 /* Ramrod data for vport stop ramrod */
5897 struct vport_stop_ramrod_data {
5902 /* Ramrod data for vport update ramrod */
5903 struct vport_update_ramrod_data_cmn {
5905 u8 update_rx_active_flg;
5907 u8 update_tx_active_flg;
5909 u8 update_rx_mode_flg;
5910 u8 update_tx_mode_flg;
5911 u8 update_approx_mcast_flg;
5914 u8 update_inner_vlan_removal_en_flg;
5916 u8 inner_vlan_removal_en;
5917 u8 update_tpa_param_flg;
5918 u8 update_tpa_en_flg;
5919 u8 update_tx_switching_en_flg;
5922 u8 update_anti_spoofing_en_flg;
5924 u8 anti_spoofing_en;
5925 u8 update_handle_ptp_pkts;
5928 u8 update_default_vlan_en_flg;
5932 u8 update_default_vlan_flg;
5934 __le16 default_vlan;
5935 u8 update_accept_any_vlan_flg;
5938 u8 silent_vlan_removal_en;
5942 u8 update_ctl_frame_checks_en_flg;
5943 u8 ctl_frame_mac_check_en;
5944 u8 ctl_frame_ethtype_check_en;
5945 u8 update_in_to_in_pri_map_mode;
5946 u8 in_to_in_pri_map[8];
5950 struct vport_update_ramrod_mcast {
5951 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
5954 /* Ramrod data for vport update ramrod */
5955 struct vport_update_ramrod_data {
5956 struct vport_update_ramrod_data_cmn common;
5958 struct eth_vport_rx_mode rx_mode;
5959 struct eth_vport_tx_mode tx_mode;
5961 struct eth_vport_tpa_param tpa_param;
5962 struct vport_update_ramrod_mcast approx_mcast;
5963 struct eth_vport_rss_config rss_config;
5966 struct e4_xstorm_eth_conn_ag_ctx_dq_ext_ldpart {
5970 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
5971 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
5972 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
5973 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1
5974 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
5975 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2
5976 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
5977 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
5978 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
5979 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4
5980 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
5981 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5
5982 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
5983 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6
5984 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
5985 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7
5987 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
5988 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
5989 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
5990 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1
5991 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
5992 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2
5993 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
5994 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
5995 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK 0x1
5996 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_SHIFT 4
5997 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK 0x1
5998 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_SHIFT 5
5999 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
6000 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6
6001 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
6002 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7
6004 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
6005 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
6006 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
6007 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2
6008 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
6009 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4
6010 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
6011 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6
6013 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
6014 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
6015 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
6016 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2
6017 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
6018 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4
6019 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
6020 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6
6022 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
6023 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
6024 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
6025 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2
6026 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
6027 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4
6028 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
6029 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6
6031 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
6032 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
6033 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
6034 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2
6035 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
6036 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4
6037 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
6038 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6
6040 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
6041 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
6042 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
6043 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2
6044 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
6045 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4
6046 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
6047 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6
6049 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
6050 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
6051 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
6052 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2
6053 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
6054 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
6055 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
6056 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
6057 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
6058 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
6060 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
6061 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
6062 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
6063 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
6064 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
6065 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
6066 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
6067 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
6068 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
6069 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
6070 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
6071 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5
6072 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
6073 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
6074 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
6075 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
6077 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
6078 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
6079 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
6080 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
6081 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
6082 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
6083 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
6084 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
6085 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
6086 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
6087 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
6088 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
6089 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
6090 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6
6091 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
6092 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7
6094 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
6095 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
6096 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
6097 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1
6098 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
6099 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2
6100 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
6101 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3
6102 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
6103 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
6104 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
6105 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5
6106 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
6107 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6
6108 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
6109 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7
6111 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
6112 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
6113 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
6114 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1
6115 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
6116 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2
6117 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
6118 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
6119 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
6120 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
6121 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
6122 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
6123 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
6124 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
6125 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
6126 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
6128 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
6129 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
6130 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
6131 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
6132 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
6133 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
6134 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
6135 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
6136 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
6137 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
6138 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
6139 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
6140 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
6141 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
6142 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
6143 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
6145 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
6146 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
6147 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
6148 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
6149 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
6150 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
6151 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
6152 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
6153 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
6154 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
6155 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
6156 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
6157 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
6158 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
6159 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
6160 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
6162 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
6163 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
6164 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
6165 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1
6166 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
6167 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2
6168 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
6169 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3
6170 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
6171 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4
6172 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
6173 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
6174 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
6175 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6
6178 __le16 e5_reserved1;
6179 __le16 edpm_num_bds;
6182 __le16 updated_qm_pq_id;
6195 struct e4_mstorm_eth_conn_ag_ctx {
6199 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6200 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6201 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
6202 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
6203 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
6204 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2
6205 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
6206 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4
6207 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
6208 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
6210 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
6211 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
6212 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
6213 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1
6214 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
6215 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
6216 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
6217 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
6218 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
6219 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
6220 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
6221 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
6222 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
6223 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
6224 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
6225 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
6232 struct e4_xstorm_eth_hw_conn_ag_ctx {
6236 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6237 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6238 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
6239 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1
6240 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
6241 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2
6242 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
6243 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
6244 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
6245 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4
6246 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
6247 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5
6248 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1
6249 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6
6250 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1
6251 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7
6253 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1
6254 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
6255 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1
6256 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1
6257 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
6258 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2
6259 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
6260 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3
6261 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
6262 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_SHIFT 4
6263 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
6264 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_SHIFT 5
6265 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
6266 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
6267 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
6268 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
6270 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
6271 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
6272 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
6273 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2
6274 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
6275 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4
6276 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
6277 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6
6279 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
6280 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
6281 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
6282 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2
6283 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
6284 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4
6285 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
6286 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6
6288 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
6289 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
6290 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
6291 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2
6292 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
6293 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4
6294 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
6295 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6
6297 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
6298 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
6299 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
6300 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2
6301 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
6302 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4
6303 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
6304 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6
6306 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
6307 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
6308 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
6309 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
6310 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
6311 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4
6312 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
6313 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
6315 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
6316 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
6317 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
6318 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2
6319 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
6320 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4
6321 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
6322 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6
6323 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
6324 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7
6326 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
6327 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
6328 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
6329 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1
6330 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
6331 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2
6332 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
6333 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3
6334 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
6335 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4
6336 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
6337 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5
6338 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
6339 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6
6340 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
6341 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7
6343 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
6344 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
6345 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
6346 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1
6347 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
6348 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2
6349 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
6350 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3
6351 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
6352 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4
6353 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
6354 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5
6355 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
6356 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
6357 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
6358 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
6360 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
6361 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
6362 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
6363 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
6364 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
6365 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
6366 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
6367 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3
6368 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
6369 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
6370 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
6371 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
6372 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
6373 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6
6374 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
6375 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7
6377 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
6378 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
6379 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
6380 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1
6381 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
6382 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
6383 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
6384 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3
6385 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
6386 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4
6387 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
6388 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5
6389 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
6390 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
6391 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
6392 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7
6394 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
6395 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
6396 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
6397 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1
6398 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
6399 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
6400 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
6401 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
6402 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
6403 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4
6404 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
6405 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5
6406 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
6407 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6
6408 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
6409 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7
6411 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
6412 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
6413 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
6414 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1
6415 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
6416 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
6417 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
6418 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
6419 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
6420 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
6421 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
6422 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
6423 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
6424 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
6425 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
6426 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
6428 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
6429 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
6430 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
6431 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
6432 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
6433 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
6434 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
6435 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
6436 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
6437 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
6438 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
6439 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
6440 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
6441 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
6444 __le16 e5_reserved1;
6445 __le16 edpm_num_bds;
6448 __le16 updated_qm_pq_id;
6452 /* GFT CAM line struct with fields breakout */
6453 struct gft_cam_line_mapped {
6455 #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1
6456 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0
6457 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1
6458 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1
6459 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1
6460 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2
6461 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF
6462 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3
6463 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF
6464 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7
6465 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF
6466 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11
6467 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1
6468 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15
6469 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1
6470 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16
6471 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF
6472 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17
6473 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF
6474 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21
6475 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF
6476 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25
6477 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7
6478 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29
6482 /* Used in gft_profile_key: Indication for ip version */
6483 enum gft_profile_ip_version {
6484 GFT_PROFILE_IPV4 = 0,
6485 GFT_PROFILE_IPV6 = 1,
6486 MAX_GFT_PROFILE_IP_VERSION
6489 /* Profile key stucr fot GFT logic in Prs */
6490 struct gft_profile_key {
6492 #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1
6493 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0
6494 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1
6495 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1
6496 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF
6497 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2
6498 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF
6499 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6
6500 #define GFT_PROFILE_KEY_PF_ID_MASK 0xF
6501 #define GFT_PROFILE_KEY_PF_ID_SHIFT 10
6502 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3
6503 #define GFT_PROFILE_KEY_RESERVED0_SHIFT 14
6506 /* Used in gft_profile_key: Indication for tunnel type */
6507 enum gft_profile_tunnel_type {
6508 GFT_PROFILE_NO_TUNNEL = 0,
6509 GFT_PROFILE_VXLAN_TUNNEL = 1,
6510 GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2,
6511 GFT_PROFILE_GRE_IP_TUNNEL = 3,
6512 GFT_PROFILE_GENEVE_MAC_TUNNEL = 4,
6513 GFT_PROFILE_GENEVE_IP_TUNNEL = 5,
6514 MAX_GFT_PROFILE_TUNNEL_TYPE
6517 /* Used in gft_profile_key: Indication for protocol type */
6518 enum gft_profile_upper_protocol_type {
6519 GFT_PROFILE_ROCE_PROTOCOL = 0,
6520 GFT_PROFILE_RROCE_PROTOCOL = 1,
6521 GFT_PROFILE_FCOE_PROTOCOL = 2,
6522 GFT_PROFILE_ICMP_PROTOCOL = 3,
6523 GFT_PROFILE_ARP_PROTOCOL = 4,
6524 GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5,
6525 GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6,
6526 GFT_PROFILE_TCP_PROTOCOL = 7,
6527 GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8,
6528 GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9,
6529 GFT_PROFILE_UDP_PROTOCOL = 10,
6530 GFT_PROFILE_USER_IP_1_INNER = 11,
6531 GFT_PROFILE_USER_IP_2_OUTER = 12,
6532 GFT_PROFILE_USER_ETH_1_INNER = 13,
6533 GFT_PROFILE_USER_ETH_2_OUTER = 14,
6534 GFT_PROFILE_RAW = 15,
6535 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
6538 /* GFT RAM line struct */
6539 struct gft_ram_line {
6541 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3
6542 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0
6543 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1
6544 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2
6545 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1
6546 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3
6547 #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1
6548 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4
6549 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1
6550 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5
6551 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1
6552 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6
6553 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1
6554 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7
6555 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1
6556 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8
6557 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1
6558 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9
6559 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1
6560 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10
6561 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1
6562 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11
6563 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1
6564 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12
6565 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1
6566 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13
6567 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1
6568 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14
6569 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1
6570 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15
6571 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1
6572 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16
6573 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1
6574 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17
6575 #define GFT_RAM_LINE_TTL_MASK 0x1
6576 #define GFT_RAM_LINE_TTL_SHIFT 18
6577 #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1
6578 #define GFT_RAM_LINE_ETHERTYPE_SHIFT 19
6579 #define GFT_RAM_LINE_RESERVED0_MASK 0x1
6580 #define GFT_RAM_LINE_RESERVED0_SHIFT 20
6581 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1
6582 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21
6583 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1
6584 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22
6585 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1
6586 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23
6587 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1
6588 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24
6589 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1
6590 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25
6591 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1
6592 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26
6593 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1
6594 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27
6595 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1
6596 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28
6597 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1
6598 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29
6599 #define GFT_RAM_LINE_DST_PORT_MASK 0x1
6600 #define GFT_RAM_LINE_DST_PORT_SHIFT 30
6601 #define GFT_RAM_LINE_SRC_PORT_MASK 0x1
6602 #define GFT_RAM_LINE_SRC_PORT_SHIFT 31
6604 #define GFT_RAM_LINE_DSCP_MASK 0x1
6605 #define GFT_RAM_LINE_DSCP_SHIFT 0
6606 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1
6607 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1
6608 #define GFT_RAM_LINE_DST_IP_MASK 0x1
6609 #define GFT_RAM_LINE_DST_IP_SHIFT 2
6610 #define GFT_RAM_LINE_SRC_IP_MASK 0x1
6611 #define GFT_RAM_LINE_SRC_IP_SHIFT 3
6612 #define GFT_RAM_LINE_PRIORITY_MASK 0x1
6613 #define GFT_RAM_LINE_PRIORITY_SHIFT 4
6614 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1
6615 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5
6616 #define GFT_RAM_LINE_VLAN_MASK 0x1
6617 #define GFT_RAM_LINE_VLAN_SHIFT 6
6618 #define GFT_RAM_LINE_DST_MAC_MASK 0x1
6619 #define GFT_RAM_LINE_DST_MAC_SHIFT 7
6620 #define GFT_RAM_LINE_SRC_MAC_MASK 0x1
6621 #define GFT_RAM_LINE_SRC_MAC_SHIFT 8
6622 #define GFT_RAM_LINE_TENANT_ID_MASK 0x1
6623 #define GFT_RAM_LINE_TENANT_ID_SHIFT 9
6624 #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF
6625 #define GFT_RAM_LINE_RESERVED1_SHIFT 10
6628 /* Used in the first 2 bits for gft_ram_line: Indication for vlan mask */
6629 enum gft_vlan_select {
6630 INNER_PROVIDER_VLAN = 0,
6632 OUTER_PROVIDER_VLAN = 2,
6637 /* The rdma task context of Mstorm */
6638 struct ystorm_rdma_task_st_ctx {
6639 struct regpair temp[4];
6642 struct e4_ystorm_rdma_task_ag_ctx {
6645 __le16 msem_ctx_upd_seq;
6647 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
6648 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6649 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6650 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
6651 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6652 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
6653 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1
6654 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6
6655 #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1
6656 #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7
6658 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6659 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
6660 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6661 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
6662 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
6663 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
6664 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6665 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
6666 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6667 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
6669 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
6670 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
6671 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6672 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
6673 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6674 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
6675 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6676 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
6677 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6678 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
6679 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6680 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
6681 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6682 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
6683 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6684 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
6686 __le32 mw_cnt_or_qp_id;
6690 __le16 tx_ref_count;
6691 __le16 last_used_ltid;
6692 __le16 parent_mr_lo;
6693 __le16 parent_mr_hi;
6698 struct e4_mstorm_rdma_task_ag_ctx {
6703 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
6704 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6705 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6706 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
6707 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6708 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
6709 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
6710 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
6711 #define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1
6712 #define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7
6714 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6715 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
6716 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6717 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2
6718 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
6719 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4
6720 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6721 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6
6722 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6723 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7
6725 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
6726 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
6727 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6728 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1
6729 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6730 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2
6731 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6732 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3
6733 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6734 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4
6735 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6736 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5
6737 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6738 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6
6739 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6740 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7
6742 __le32 mw_cnt_or_qp_id;
6746 __le16 tx_ref_count;
6747 __le16 last_used_ltid;
6748 __le16 parent_mr_lo;
6749 __le16 parent_mr_hi;
6754 /* The roce task context of Mstorm */
6755 struct mstorm_rdma_task_st_ctx {
6756 struct regpair temp[4];
6759 /* The roce task context of Ustorm */
6760 struct ustorm_rdma_task_st_ctx {
6761 struct regpair temp[6];
6764 struct e4_ustorm_rdma_task_ag_ctx {
6769 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
6770 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
6771 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
6772 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
6773 #define E4_USTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6774 #define E4_USTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
6775 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
6776 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6
6778 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3
6779 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
6780 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3
6781 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2
6782 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_MASK 0x3
6783 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_SHIFT 4
6784 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
6785 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
6787 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1
6788 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
6789 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1
6790 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1
6791 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1
6792 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2
6793 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED4_MASK 0x1
6794 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED4_SHIFT 3
6795 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
6796 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
6797 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6798 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5
6799 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6800 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6
6801 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6802 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7
6804 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_MASK 0x1
6805 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_SHIFT 0
6806 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6807 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1
6808 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_MASK 0x1
6809 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_SHIFT 2
6810 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
6811 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3
6812 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
6813 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
6814 __le32 dif_err_intervals;
6815 __le32 dif_error_1st_interval;
6816 __le32 dif_rxmit_cons;
6817 __le32 dif_rxmit_prod;
6822 __le16 dif_write_cons;
6823 __le16 dif_write_prod;
6825 __le32 dif_error_buffer_address_lo;
6826 __le32 dif_error_buffer_address_hi;
6829 /* RDMA task context */
6830 struct e4_rdma_task_context {
6831 struct ystorm_rdma_task_st_ctx ystorm_st_context;
6832 struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context;
6833 struct tdif_task_context tdif_context;
6834 struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context;
6835 struct mstorm_rdma_task_st_ctx mstorm_st_context;
6836 struct rdif_task_context rdif_context;
6837 struct ustorm_rdma_task_st_ctx ustorm_st_context;
6838 struct regpair ustorm_st_padding[2];
6839 struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context;
6842 /* rdma function init ramrod data */
6843 struct rdma_close_func_ramrod_data {
6844 u8 cnq_start_offset;
6851 /* rdma function init CNQ parameters */
6852 struct rdma_cnq_params {
6857 struct regpair pbl_base_addr;
6858 __le16 queue_zone_num;
6862 /* rdma create cq ramrod data */
6863 struct rdma_create_cq_ramrod_data {
6864 struct regpair cq_handle;
6865 struct regpair pbl_addr;
6867 __le16 pbl_num_pages;
6869 u8 is_two_level_pbl;
6871 u8 pbl_log_page_size;
6876 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
6877 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 0
6878 #define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_MASK 0x7F
6879 #define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_SHIFT 1
6882 /* rdma deregister tid ramrod data */
6883 struct rdma_deregister_tid_ramrod_data {
6888 /* rdma destroy cq output params */
6889 struct rdma_destroy_cq_output_params {
6895 /* rdma destroy cq ramrod data */
6896 struct rdma_destroy_cq_ramrod_data {
6897 struct regpair output_params_addr;
6900 /* RDMA slow path EQ cmd IDs */
6901 enum rdma_event_opcode {
6903 RDMA_EVENT_FUNC_INIT,
6904 RDMA_EVENT_FUNC_CLOSE,
6905 RDMA_EVENT_REGISTER_MR,
6906 RDMA_EVENT_DEREGISTER_MR,
6907 RDMA_EVENT_CREATE_CQ,
6908 RDMA_EVENT_RESIZE_CQ,
6909 RDMA_EVENT_DESTROY_CQ,
6910 RDMA_EVENT_CREATE_SRQ,
6911 RDMA_EVENT_MODIFY_SRQ,
6912 RDMA_EVENT_DESTROY_SRQ,
6913 MAX_RDMA_EVENT_OPCODE
6916 /* RDMA FW return code for slow path ramrods */
6917 enum rdma_fw_return_code {
6919 RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
6920 RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
6921 RDMA_RETURN_RESIZE_CQ_ERR,
6922 RDMA_RETURN_NIG_DRAIN_REQ,
6923 RDMA_RETURN_GENERAL_ERR,
6924 MAX_RDMA_FW_RETURN_CODE
6927 /* rdma function init header */
6928 struct rdma_init_func_hdr {
6929 u8 cnq_start_offset;
6934 u8 relaxed_ordering;
6935 __le16 first_reg_srq_id;
6936 __le32 reg_srq_base_addr;
6943 /* rdma function init ramrod data */
6944 struct rdma_init_func_ramrod_data {
6945 struct rdma_init_func_hdr params_header;
6946 struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
6949 /* RDMA ramrod command IDs */
6950 enum rdma_ramrod_cmd_id {
6952 RDMA_RAMROD_FUNC_INIT,
6953 RDMA_RAMROD_FUNC_CLOSE,
6954 RDMA_RAMROD_REGISTER_MR,
6955 RDMA_RAMROD_DEREGISTER_MR,
6956 RDMA_RAMROD_CREATE_CQ,
6957 RDMA_RAMROD_RESIZE_CQ,
6958 RDMA_RAMROD_DESTROY_CQ,
6959 RDMA_RAMROD_CREATE_SRQ,
6960 RDMA_RAMROD_MODIFY_SRQ,
6961 RDMA_RAMROD_DESTROY_SRQ,
6962 MAX_RDMA_RAMROD_CMD_ID
6965 /* rdma register tid ramrod data */
6966 struct rdma_register_tid_ramrod_data {
6968 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F
6969 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 0
6970 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1
6971 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 5
6972 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1
6973 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 6
6974 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1
6975 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 7
6976 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1
6977 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 8
6978 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1
6979 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 9
6980 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1
6981 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 10
6982 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1
6983 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 11
6984 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1
6985 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 12
6986 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1
6987 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 13
6988 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3
6989 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT 14
6991 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F
6992 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
6993 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7
6994 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5
6996 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1
6997 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0
6998 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1
6999 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1
7000 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F
7001 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2
7012 struct regpair pbl_base;
7013 struct regpair dif_error_addr;
7014 __le32 reserved4[4];
7017 /* rdma resize cq output params */
7018 struct rdma_resize_cq_output_params {
7023 /* rdma resize cq ramrod data */
7024 struct rdma_resize_cq_ramrod_data {
7026 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1
7027 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0
7028 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1
7029 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1
7030 #define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
7031 #define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 2
7032 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x1F
7033 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 3
7034 u8 pbl_log_page_size;
7035 __le16 pbl_num_pages;
7037 struct regpair pbl_addr;
7038 struct regpair output_params_addr;
7043 /* The rdma SRQ context */
7044 struct rdma_srq_context {
7045 struct regpair temp[8];
7048 /* rdma create qp requester ramrod data */
7049 struct rdma_srq_create_ramrod_data {
7051 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK 0x1
7052 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT 0
7053 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
7054 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 1
7055 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK 0x3F
7056 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_SHIFT 2
7059 __le32 xrc_srq_cq_cid;
7060 struct regpair pbl_base_addr;
7061 __le16 pages_in_srq_pbl;
7063 struct rdma_srq_id srq_id;
7067 struct regpair producers_addr;
7070 /* rdma create qp requester ramrod data */
7071 struct rdma_srq_destroy_ramrod_data {
7072 struct rdma_srq_id srq_id;
7076 /* rdma create qp requester ramrod data */
7077 struct rdma_srq_modify_ramrod_data {
7078 struct rdma_srq_id srq_id;
7082 /* RDMA Tid type enumeration (for register_tid ramrod) */
7083 enum rdma_tid_type {
7084 RDMA_TID_REGISTERED_MR,
7090 /* The rdma XRC SRQ context */
7091 struct rdma_xrc_srq_context {
7092 struct regpair temp[9];
7095 struct e4_tstorm_rdma_task_ag_ctx {
7100 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF
7101 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
7102 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1
7103 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4
7104 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
7105 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5
7106 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
7107 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6
7108 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
7109 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7
7111 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
7112 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
7113 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1
7114 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1
7115 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
7116 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2
7117 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
7118 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4
7119 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
7120 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6
7122 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
7123 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0
7124 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3
7125 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2
7126 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3
7127 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4
7128 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3
7129 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6
7131 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3
7132 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0
7133 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
7134 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2
7135 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
7136 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3
7137 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
7138 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4
7139 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
7140 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5
7141 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1
7142 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6
7143 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1
7144 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7
7146 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1
7147 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0
7148 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1
7149 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1
7150 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
7151 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2
7152 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
7153 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3
7154 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
7155 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4
7156 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
7157 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5
7158 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
7159 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6
7160 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
7161 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7
7174 struct e4_ustorm_rdma_conn_ag_ctx {
7178 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7179 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7180 #define E4_USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_MASK 0x1
7181 #define E4_USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_SHIFT 1
7182 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7183 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2
7184 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
7185 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4
7186 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
7187 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6
7189 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
7190 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0
7191 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
7192 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
7193 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
7194 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
7195 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
7196 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6
7198 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7199 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7200 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
7201 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1
7202 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
7203 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2
7204 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
7205 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3
7206 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
7207 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
7208 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
7209 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
7210 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
7211 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6
7212 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
7213 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
7215 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1
7216 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0
7217 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
7218 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1
7219 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
7220 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2
7221 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
7222 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3
7223 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
7224 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4
7225 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
7226 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5
7227 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
7228 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6
7229 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
7230 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7
7243 struct e4_xstorm_roce_conn_ag_ctx {
7247 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7248 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7249 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
7250 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1
7251 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1
7252 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT 2
7253 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
7254 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
7255 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1
7256 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT 4
7257 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1
7258 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT 5
7259 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT6_MASK 0x1
7260 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT6_SHIFT 6
7261 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT7_MASK 0x1
7262 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT7_SHIFT 7
7264 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT8_MASK 0x1
7265 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT8_SHIFT 0
7266 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT9_MASK 0x1
7267 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT9_SHIFT 1
7268 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT10_MASK 0x1
7269 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT10_SHIFT 2
7270 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_MASK 0x1
7271 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_SHIFT 3
7272 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
7273 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4
7274 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
7275 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5
7276 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT14_MASK 0x1
7277 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT14_SHIFT 6
7278 #define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
7279 #define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
7281 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
7282 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 0
7283 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
7284 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 2
7285 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
7286 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 4
7287 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3_MASK 0x3
7288 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3_SHIFT 6
7290 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4_MASK 0x3
7291 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4_SHIFT 0
7292 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3
7293 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT 2
7294 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3
7295 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT 4
7296 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7297 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7299 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3
7300 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT 0
7301 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3
7302 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT 2
7303 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3
7304 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT 4
7305 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11_MASK 0x3
7306 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11_SHIFT 6
7308 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12_MASK 0x3
7309 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12_SHIFT 0
7310 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13_MASK 0x3
7311 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13_SHIFT 2
7312 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14_MASK 0x3
7313 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14_SHIFT 4
7314 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15_MASK 0x3
7315 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15_SHIFT 6
7317 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16_MASK 0x3
7318 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16_SHIFT 0
7319 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17_MASK 0x3
7320 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17_SHIFT 2
7321 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18_MASK 0x3
7322 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18_SHIFT 4
7323 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19_MASK 0x3
7324 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19_SHIFT 6
7326 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20_MASK 0x3
7327 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20_SHIFT 0
7328 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21_MASK 0x3
7329 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21_SHIFT 2
7330 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
7331 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
7332 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
7333 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 6
7334 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
7335 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 7
7337 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
7338 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 0
7339 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3EN_MASK 0x1
7340 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3EN_SHIFT 1
7341 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4EN_MASK 0x1
7342 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4EN_SHIFT 2
7343 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1
7344 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT 3
7345 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1
7346 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT 4
7347 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7348 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
7349 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1
7350 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT 6
7351 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1
7352 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT 7
7354 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1
7355 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT 0
7356 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11EN_MASK 0x1
7357 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11EN_SHIFT 1
7358 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12EN_MASK 0x1
7359 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12EN_SHIFT 2
7360 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13EN_MASK 0x1
7361 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13EN_SHIFT 3
7362 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14EN_MASK 0x1
7363 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14EN_SHIFT 4
7364 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15EN_MASK 0x1
7365 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15EN_SHIFT 5
7366 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16EN_MASK 0x1
7367 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16EN_SHIFT 6
7368 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17EN_MASK 0x1
7369 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17EN_SHIFT 7
7371 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18EN_MASK 0x1
7372 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18EN_SHIFT 0
7373 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19EN_MASK 0x1
7374 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19EN_SHIFT 1
7375 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20EN_MASK 0x1
7376 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20EN_SHIFT 2
7377 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21EN_MASK 0x1
7378 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21EN_SHIFT 3
7379 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
7380 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
7381 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23EN_MASK 0x1
7382 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23EN_SHIFT 5
7383 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
7384 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 6
7385 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
7386 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 7
7388 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
7389 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 0
7390 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
7391 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 1
7392 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
7393 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 2
7394 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1
7395 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT 3
7396 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1
7397 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 4
7398 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1
7399 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT 5
7400 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
7401 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
7402 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE9EN_MASK 0x1
7403 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE9EN_SHIFT 7
7405 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE10EN_MASK 0x1
7406 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE10EN_SHIFT 0
7407 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE11EN_MASK 0x1
7408 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE11EN_SHIFT 1
7409 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
7410 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
7411 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
7412 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
7413 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE14EN_MASK 0x1
7414 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE14EN_SHIFT 4
7415 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE15EN_MASK 0x1
7416 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE15EN_SHIFT 5
7417 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE16EN_MASK 0x1
7418 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE16EN_SHIFT 6
7419 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE17EN_MASK 0x1
7420 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE17EN_SHIFT 7
7422 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE18EN_MASK 0x1
7423 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE18EN_SHIFT 0
7424 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE19EN_MASK 0x1
7425 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE19EN_SHIFT 1
7426 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
7427 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
7428 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
7429 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
7430 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
7431 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
7432 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
7433 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
7434 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
7435 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
7436 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
7437 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
7439 #define E4_XSTORM_ROCE_CONN_AG_CTX_MIGRATION_MASK 0x1
7440 #define E4_XSTORM_ROCE_CONN_AG_CTX_MIGRATION_SHIFT 0
7441 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT17_MASK 0x1
7442 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT17_SHIFT 1
7443 #define E4_XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
7444 #define E4_XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
7445 #define E4_XSTORM_ROCE_CONN_AG_CTX_RESERVED_MASK 0x1
7446 #define E4_XSTORM_ROCE_CONN_AG_CTX_RESERVED_SHIFT 4
7447 #define E4_XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
7448 #define E4_XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
7449 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23_MASK 0x3
7450 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23_SHIFT 6
7472 struct e4_tstorm_roce_conn_ag_ctx {
7476 #define E4_TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7477 #define E4_TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7478 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
7479 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1
7480 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1
7481 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT 2
7482 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT3_MASK 0x1
7483 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT3_SHIFT 3
7484 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1
7485 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT 4
7486 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1
7487 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT 5
7488 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
7489 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 6
7491 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7492 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
7493 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
7494 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 2
7495 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
7496 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
7497 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7498 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
7500 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3
7501 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT 0
7502 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3
7503 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT 2
7504 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7_MASK 0x3
7505 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7_SHIFT 4
7506 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3
7507 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT 6
7509 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3
7510 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT 0
7511 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3
7512 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT 2
7513 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
7514 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 4
7515 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
7516 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5
7517 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
7518 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 6
7519 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
7520 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
7522 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7523 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7524 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1
7525 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT 1
7526 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1
7527 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT 2
7528 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7EN_MASK 0x1
7529 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7EN_SHIFT 3
7530 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1
7531 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT 4
7532 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1
7533 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT 5
7534 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1
7535 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT 6
7536 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
7537 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 7
7539 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
7540 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 0
7541 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
7542 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 1
7543 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
7544 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 2
7545 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
7546 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 3
7547 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1
7548 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT 4
7549 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1
7550 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 5
7551 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1
7552 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT 6
7553 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE8EN_MASK 0x1
7554 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE8EN_SHIFT 7
7576 /* The roce storm context of Ystorm */
7577 struct ystorm_roce_conn_st_ctx {
7578 struct regpair temp[2];
7581 /* The roce storm context of Mstorm */
7582 struct pstorm_roce_conn_st_ctx {
7583 struct regpair temp[16];
7586 /* The roce storm context of Xstorm */
7587 struct xstorm_roce_conn_st_ctx {
7588 struct regpair temp[24];
7591 /* The roce storm context of Tstorm */
7592 struct tstorm_roce_conn_st_ctx {
7593 struct regpair temp[30];
7596 /* The roce storm context of Mstorm */
7597 struct mstorm_roce_conn_st_ctx {
7598 struct regpair temp[6];
7601 /* The roce storm context of Ustorm */
7602 struct ustorm_roce_conn_st_ctx {
7603 struct regpair temp[14];
7606 /* roce connection context */
7607 struct e4_roce_conn_context {
7608 struct ystorm_roce_conn_st_ctx ystorm_st_context;
7609 struct regpair ystorm_st_padding[2];
7610 struct pstorm_roce_conn_st_ctx pstorm_st_context;
7611 struct xstorm_roce_conn_st_ctx xstorm_st_context;
7612 struct e4_xstorm_roce_conn_ag_ctx xstorm_ag_context;
7613 struct e4_tstorm_roce_conn_ag_ctx tstorm_ag_context;
7614 struct timers_context timer_context;
7615 struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context;
7616 struct tstorm_roce_conn_st_ctx tstorm_st_context;
7617 struct regpair tstorm_st_padding[2];
7618 struct mstorm_roce_conn_st_ctx mstorm_st_context;
7619 struct regpair mstorm_st_padding[2];
7620 struct ustorm_roce_conn_st_ctx ustorm_st_context;
7621 struct regpair ustorm_st_padding[2];
7624 /* roce cqes statistics */
7625 struct roce_cqe_stats {
7626 __le32 req_cqe_error;
7627 __le32 req_remote_access_errors;
7628 __le32 req_remote_invalid_request;
7629 __le32 resp_cqe_error;
7630 __le32 resp_local_length_error;
7634 /* roce create qp requester ramrod data */
7635 struct roce_create_qp_req_ramrod_data {
7637 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
7638 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
7639 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
7640 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2
7641 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
7642 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3
7643 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
7644 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4
7645 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK 0x1
7646 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_SHIFT 7
7647 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
7648 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8
7649 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
7650 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12
7658 __le32 ack_timeout_val;
7662 __le16 sq_num_pages;
7663 __le16 low_latency_phy_queue;
7664 struct regpair sq_pbl_addr;
7665 struct regpair orq_pbl_addr;
7666 __le16 local_mac_addr[3];
7667 __le16 remote_mac_addr[3];
7669 __le16 udp_src_port;
7673 struct regpair qp_handle_for_cqe;
7674 struct regpair qp_handle_for_async;
7675 u8 stats_counter_id;
7679 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_MASK 0x1
7680 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_SHIFT 0
7681 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
7682 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_SHIFT 1
7683 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x3F
7684 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 2
7687 __le16 regular_latency_phy_queue;
7691 /* roce create qp responder ramrod data */
7692 struct roce_create_qp_resp_ramrod_data {
7694 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
7695 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
7696 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
7697 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
7698 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
7699 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
7700 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
7701 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
7702 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1
7703 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5
7704 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1
7705 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6
7706 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
7707 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7
7708 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
7709 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8
7710 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
7711 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11
7712 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK 0x1
7713 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_SHIFT 16
7714 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_MASK 0x1
7715 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_SHIFT 17
7716 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK 0x3FFF
7717 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT 18
7726 u8 stats_counter_id;
7731 __le16 rq_num_pages;
7732 struct rdma_srq_id srq_id;
7733 struct regpair rq_pbl_addr;
7734 struct regpair irq_pbl_addr;
7735 __le16 local_mac_addr[3];
7736 __le16 remote_mac_addr[3];
7738 __le16 udp_src_port;
7741 struct regpair qp_handle_for_cqe;
7742 struct regpair qp_handle_for_async;
7743 __le16 low_latency_phy_queue;
7747 __le16 regular_latency_phy_queue;
7754 /* roce DCQCN received statistics */
7755 struct roce_dcqcn_received_stats {
7756 struct regpair ecn_pkt_rcv;
7757 struct regpair cnp_pkt_rcv;
7760 /* roce DCQCN sent statistics */
7761 struct roce_dcqcn_sent_stats {
7762 struct regpair cnp_pkt_sent;
7765 /* RoCE destroy qp requester output params */
7766 struct roce_destroy_qp_req_output_params {
7771 /* RoCE destroy qp requester ramrod data */
7772 struct roce_destroy_qp_req_ramrod_data {
7773 struct regpair output_params_addr;
7776 /* RoCE destroy qp responder output params */
7777 struct roce_destroy_qp_resp_output_params {
7782 /* RoCE destroy qp responder ramrod data */
7783 struct roce_destroy_qp_resp_ramrod_data {
7784 struct regpair output_params_addr;
7789 /* roce error statistics */
7790 struct roce_error_stats {
7791 __le32 resp_remote_access_errors;
7795 /* roce special events statistics */
7796 struct roce_events_stats {
7797 __le32 silent_drops;
7798 __le32 rnr_naks_sent;
7799 __le32 retransmit_count;
7800 __le32 icrc_error_count;
7801 __le32 implied_nak_seq_err;
7802 __le32 duplicate_request;
7803 __le32 local_ack_timeout_err;
7804 __le32 out_of_sequence;
7805 __le32 packet_seq_err;
7806 __le32 rnr_nak_retry_err;
7809 /* roce slow path EQ cmd IDs */
7810 enum roce_event_opcode {
7811 ROCE_EVENT_CREATE_QP = 11,
7812 ROCE_EVENT_MODIFY_QP,
7813 ROCE_EVENT_QUERY_QP,
7814 ROCE_EVENT_DESTROY_QP,
7815 ROCE_EVENT_CREATE_UD_QP,
7816 ROCE_EVENT_DESTROY_UD_QP,
7817 ROCE_EVENT_FUNC_UPDATE,
7818 MAX_ROCE_EVENT_OPCODE
7821 /* roce func init ramrod data */
7822 struct roce_init_func_params {
7824 u8 cnp_vlan_priority;
7827 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1
7828 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_SHIFT 0
7829 #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1
7830 #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_SHIFT 1
7831 #define ROCE_INIT_FUNC_PARAMS_RESERVED0_MASK 0x3F
7832 #define ROCE_INIT_FUNC_PARAMS_RESERVED0_SHIFT 2
7833 __le32 cnp_send_timeout;
7839 /* roce func init ramrod data */
7840 struct roce_init_func_ramrod_data {
7841 struct rdma_init_func_ramrod_data rdma;
7842 struct roce_init_func_params roce;
7845 /* roce modify qp requester ramrod data */
7846 struct roce_modify_qp_req_ramrod_data {
7848 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
7849 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
7850 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1
7851 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1
7852 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1
7853 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2
7854 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1
7855 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3
7856 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
7857 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4
7858 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1
7859 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5
7860 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1
7861 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6
7862 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1
7863 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7
7864 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1
7865 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8
7866 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1
7867 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9
7868 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
7869 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10
7870 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
7871 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 13
7872 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x3
7873 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 14
7875 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
7876 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0
7877 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
7878 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4
7884 __le32 ack_timeout_val;
7887 __le32 reserved3[2];
7888 __le16 low_latency_phy_queue;
7889 __le16 regular_latency_phy_queue;
7894 /* roce modify qp responder ramrod data */
7895 struct roce_modify_qp_resp_ramrod_data {
7897 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
7898 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
7899 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
7900 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1
7901 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
7902 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2
7903 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
7904 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3
7905 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1
7906 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4
7907 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
7908 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5
7909 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1
7910 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6
7911 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1
7912 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7
7913 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1
7914 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8
7915 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
7916 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9
7917 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
7918 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 10
7919 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x1F
7920 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 11
7922 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
7923 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0
7924 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
7925 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3
7932 __le16 low_latency_phy_queue;
7933 __le16 regular_latency_phy_queue;
7939 /* RoCE query qp requester output params */
7940 struct roce_query_qp_req_output_params {
7943 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1
7944 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0
7945 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1
7946 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1
7947 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF
7948 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2
7951 /* RoCE query qp requester ramrod data */
7952 struct roce_query_qp_req_ramrod_data {
7953 struct regpair output_params_addr;
7956 /* RoCE query qp responder output params */
7957 struct roce_query_qp_resp_output_params {
7960 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
7961 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
7962 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
7963 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
7966 /* RoCE query qp responder ramrod data */
7967 struct roce_query_qp_resp_ramrod_data {
7968 struct regpair output_params_addr;
7971 /* ROCE ramrod command IDs */
7972 enum roce_ramrod_cmd_id {
7973 ROCE_RAMROD_CREATE_QP = 11,
7974 ROCE_RAMROD_MODIFY_QP,
7975 ROCE_RAMROD_QUERY_QP,
7976 ROCE_RAMROD_DESTROY_QP,
7977 ROCE_RAMROD_CREATE_UD_QP,
7978 ROCE_RAMROD_DESTROY_UD_QP,
7979 ROCE_RAMROD_FUNC_UPDATE,
7980 MAX_ROCE_RAMROD_CMD_ID
7983 /* RoCE func init ramrod data */
7984 struct roce_update_func_params {
7985 u8 cnp_vlan_priority;
7988 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1
7989 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_SHIFT 0
7990 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1
7991 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_SHIFT 1
7992 #define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_MASK 0x3FFF
7993 #define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_SHIFT 2
7994 __le32 cnp_send_timeout;
7997 struct e4_xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
8001 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
8002 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
8003 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1
8004 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1
8005 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1
8006 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2
8007 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
8008 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3
8009 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1
8010 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4
8011 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1
8012 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5
8013 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1
8014 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6
8015 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1
8016 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7
8018 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1
8019 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0
8020 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1
8021 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1
8022 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1
8023 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2
8024 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
8025 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3
8026 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK 0x1
8027 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_SHIFT 4
8028 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK 0x1
8029 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_SHIFT 5
8030 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1
8031 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6
8032 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1
8033 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7
8035 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3
8036 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0
8037 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3
8038 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2
8039 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3
8040 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4
8041 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3
8042 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6
8044 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3
8045 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0
8046 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3
8047 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2
8048 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3
8049 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4
8050 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3
8051 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6
8053 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3
8054 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0
8055 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3
8056 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2
8057 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3
8058 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4
8059 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3
8060 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6
8062 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3
8063 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0
8064 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3
8065 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2
8066 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3
8067 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4
8068 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3
8069 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6
8071 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3
8072 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0
8073 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3
8074 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2
8075 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3
8076 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4
8077 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3
8078 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6
8080 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3
8081 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0
8082 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3
8083 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2
8084 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
8085 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4
8086 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
8087 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6
8088 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
8089 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7
8091 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
8092 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
8093 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
8094 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1
8095 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
8096 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2
8097 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
8098 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3
8099 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
8100 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4
8101 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1
8102 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5
8103 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
8104 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6
8105 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
8106 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7
8108 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
8109 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
8110 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
8111 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1
8112 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
8113 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2
8114 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
8115 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3
8116 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
8117 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4
8118 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
8119 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5
8120 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1
8121 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6
8122 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1
8123 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7
8125 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1
8126 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0
8127 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1
8128 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1
8129 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1
8130 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2
8131 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1
8132 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3
8133 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
8134 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4
8135 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1
8136 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5
8137 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1
8138 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6
8139 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1
8140 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7
8142 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1
8143 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0
8144 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1
8145 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1
8146 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1
8147 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2
8148 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
8149 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3
8150 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
8151 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4
8152 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
8153 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5
8154 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
8155 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6
8156 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
8157 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7
8159 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
8160 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
8161 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
8162 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1
8163 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
8164 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2
8165 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
8166 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3
8167 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
8168 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4
8169 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
8170 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5
8171 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
8172 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6
8173 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
8174 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7
8176 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
8177 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
8178 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
8179 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1
8180 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
8181 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2
8182 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
8183 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3
8184 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
8185 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4
8186 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
8187 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5
8188 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
8189 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6
8190 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
8191 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7
8193 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1
8194 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0
8195 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1
8196 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1
8197 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3
8198 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2
8199 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1
8200 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4
8201 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
8202 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5
8203 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3
8204 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6
8224 struct e4_mstorm_roce_conn_ag_ctx {
8228 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1
8229 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0
8230 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
8231 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1
8232 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
8233 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 2
8234 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
8235 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 4
8236 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
8237 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 6
8239 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
8240 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0
8241 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
8242 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1
8243 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
8244 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2
8245 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
8246 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3
8247 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
8248 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4
8249 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
8250 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5
8251 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
8252 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6
8253 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
8254 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7
8261 struct e4_mstorm_roce_req_conn_ag_ctx {
8265 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
8266 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
8267 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
8268 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
8269 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8270 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
8271 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8272 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
8273 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8274 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
8276 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8277 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
8278 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8279 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
8280 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8281 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
8282 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8283 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
8284 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8285 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
8286 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8287 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
8288 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8289 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
8290 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8291 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
8298 struct e4_mstorm_roce_resp_conn_ag_ctx {
8302 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
8303 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
8304 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
8305 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
8306 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8307 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
8308 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8309 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
8310 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8311 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
8313 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8314 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
8315 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8316 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
8317 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8318 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
8319 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8320 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
8321 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8322 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
8323 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8324 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
8325 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8326 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
8327 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8328 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
8335 struct e4_tstorm_roce_req_conn_ag_ctx {
8339 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8340 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8341 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK 0x1
8342 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_SHIFT 1
8343 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK 0x1
8344 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_SHIFT 2
8345 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1
8346 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3
8347 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
8348 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
8349 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
8350 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
8351 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3
8352 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6
8354 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
8355 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
8356 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3
8357 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2
8358 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
8359 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
8360 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8361 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
8363 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_MASK 0x3
8364 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_SHIFT 0
8365 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3
8366 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2
8367 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3
8368 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4
8369 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3
8370 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6
8372 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3
8373 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0
8374 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3
8375 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2
8376 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1
8377 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4
8378 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
8379 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5
8380 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1
8381 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6
8382 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
8383 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
8385 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8386 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
8387 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_MASK 0x1
8388 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_SHIFT 1
8389 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1
8390 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2
8391 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1
8392 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3
8393 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1
8394 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4
8395 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1
8396 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5
8397 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1
8398 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6
8399 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8400 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
8402 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8403 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
8404 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_MASK 0x1
8405 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_SHIFT 1
8406 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8407 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
8408 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8409 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
8410 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
8411 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
8412 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1
8413 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5
8414 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
8415 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
8416 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
8417 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
8418 __le32 dif_rxmit_cnt;
8423 __le32 dif_acked_cnt;
8427 u8 tx_cqe_error_type;
8429 __le16 snd_sq_cons_th;
8434 __le16 force_comp_cons;
8435 __le32 dif_rxmit_acked_cnt;
8439 struct e4_tstorm_roce_resp_conn_ag_ctx {
8443 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8444 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8445 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1
8446 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1
8447 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1
8448 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2
8449 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1
8450 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3
8451 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
8452 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4
8453 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1
8454 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5
8455 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8456 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6
8458 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
8459 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
8460 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3
8461 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2
8462 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8463 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4
8464 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8465 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
8467 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8468 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0
8469 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
8470 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2
8471 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3
8472 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4
8473 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
8474 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6
8476 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
8477 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0
8478 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
8479 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2
8480 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8481 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4
8482 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
8483 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5
8484 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1
8485 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6
8486 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
8487 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7
8489 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8490 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
8491 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
8492 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 1
8493 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
8494 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2
8495 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1
8496 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3
8497 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
8498 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4
8499 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
8500 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5
8501 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
8502 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6
8503 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8504 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
8506 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8507 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
8508 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8509 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
8510 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8511 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
8512 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8513 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
8514 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8515 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
8516 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1
8517 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5
8518 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8519 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
8520 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
8521 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
8522 __le32 psn_and_rxmit_id_echo;
8531 u8 tx_async_error_type;
8543 struct e4_ustorm_roce_req_conn_ag_ctx {
8547 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
8548 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
8549 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
8550 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
8551 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8552 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
8553 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8554 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
8555 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8556 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
8558 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
8559 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0
8560 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3
8561 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2
8562 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3
8563 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4
8564 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3
8565 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6
8567 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8568 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
8569 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8570 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
8571 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8572 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
8573 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
8574 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3
8575 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1
8576 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4
8577 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1
8578 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5
8579 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1
8580 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6
8581 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8582 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7
8584 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8585 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
8586 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8587 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1
8588 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8589 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2
8590 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8591 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3
8592 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
8593 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4
8594 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
8595 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5
8596 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
8597 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6
8598 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
8599 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7
8612 struct e4_ustorm_roce_resp_conn_ag_ctx {
8616 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
8617 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
8618 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
8619 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
8620 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8621 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
8622 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8623 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
8624 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8625 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
8627 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8628 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0
8629 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3
8630 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2
8631 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3
8632 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4
8633 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
8634 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6
8636 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8637 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
8638 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8639 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
8640 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8641 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
8642 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
8643 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3
8644 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1
8645 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4
8646 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1
8647 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5
8648 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
8649 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6
8650 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8651 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7
8653 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8654 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
8655 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8656 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1
8657 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8658 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2
8659 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8660 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3
8661 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8662 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4
8663 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
8664 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5
8665 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8666 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6
8667 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
8668 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7
8681 struct e4_xstorm_roce_req_conn_ag_ctx {
8685 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8686 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8687 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1
8688 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1
8689 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1
8690 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2
8691 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8692 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
8693 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1
8694 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4
8695 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1
8696 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5
8697 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1
8698 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6
8699 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1
8700 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7
8702 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1
8703 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0
8704 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1
8705 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1
8706 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1
8707 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2
8708 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1
8709 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3
8710 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
8711 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4
8712 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
8713 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5
8714 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1
8715 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6
8716 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
8717 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
8719 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8720 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0
8721 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8722 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2
8723 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8724 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4
8725 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
8726 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6
8728 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
8729 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0
8730 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8731 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
8732 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3
8733 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4
8734 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8735 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
8737 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_MASK 0x3
8738 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_SHIFT 0
8739 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_MASK 0x3
8740 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_SHIFT 2
8741 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3
8742 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4
8743 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3
8744 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6
8746 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3
8747 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0
8748 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3
8749 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2
8750 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3
8751 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4
8752 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3
8753 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6
8755 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3
8756 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0
8757 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3
8758 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2
8759 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3
8760 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4
8761 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3
8762 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6
8764 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3
8765 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0
8766 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3
8767 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2
8768 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8769 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4
8770 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8771 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6
8772 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8773 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7
8775 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8776 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0
8777 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
8778 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1
8779 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
8780 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2
8781 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
8782 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
8783 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1
8784 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4
8785 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8786 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
8787 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
8788 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_SHIFT 6
8789 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_MASK 0x1
8790 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_SHIFT 7
8792 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1
8793 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0
8794 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1
8795 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1
8796 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1
8797 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2
8798 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1
8799 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3
8800 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1
8801 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4
8802 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1
8803 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5
8804 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1
8805 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6
8806 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1
8807 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7
8809 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1
8810 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0
8811 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1
8812 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1
8813 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1
8814 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2
8815 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1
8816 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3
8817 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8818 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
8819 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1
8820 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5
8821 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8822 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6
8823 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8824 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7
8826 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8827 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0
8828 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8829 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1
8830 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8831 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2
8832 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
8833 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3
8834 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
8835 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4
8836 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1
8837 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5
8838 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8839 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
8840 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1
8841 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7
8843 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1
8844 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0
8845 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1
8846 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1
8847 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8848 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
8849 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8850 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
8851 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1
8852 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4
8853 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1
8854 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5
8855 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1
8856 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6
8857 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1
8858 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7
8860 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1
8861 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0
8862 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1
8863 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1
8864 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
8865 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
8866 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
8867 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
8868 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8869 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
8870 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
8871 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
8872 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8873 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
8874 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8875 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
8877 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1
8878 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0
8879 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1
8880 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1
8881 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
8882 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2
8883 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1
8884 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4
8885 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
8886 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
8887 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3
8888 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6
8895 __le16 dif_error_first_sq_cons;
8897 u8 dif_error_sge_index;
8905 __le32 dif_error_offset;
8910 struct e4_xstorm_roce_resp_conn_ag_ctx {
8914 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8915 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8916 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1
8917 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1
8918 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1
8919 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2
8920 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8921 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
8922 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1
8923 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4
8924 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1
8925 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5
8926 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1
8927 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6
8928 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1
8929 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7
8931 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1
8932 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0
8933 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1
8934 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1
8935 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1
8936 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2
8937 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1
8938 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3
8939 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
8940 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4
8941 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
8942 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5
8943 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1
8944 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6
8945 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
8946 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7
8948 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8949 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0
8950 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8951 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2
8952 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8953 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4
8954 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8955 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6
8957 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3
8958 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0
8959 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8960 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2
8961 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3
8962 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4
8963 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8964 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6
8966 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
8967 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0
8968 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
8969 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2
8970 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
8971 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4
8972 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3
8973 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6
8975 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3
8976 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0
8977 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3
8978 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2
8979 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3
8980 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4
8981 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3
8982 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6
8984 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3
8985 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0
8986 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3
8987 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2
8988 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3
8989 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4
8990 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3
8991 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6
8993 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3
8994 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0
8995 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3
8996 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2
8997 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8998 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
8999 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
9000 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6
9001 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
9002 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7
9004 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
9005 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0
9006 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
9007 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1
9008 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1
9009 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2
9010 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
9011 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3
9012 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1
9013 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4
9014 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
9015 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
9016 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
9017 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6
9018 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
9019 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7
9021 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
9022 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0
9023 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1
9024 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1
9025 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1
9026 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2
9027 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1
9028 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3
9029 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1
9030 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4
9031 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1
9032 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5
9033 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1
9034 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6
9035 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1
9036 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7
9038 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1
9039 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0
9040 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1
9041 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1
9042 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1
9043 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2
9044 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1
9045 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3
9046 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
9047 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
9048 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1
9049 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5
9050 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
9051 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6
9052 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
9053 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7
9055 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
9056 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0
9057 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
9058 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1
9059 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
9060 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2
9061 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
9062 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3
9063 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
9064 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4
9065 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
9066 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5
9067 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
9068 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
9069 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1
9070 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7
9072 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1
9073 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 0
9074 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK 0x1
9075 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT 1
9076 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
9077 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
9078 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
9079 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
9080 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1
9081 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4
9082 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1
9083 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5
9084 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1
9085 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6
9086 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1
9087 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7
9089 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1
9090 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0
9091 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1
9092 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1
9093 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
9094 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
9095 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
9096 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
9097 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
9098 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
9099 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
9100 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
9101 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
9102 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
9103 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
9104 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
9106 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1
9107 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0
9108 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1
9109 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1
9110 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1
9111 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2
9112 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1
9113 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3
9114 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1
9115 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4
9116 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1
9117 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5
9118 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3
9119 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6
9122 __le16 irq_prod_shadow;
9126 __le16 e5_reserved1;
9132 __le32 rxmit_psn_and_id;
9133 __le32 rxmit_bytes_length;
9138 __le32 msn_and_syndrome;
9141 struct e4_ystorm_roce_conn_ag_ctx {
9145 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1
9146 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0
9147 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
9148 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1
9149 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
9150 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 2
9151 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
9152 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 4
9153 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
9154 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 6
9156 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
9157 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0
9158 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
9159 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1
9160 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
9161 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2
9162 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
9163 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3
9164 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
9165 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4
9166 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
9167 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5
9168 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
9169 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6
9170 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
9171 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7
9185 struct e4_ystorm_roce_req_conn_ag_ctx {
9189 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
9190 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
9191 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
9192 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1
9193 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
9194 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2
9195 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
9196 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4
9197 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
9198 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6
9200 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
9201 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
9202 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
9203 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1
9204 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
9205 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2
9206 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
9207 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3
9208 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
9209 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4
9210 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
9211 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5
9212 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
9213 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6
9214 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
9215 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7
9229 struct e4_ystorm_roce_resp_conn_ag_ctx {
9233 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
9234 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
9235 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
9236 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1
9237 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
9238 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2
9239 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
9240 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4
9241 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
9242 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6
9244 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
9245 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
9246 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
9247 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1
9248 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
9249 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2
9250 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
9251 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3
9252 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
9253 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4
9254 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
9255 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5
9256 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
9257 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6
9258 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
9259 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7
9273 /* Roce doorbell data */
9281 /* The iwarp storm context of Ystorm */
9282 struct ystorm_iwarp_conn_st_ctx {
9286 /* The iwarp storm context of Pstorm */
9287 struct pstorm_iwarp_conn_st_ctx {
9288 __le32 reserved[36];
9291 /* The iwarp storm context of Xstorm */
9292 struct xstorm_iwarp_conn_st_ctx {
9293 __le32 reserved[48];
9296 struct e4_xstorm_iwarp_conn_ag_ctx {
9300 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9301 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9302 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
9303 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
9304 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1
9305 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT 2
9306 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
9307 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
9308 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
9309 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
9310 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1
9311 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5
9312 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1
9313 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6
9314 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1
9315 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7
9317 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1
9318 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0
9319 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1
9320 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1
9321 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1
9322 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2
9323 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1
9324 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3
9325 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1
9326 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4
9327 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1
9328 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5
9329 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1
9330 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6
9331 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1
9332 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7
9334 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9335 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0
9336 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9337 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2
9338 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9339 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4
9340 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
9341 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
9343 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
9344 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0
9345 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
9346 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2
9347 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
9348 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4
9349 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
9350 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6
9352 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
9353 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0
9354 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3
9355 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2
9356 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3
9357 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4
9358 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3
9359 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6
9361 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3
9362 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0
9363 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3
9364 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2
9365 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
9366 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4
9367 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3
9368 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6
9370 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3
9371 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
9372 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3
9373 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2
9374 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3
9375 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4
9376 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
9377 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
9379 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
9380 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
9381 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
9382 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2
9383 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
9384 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4
9385 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
9386 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6
9387 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9388 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7
9390 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9391 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0
9392 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
9393 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
9394 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
9395 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2
9396 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
9397 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3
9398 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
9399 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4
9400 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
9401 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5
9402 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
9403 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6
9404 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1
9405 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7
9407 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1
9408 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0
9409 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1
9410 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1
9411 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1
9412 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2
9413 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1
9414 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3
9415 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
9416 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4
9417 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1
9418 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5
9419 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1
9420 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6
9421 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1
9422 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7
9424 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1
9425 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0
9426 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
9427 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
9428 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
9429 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
9430 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1
9431 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3
9432 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
9433 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
9434 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_MASK 0x1
9435 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_SHIFT 5
9436 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9437 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6
9438 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1
9439 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7
9441 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
9442 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
9443 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9444 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1
9445 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1
9446 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2
9447 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
9448 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3
9449 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
9450 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4
9451 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
9452 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5
9453 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
9454 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
9455 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1
9456 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7
9458 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1
9459 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0
9460 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1
9461 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1
9462 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
9463 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
9464 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
9465 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
9466 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1
9467 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4
9468 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1
9469 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5
9470 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1
9471 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6
9472 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1
9473 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7
9475 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1
9476 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0
9477 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1
9478 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1
9479 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1
9480 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2
9481 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1
9482 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3
9483 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
9484 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
9485 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1
9486 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5
9487 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
9488 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
9489 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
9490 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
9492 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1
9493 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0
9494 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1
9495 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1
9496 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1
9497 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT 2
9498 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1
9499 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT 3
9500 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
9501 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4
9502 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
9503 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5
9504 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_MASK 0x3
9505 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_SHIFT 6
9509 __le16 sq_comp_cons;
9521 __le32 more_to_send_seq;
9523 __le32 rewinded_snd_max_or_term_opcode;
9525 __le16 irq_prod_via_msdm;
9527 __le16 hq_cons_th_or_mpa_data;
9533 u8 wqe_data_pad_bytes;
9536 u8 irq_prod_via_msem;
9538 u8 max_pkt_pdu_size_lo;
9539 u8 max_pkt_pdu_size_hi;
9542 __le16 e5_reserved4;
9545 __le32 shared_queue_page_addr_lo;
9546 __le32 shared_queue_page_addr_hi;
9553 struct e4_tstorm_iwarp_conn_ag_ctx {
9557 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9558 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9559 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9560 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
9561 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1
9562 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2
9563 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_MASK 0x1
9564 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_SHIFT 3
9565 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
9566 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4
9567 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
9568 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5
9569 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9570 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6
9572 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3
9573 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0
9574 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3
9575 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT 2
9576 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
9577 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
9578 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
9579 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6
9581 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
9582 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0
9583 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
9584 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2
9585 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
9586 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4
9587 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
9588 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6
9590 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3
9591 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_SHIFT 0
9592 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3
9593 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2
9594 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
9595 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4
9596 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1
9597 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5
9598 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1
9599 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT 6
9600 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
9601 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
9603 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
9604 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0
9605 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
9606 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1
9607 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
9608 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2
9609 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
9610 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3
9611 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
9612 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4
9613 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_MASK 0x1
9614 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_SHIFT 5
9615 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1
9616 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6
9617 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9618 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7
9620 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9621 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0
9622 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9623 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
9624 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9625 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
9626 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9627 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
9628 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
9629 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
9630 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1
9631 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5
9632 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
9633 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
9634 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
9635 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
9638 __le32 unaligned_nxt_seq;
9647 __le16 sq_tx_cons_th;
9654 __le32 last_hq_sequence;
9657 /* The iwarp storm context of Tstorm */
9658 struct tstorm_iwarp_conn_st_ctx {
9659 __le32 reserved[60];
9662 /* The iwarp storm context of Mstorm */
9663 struct mstorm_iwarp_conn_st_ctx {
9664 __le32 reserved[32];
9667 /* The iwarp storm context of Ustorm */
9668 struct ustorm_iwarp_conn_st_ctx {
9669 struct regpair reserved[14];
9672 /* iwarp connection context */
9673 struct e4_iwarp_conn_context {
9674 struct ystorm_iwarp_conn_st_ctx ystorm_st_context;
9675 struct regpair ystorm_st_padding[2];
9676 struct pstorm_iwarp_conn_st_ctx pstorm_st_context;
9677 struct regpair pstorm_st_padding[2];
9678 struct xstorm_iwarp_conn_st_ctx xstorm_st_context;
9679 struct e4_xstorm_iwarp_conn_ag_ctx xstorm_ag_context;
9680 struct e4_tstorm_iwarp_conn_ag_ctx tstorm_ag_context;
9681 struct timers_context timer_context;
9682 struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context;
9683 struct tstorm_iwarp_conn_st_ctx tstorm_st_context;
9684 struct regpair tstorm_st_padding[2];
9685 struct mstorm_iwarp_conn_st_ctx mstorm_st_context;
9686 struct ustorm_iwarp_conn_st_ctx ustorm_st_context;
9687 struct regpair ustorm_st_padding[2];
9690 /* iWARP create QP params passed by driver to FW in CreateQP Request Ramrod */
9691 struct iwarp_create_qp_ramrod_data {
9693 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
9694 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0
9695 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
9696 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT 1
9697 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
9698 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2
9699 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
9700 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3
9701 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
9702 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 4
9703 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1
9704 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT 5
9705 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_MASK 0x1
9706 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_SHIFT 6
9707 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x1
9708 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT 7
9711 __le16 sq_num_pages;
9712 __le16 rq_num_pages;
9713 __le32 reserved3[2];
9714 struct regpair qp_handle_for_cqe;
9715 struct rdma_srq_id srq_id;
9716 __le32 cq_cid_for_sq;
9717 __le32 cq_cid_for_rq;
9724 /* iWARP completion queue types */
9725 enum iwarp_eqe_async_opcode {
9726 IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE,
9727 IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED,
9728 IWARP_EVENT_TYPE_ASYNC_MPA_HANDSHAKE_COMPLETE,
9729 IWARP_EVENT_TYPE_ASYNC_CID_CLEANED,
9730 IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED,
9731 IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE,
9732 IWARP_EVENT_TYPE_ASYNC_CQ_OVERFLOW,
9733 IWARP_EVENT_TYPE_ASYNC_SRQ_EMPTY,
9734 IWARP_EVENT_TYPE_ASYNC_SRQ_LIMIT,
9735 MAX_IWARP_EQE_ASYNC_OPCODE
9738 struct iwarp_eqe_data_mpa_async_completion {
9739 __le16 ulp_data_len;
9744 struct iwarp_eqe_data_tcp_async_completion {
9745 __le16 ulp_data_len;
9746 u8 mpa_handshake_mode;
9750 /* iWARP completion queue types */
9751 enum iwarp_eqe_sync_opcode {
9752 IWARP_EVENT_TYPE_TCP_OFFLOAD =
9754 IWARP_EVENT_TYPE_MPA_OFFLOAD,
9755 IWARP_EVENT_TYPE_MPA_OFFLOAD_SEND_RTR,
9756 IWARP_EVENT_TYPE_CREATE_QP,
9757 IWARP_EVENT_TYPE_QUERY_QP,
9758 IWARP_EVENT_TYPE_MODIFY_QP,
9759 IWARP_EVENT_TYPE_DESTROY_QP,
9760 IWARP_EVENT_TYPE_ABORT_TCP_OFFLOAD,
9761 MAX_IWARP_EQE_SYNC_OPCODE
9764 /* iWARP EQE completion status */
9765 enum iwarp_fw_return_code {
9766 IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 6,
9767 IWARP_CONN_ERROR_TCP_CONNECTION_RST,
9768 IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT,
9769 IWARP_CONN_ERROR_MPA_ERROR_REJECT,
9770 IWARP_CONN_ERROR_MPA_NOT_SUPPORTED_VER,
9771 IWARP_CONN_ERROR_MPA_RST,
9772 IWARP_CONN_ERROR_MPA_FIN,
9773 IWARP_CONN_ERROR_MPA_RTR_MISMATCH,
9774 IWARP_CONN_ERROR_MPA_INSUF_IRD,
9775 IWARP_CONN_ERROR_MPA_INVALID_PACKET,
9776 IWARP_CONN_ERROR_MPA_LOCAL_ERROR,
9777 IWARP_CONN_ERROR_MPA_TIMEOUT,
9778 IWARP_CONN_ERROR_MPA_TERMINATE,
9779 IWARP_QP_IN_ERROR_GOOD_CLOSE,
9780 IWARP_QP_IN_ERROR_BAD_CLOSE,
9781 IWARP_EXCEPTION_DETECTED_LLP_CLOSED,
9782 IWARP_EXCEPTION_DETECTED_LLP_RESET,
9783 IWARP_EXCEPTION_DETECTED_IRQ_FULL,
9784 IWARP_EXCEPTION_DETECTED_RQ_EMPTY,
9785 IWARP_EXCEPTION_DETECTED_SRQ_EMPTY,
9786 IWARP_EXCEPTION_DETECTED_SRQ_LIMIT,
9787 IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT,
9788 IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR,
9789 IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW,
9790 IWARP_EXCEPTION_DETECTED_LOCAL_CATASTROPHIC,
9791 IWARP_EXCEPTION_DETECTED_LOCAL_ACCESS_ERROR,
9792 IWARP_EXCEPTION_DETECTED_REMOTE_OPERATION_ERROR,
9793 IWARP_EXCEPTION_DETECTED_TERMINATE_RECEIVED,
9794 MAX_IWARP_FW_RETURN_CODE
9797 /* unaligned opaque data received from LL2 */
9798 struct iwarp_init_func_params {
9803 /* iwarp func init ramrod data */
9804 struct iwarp_init_func_ramrod_data {
9805 struct rdma_init_func_ramrod_data rdma;
9806 struct tcp_init_params tcp;
9807 struct iwarp_init_func_params iwarp;
9810 /* iWARP QP - possible states to transition to */
9811 enum iwarp_modify_qp_new_state_type {
9812 IWARP_MODIFY_QP_STATE_CLOSING = 1,
9813 IWARP_MODIFY_QP_STATE_ERROR = 2,
9814 MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE
9817 /* iwarp modify qp responder ramrod data */
9818 struct iwarp_modify_qp_ramrod_data {
9819 __le16 transition_to_state;
9821 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
9822 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0
9823 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
9824 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 1
9825 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
9826 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 2
9827 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1
9828 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT 3
9829 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
9830 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 4
9831 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
9832 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 5
9833 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x3FF
9834 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT 6
9837 __le32 reserved1[10];
9840 /* MPA params for Enhanced mode */
9841 struct mpa_rq_params {
9846 /* MPA host Address-Len for private data */
9847 struct mpa_ulp_buffer {
9848 struct regpair addr;
9853 /* iWARP MPA offload params common to Basic and Enhanced modes */
9854 struct mpa_outgoing_params {
9858 struct mpa_rq_params out_rq;
9859 struct mpa_ulp_buffer outgoing_ulp_buffer;
9862 /* iWARP MPA offload params passed by driver to FW in MPA Offload Request
9865 struct iwarp_mpa_offload_ramrod_data {
9866 struct mpa_outgoing_params common;
9869 u8 tcp_connect_side;
9871 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK 0x7
9872 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0
9873 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F
9874 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT 3
9876 struct mpa_ulp_buffer incoming_ulp_buffer;
9877 struct regpair async_eqe_output_buf;
9878 struct regpair handle_for_async;
9879 struct regpair shared_queue_addr;
9881 u8 stats_counter_id;
9885 /* iWARP TCP connection offload params passed by driver to FW */
9886 struct iwarp_offload_params {
9887 struct mpa_ulp_buffer incoming_ulp_buffer;
9888 struct regpair async_eqe_output_buf;
9889 struct regpair handle_for_async;
9892 u8 stats_counter_id;
9897 /* iWARP query QP output params */
9898 struct iwarp_query_qp_output_params {
9900 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
9901 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
9902 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
9903 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
9907 /* iWARP query QP ramrod data */
9908 struct iwarp_query_qp_ramrod_data {
9909 struct regpair output_params_addr;
9912 /* iWARP Ramrod Command IDs */
9913 enum iwarp_ramrod_cmd_id {
9914 IWARP_RAMROD_CMD_ID_TCP_OFFLOAD = 11,
9915 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD,
9916 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR,
9917 IWARP_RAMROD_CMD_ID_CREATE_QP,
9918 IWARP_RAMROD_CMD_ID_QUERY_QP,
9919 IWARP_RAMROD_CMD_ID_MODIFY_QP,
9920 IWARP_RAMROD_CMD_ID_DESTROY_QP,
9921 IWARP_RAMROD_CMD_ID_ABORT_TCP_OFFLOAD,
9922 MAX_IWARP_RAMROD_CMD_ID
9925 /* Per PF iWARP retransmit path statistics */
9926 struct iwarp_rxmit_stats_drv {
9927 struct regpair tx_go_to_slow_start_event_cnt;
9928 struct regpair tx_fast_retransmit_event_cnt;
9931 /* iWARP and TCP connection offload params passed by driver to FW in iWARP
9934 struct iwarp_tcp_offload_ramrod_data {
9935 struct tcp_offload_params_opt2 tcp;
9936 struct iwarp_offload_params iwarp;
9939 /* iWARP MPA negotiation types */
9940 enum mpa_negotiation_mode {
9941 MPA_NEGOTIATION_TYPE_BASIC = 1,
9942 MPA_NEGOTIATION_TYPE_ENHANCED = 2,
9943 MAX_MPA_NEGOTIATION_MODE
9946 /* iWARP MPA Enhanced mode RTR types */
9948 MPA_RTR_TYPE_NONE = 0,
9949 MPA_RTR_TYPE_ZERO_SEND = 1,
9950 MPA_RTR_TYPE_ZERO_WRITE = 2,
9951 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE = 3,
9952 MPA_RTR_TYPE_ZERO_READ = 4,
9953 MPA_RTR_TYPE_ZERO_SEND_AND_READ = 5,
9954 MPA_RTR_TYPE_ZERO_WRITE_AND_READ = 6,
9955 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE_AND_READ = 7,
9959 /* unaligned opaque data received from LL2 */
9960 struct unaligned_opaque_data {
9961 __le16 first_mpa_offset;
9962 u8 tcp_payload_offset;
9964 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1
9965 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0
9966 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1
9967 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT 1
9968 #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x3F
9969 #define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT 2
9973 struct e4_mstorm_iwarp_conn_ag_ctx {
9977 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9978 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9979 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9980 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
9981 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3
9982 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2
9983 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9984 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
9985 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9986 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
9988 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1
9989 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0
9990 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9991 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
9992 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9993 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
9994 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9995 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
9996 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9997 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
9998 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9999 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
10000 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1
10001 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6
10002 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
10003 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
10005 __le16 rcq_cons_th;
10010 struct e4_ustorm_iwarp_conn_ag_ctx {
10014 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10015 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10016 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
10017 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
10018 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
10019 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
10020 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
10021 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
10022 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
10023 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
10025 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3
10026 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0
10027 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
10028 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2
10029 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
10030 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4
10031 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
10032 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6
10034 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
10035 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
10036 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
10037 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
10038 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
10039 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
10040 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1
10041 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3
10042 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
10043 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4
10044 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
10045 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5
10046 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
10047 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6
10048 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
10049 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7
10051 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1
10052 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0
10053 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
10054 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1
10055 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
10056 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2
10057 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
10058 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3
10059 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
10060 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4
10061 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
10062 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5
10063 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
10064 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6
10065 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
10066 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7
10079 struct e4_ystorm_iwarp_conn_ag_ctx {
10083 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1
10084 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0
10085 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
10086 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1
10087 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
10088 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2
10089 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
10090 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4
10091 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
10092 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6
10094 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
10095 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
10096 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
10097 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1
10098 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
10099 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2
10100 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
10101 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3
10102 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
10103 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4
10104 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
10105 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5
10106 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
10107 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6
10108 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
10109 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7
10123 /* The fcoe storm context of Ystorm */
10124 struct ystorm_fcoe_conn_st_ctx {
10129 __le16 stat_ram_addr;
10131 __le16 max_fc_payload_len;
10132 __le16 tx_max_fc_pay_len;
10136 struct regpair reserved;
10137 __le16 min_frame_size;
10138 u8 protection_info_flags;
10139 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
10140 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0
10141 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
10142 #define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 1
10143 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F
10144 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT 2
10145 u8 dst_protection_per_mss;
10146 u8 src_protection_per_mss;
10147 u8 ptu_log_page_size;
10149 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
10150 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0
10151 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
10152 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 1
10153 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F
10154 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 2
10158 /* FCoE 16-bits vlan structure */
10159 struct fcoe_vlan_fields {
10161 #define FCOE_VLAN_FIELDS_VID_MASK 0xFFF
10162 #define FCOE_VLAN_FIELDS_VID_SHIFT 0
10163 #define FCOE_VLAN_FIELDS_CLI_MASK 0x1
10164 #define FCOE_VLAN_FIELDS_CLI_SHIFT 12
10165 #define FCOE_VLAN_FIELDS_PRI_MASK 0x7
10166 #define FCOE_VLAN_FIELDS_PRI_SHIFT 13
10169 /* FCoE 16-bits vlan union */
10170 union fcoe_vlan_field_union {
10171 struct fcoe_vlan_fields fields;
10175 /* FCoE 16-bits vlan, vif union */
10176 union fcoe_vlan_vif_field_union {
10177 union fcoe_vlan_field_union vlan;
10181 /* Ethernet context section */
10182 struct pstorm_fcoe_eth_context_section {
10195 union fcoe_vlan_vif_field_union vif_outer_vlan;
10196 __le16 vif_outer_eth_type;
10197 union fcoe_vlan_vif_field_union inner_vlan;
10198 __le16 inner_eth_type;
10201 /* The fcoe storm context of Pstorm */
10202 struct pstorm_fcoe_conn_st_ctx {
10207 __le16 stat_ram_addr;
10209 struct regpair abts_cleanup_addr;
10210 struct pstorm_fcoe_eth_context_section eth;
10215 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1
10216 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0
10217 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1
10218 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1
10219 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
10220 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 2
10221 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
10222 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3
10223 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK 0x1
10224 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_SHIFT 4
10225 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x7
10226 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 5
10231 __le16 rec_rr_tov_val;
10232 u8 q_relative_offset;
10236 /* The fcoe storm context of Xstorm */
10237 struct xstorm_fcoe_conn_st_ctx {
10241 u8 cached_wqes_avail;
10242 __le16 stat_ram_addr;
10244 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1
10245 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0
10246 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
10247 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 1
10248 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1
10249 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT 2
10250 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3
10251 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3
10252 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7
10253 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 5
10254 u8 cached_wqes_offset;
10259 __le16 num_pages_in_pbl;
10261 struct regpair sq_pbl_addr;
10262 struct regpair sq_curr_page_addr;
10263 struct regpair sq_next_page_addr;
10264 struct regpair xferq_pbl_addr;
10265 struct regpair xferq_curr_page_addr;
10266 struct regpair xferq_next_page_addr;
10267 struct regpair respq_pbl_addr;
10268 struct regpair respq_curr_page_addr;
10269 struct regpair respq_next_page_addr;
10271 __le16 tx_max_fc_pay_len;
10272 __le16 max_fc_payload_len;
10273 __le16 min_frame_size;
10274 __le16 sq_pbl_next_index;
10275 __le16 respq_pbl_next_index;
10276 u8 fcp_cmd_byte_credit;
10277 u8 fcp_rsp_byte_credit;
10278 __le16 protection_info;
10279 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1
10280 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0
10281 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
10282 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 1
10283 #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
10284 #define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 2
10285 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1
10286 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3
10287 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF
10288 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT 4
10289 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF
10290 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8
10291 __le16 xferq_pbl_next_index;
10294 u8 fcp_xfer_byte_credit;
10296 struct fcoe_wqe cached_wqes[16];
10299 struct e4_xstorm_fcoe_conn_ag_ctx {
10303 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10304 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10305 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1
10306 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1
10307 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1
10308 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2
10309 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
10310 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
10311 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1
10312 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4
10313 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1
10314 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5
10315 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1
10316 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6
10317 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1
10318 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7
10320 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1
10321 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0
10322 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1
10323 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1
10324 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1
10325 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2
10326 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1
10327 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3
10328 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1
10329 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4
10330 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1
10331 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5
10332 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1
10333 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6
10334 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1
10335 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7
10337 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10338 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0
10339 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10340 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2
10341 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10342 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4
10343 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
10344 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6
10346 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
10347 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0
10348 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
10349 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2
10350 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
10351 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4
10352 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
10353 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6
10355 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
10356 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0
10357 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
10358 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2
10359 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
10360 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4
10361 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3
10362 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6
10364 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3
10365 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0
10366 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3
10367 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2
10368 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3
10369 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4
10370 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3
10371 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6
10373 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3
10374 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0
10375 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3
10376 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2
10377 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3
10378 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4
10379 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3
10380 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6
10382 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
10383 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
10384 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3
10385 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2
10386 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
10387 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
10388 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10389 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6
10390 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10391 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7
10393 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10394 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0
10395 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
10396 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1
10397 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
10398 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2
10399 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
10400 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3
10401 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
10402 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4
10403 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
10404 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5
10405 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
10406 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6
10407 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
10408 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7
10410 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
10411 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0
10412 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1
10413 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1
10414 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1
10415 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2
10416 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1
10417 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3
10418 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1
10419 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4
10420 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1
10421 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5
10422 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1
10423 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6
10424 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1
10425 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7
10427 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1
10428 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0
10429 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
10430 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1
10431 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
10432 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
10433 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1
10434 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3
10435 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
10436 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
10437 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1
10438 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5
10439 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1
10440 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6
10441 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1
10442 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7
10444 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1
10445 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0
10446 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1
10447 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1
10448 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1
10449 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2
10450 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
10451 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3
10452 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
10453 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4
10454 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
10455 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5
10456 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
10457 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
10458 #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1
10459 #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7
10461 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1
10462 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0
10463 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1
10464 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1
10465 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
10466 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
10467 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
10468 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
10469 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1
10470 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4
10471 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1
10472 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5
10473 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1
10474 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6
10475 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1
10476 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7
10478 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1
10479 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0
10480 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1
10481 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1
10482 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
10483 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
10484 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
10485 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
10486 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
10487 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
10488 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
10489 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
10490 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
10491 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
10492 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
10493 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
10495 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1
10496 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0
10497 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1
10498 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1
10499 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1
10500 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2
10501 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1
10502 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3
10503 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1
10504 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4
10505 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1
10506 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5
10507 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3
10508 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6
10510 __le16 physical_q0;
10536 /* The fcoe storm context of Ustorm */
10537 struct ustorm_fcoe_conn_st_ctx {
10538 struct regpair respq_pbl_addr;
10539 __le16 num_pages_in_pbl;
10540 u8 ptu_log_page_size;
10546 struct e4_tstorm_fcoe_conn_ag_ctx {
10550 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10551 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10552 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10553 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
10554 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1
10555 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2
10556 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1
10557 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3
10558 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1
10559 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4
10560 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1
10561 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5
10562 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3
10563 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6
10565 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
10566 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0
10567 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10568 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2
10569 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
10570 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4
10571 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
10572 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6
10574 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
10575 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0
10576 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
10577 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2
10578 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
10579 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4
10580 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
10581 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6
10583 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
10584 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0
10585 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
10586 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2
10587 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1
10588 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4
10589 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
10590 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5
10591 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10592 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6
10593 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
10594 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
10596 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
10597 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0
10598 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
10599 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1
10600 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
10601 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2
10602 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
10603 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3
10604 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
10605 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4
10606 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
10607 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5
10608 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
10609 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6
10610 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10611 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
10613 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10614 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
10615 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10616 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
10617 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10618 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
10619 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10620 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
10621 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
10622 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
10623 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
10624 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
10625 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
10626 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
10627 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
10628 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
10633 struct e4_ustorm_fcoe_conn_ag_ctx {
10637 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10638 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10639 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10640 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
10641 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10642 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
10643 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10644 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
10645 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10646 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
10648 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
10649 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0
10650 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
10651 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2
10652 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
10653 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4
10654 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
10655 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6
10657 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10658 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10659 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10660 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
10661 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10662 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
10663 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
10664 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3
10665 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
10666 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4
10667 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
10668 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5
10669 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
10670 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6
10671 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10672 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7
10674 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10675 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
10676 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10677 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1
10678 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10679 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2
10680 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10681 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3
10682 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
10683 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4
10684 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
10685 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5
10686 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
10687 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6
10688 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
10689 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7
10702 /* The fcoe storm context of Tstorm */
10703 struct tstorm_fcoe_conn_st_ctx {
10704 __le16 stat_ram_addr;
10705 __le16 rx_max_fc_payload_len;
10706 __le16 e_d_tov_val;
10708 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1
10709 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0
10710 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1
10711 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1
10712 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F
10713 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT 2
10714 u8 timers_cleanup_invocation_cnt;
10715 __le32 reserved1[2];
10716 __le32 dst_mac_address_bytes_0_to_3;
10717 __le16 dst_mac_address_bytes_4_to_5;
10718 __le16 ramrod_echo;
10720 #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3
10721 #define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0
10722 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F
10723 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 2
10724 u8 cq_relative_offset;
10725 u8 cmdq_relative_offset;
10726 u8 bdq_resource_id;
10730 struct e4_mstorm_fcoe_conn_ag_ctx {
10734 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10735 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10736 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10737 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
10738 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10739 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
10740 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10741 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
10742 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10743 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
10745 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10746 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10747 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10748 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
10749 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10750 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
10751 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10752 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
10753 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10754 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
10755 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10756 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
10757 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10758 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
10759 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10760 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
10767 /* Fast path part of the fcoe storm context of Mstorm */
10768 struct fcoe_mstorm_fcoe_conn_st_ctx_fp {
10772 u8 protection_info;
10773 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1
10774 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0
10775 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1
10776 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT 1
10777 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK 0x3F
10778 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT 2
10779 u8 q_relative_offset;
10783 /* Non fast path part of the fcoe storm context of Mstorm */
10784 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp {
10786 __le16 stat_ram_addr;
10787 __le16 num_pages_in_pbl;
10788 u8 ptu_log_page_size;
10790 __le16 unsolicited_cq_count;
10792 u8 bdq_resource_id;
10794 struct regpair xferq_pbl_addr;
10795 struct regpair reserved1;
10796 struct regpair reserved2[3];
10799 /* The fcoe storm context of Mstorm */
10800 struct mstorm_fcoe_conn_st_ctx {
10801 struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp;
10802 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp;
10805 /* fcoe connection context */
10806 struct e4_fcoe_conn_context {
10807 struct ystorm_fcoe_conn_st_ctx ystorm_st_context;
10808 struct pstorm_fcoe_conn_st_ctx pstorm_st_context;
10809 struct regpair pstorm_st_padding[2];
10810 struct xstorm_fcoe_conn_st_ctx xstorm_st_context;
10811 struct e4_xstorm_fcoe_conn_ag_ctx xstorm_ag_context;
10812 struct regpair xstorm_ag_padding[6];
10813 struct ustorm_fcoe_conn_st_ctx ustorm_st_context;
10814 struct regpair ustorm_st_padding[2];
10815 struct e4_tstorm_fcoe_conn_ag_ctx tstorm_ag_context;
10816 struct regpair tstorm_ag_padding[2];
10817 struct timers_context timer_context;
10818 struct e4_ustorm_fcoe_conn_ag_ctx ustorm_ag_context;
10819 struct tstorm_fcoe_conn_st_ctx tstorm_st_context;
10820 struct e4_mstorm_fcoe_conn_ag_ctx mstorm_ag_context;
10821 struct mstorm_fcoe_conn_st_ctx mstorm_st_context;
10824 /* FCoE connection offload params passed by driver to FW in FCoE offload
10827 struct fcoe_conn_offload_ramrod_params {
10828 struct fcoe_conn_offload_ramrod_data offload_ramrod_data;
10831 /* FCoE connection terminate params passed by driver to FW in FCoE terminate
10834 struct fcoe_conn_terminate_ramrod_params {
10835 struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data;
10838 /* FCoE event type */
10839 enum fcoe_event_type {
10840 FCOE_EVENT_INIT_FUNC,
10841 FCOE_EVENT_DESTROY_FUNC,
10842 FCOE_EVENT_STAT_FUNC,
10843 FCOE_EVENT_OFFLOAD_CONN,
10844 FCOE_EVENT_TERMINATE_CONN,
10846 MAX_FCOE_EVENT_TYPE
10849 /* FCoE init params passed by driver to FW in FCoE init ramrod */
10850 struct fcoe_init_ramrod_params {
10851 struct fcoe_init_func_ramrod_data init_ramrod_data;
10854 /* FCoE ramrod Command IDs */
10855 enum fcoe_ramrod_cmd_id {
10856 FCOE_RAMROD_CMD_ID_INIT_FUNC,
10857 FCOE_RAMROD_CMD_ID_DESTROY_FUNC,
10858 FCOE_RAMROD_CMD_ID_STAT_FUNC,
10859 FCOE_RAMROD_CMD_ID_OFFLOAD_CONN,
10860 FCOE_RAMROD_CMD_ID_TERMINATE_CONN,
10861 MAX_FCOE_RAMROD_CMD_ID
10864 /* FCoE statistics params buffer passed by driver to FW in FCoE statistics
10867 struct fcoe_stat_ramrod_params {
10868 struct fcoe_stat_ramrod_data stat_ramrod_data;
10871 struct e4_ystorm_fcoe_conn_ag_ctx {
10875 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10876 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10877 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10878 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1
10879 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10880 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2
10881 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10882 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4
10883 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10884 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6
10886 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10887 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10888 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10889 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1
10890 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10891 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2
10892 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10893 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3
10894 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10895 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4
10896 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10897 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5
10898 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10899 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6
10900 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10901 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7
10915 /* The iscsi storm connection context of Ystorm */
10916 struct ystorm_iscsi_conn_st_ctx {
10917 __le32 reserved[8];
10920 /* Combined iSCSI and TCP storm connection of Pstorm */
10921 struct pstorm_iscsi_tcp_conn_st_ctx {
10926 /* The combined tcp and iscsi storm context of Xstorm */
10927 struct xstorm_iscsi_tcp_conn_st_ctx {
10928 __le32 reserved_tcp[4];
10929 __le32 reserved_iscsi[44];
10932 struct e4_xstorm_iscsi_conn_ag_ctx {
10936 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10937 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10938 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
10939 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1
10940 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1
10941 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT 2
10942 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
10943 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
10944 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
10945 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
10946 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1
10947 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT 5
10948 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1
10949 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT 6
10950 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1
10951 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT 7
10953 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1
10954 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0
10955 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1
10956 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT 1
10957 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1
10958 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT 2
10959 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1
10960 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3
10961 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1
10962 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT 4
10963 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1
10964 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT 5
10965 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1
10966 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT 6
10967 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1
10968 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT 7
10970 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10971 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0
10972 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10973 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 2
10974 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10975 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 4
10976 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
10977 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6
10979 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10980 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0
10981 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10982 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 2
10983 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10984 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 4
10985 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
10986 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 6
10988 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
10989 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0
10990 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3
10991 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT 2
10992 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
10993 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 4
10994 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3
10995 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT 6
10997 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3
10998 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0
10999 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3
11000 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT 2
11001 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3
11002 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT 4
11003 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3
11004 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT 6
11006 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3
11007 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0
11008 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3
11009 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT 2
11010 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3
11011 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT 4
11012 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
11013 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT 6
11015 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3
11016 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0
11017 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3
11018 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT 2
11019 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3
11020 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT 4
11021 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
11022 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 6
11023 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
11024 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 7
11026 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
11027 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0
11028 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
11029 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1
11030 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
11031 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 2
11032 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
11033 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 3
11034 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
11035 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 4
11036 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
11037 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 5
11038 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
11039 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 6
11040 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1
11041 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT 7
11043 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
11044 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0
11045 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1
11046 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT 1
11047 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1
11048 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT 2
11049 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1
11050 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT 3
11051 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1
11052 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT 4
11053 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1
11054 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5
11055 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1
11056 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT 6
11057 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1
11058 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT 7
11060 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1
11061 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0
11062 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
11063 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1
11064 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1
11065 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT 2
11066 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1
11067 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT 3
11068 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
11069 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
11070 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1
11071 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT 5
11072 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
11073 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 6
11074 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1
11075 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT 7
11077 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
11078 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
11079 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
11080 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 1
11081 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1
11082 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT 2
11083 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
11084 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 3
11085 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
11086 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 4
11087 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
11088 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 5
11089 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
11090 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
11091 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1
11092 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT 7
11094 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1
11095 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0
11096 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1
11097 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT 1
11098 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
11099 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
11100 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
11101 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
11102 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1
11103 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT 4
11104 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1
11105 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT 5
11106 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1
11107 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT 6
11108 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1
11109 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT 7
11111 #define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1
11112 #define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0
11113 #define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1
11114 #define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT 1
11115 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
11116 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
11117 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
11118 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
11119 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
11120 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
11121 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
11122 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
11123 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
11124 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
11125 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
11126 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
11128 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1
11129 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0
11130 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1
11131 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT 1
11132 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1
11133 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT 2
11134 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1
11135 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT 3
11136 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1
11137 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT 4
11138 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1
11139 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT 5
11140 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3
11141 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT 6
11143 __le16 physical_q0;
11144 __le16 physical_q1;
11145 __le16 dummy_dorq_var;
11149 __le16 slow_io_total_data_tx_update;
11157 __le32 more_to_send_seq;
11160 __le32 hq_scan_next_relevant_ack;
11166 __le32 bytes_to_next_pdu;
11181 __le32 exp_stat_sn;
11182 __le32 ongoing_fast_rxmit_seq;
11189 struct e4_tstorm_iscsi_conn_ag_ctx {
11193 #define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
11194 #define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
11195 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
11196 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
11197 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1
11198 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT 2
11199 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1
11200 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT 3
11201 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
11202 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4
11203 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1
11204 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT 5
11205 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
11206 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 6
11208 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3
11209 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0
11210 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3
11211 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT 2
11212 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
11213 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4
11214 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
11215 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 6
11217 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
11218 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0
11219 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
11220 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 2
11221 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
11222 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 4
11223 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
11224 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 6
11226 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
11227 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
11228 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_MASK 0x3
11229 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_SHIFT 2
11230 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
11231 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4
11232 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1
11233 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT 5
11234 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1
11235 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT 6
11236 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
11237 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7
11239 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
11240 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0
11241 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
11242 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 1
11243 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
11244 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 2
11245 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
11246 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 3
11247 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
11248 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4
11249 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
11250 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5
11251 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_MASK 0x1
11252 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_SHIFT 6
11253 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
11254 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
11256 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
11257 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
11258 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
11259 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
11260 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
11261 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
11262 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
11263 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
11264 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
11265 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
11266 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
11267 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
11268 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
11269 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
11270 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
11271 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
11274 __le32 rx_tcp_checksum_err_cnt;
11281 u8 cid_offload_cnt;
11286 struct e4_ustorm_iscsi_conn_ag_ctx {
11290 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
11291 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
11292 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
11293 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
11294 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
11295 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
11296 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
11297 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
11298 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
11299 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
11301 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3
11302 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0
11303 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
11304 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 2
11305 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
11306 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 4
11307 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
11308 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 6
11310 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
11311 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
11312 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
11313 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
11314 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
11315 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
11316 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1
11317 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT 3
11318 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
11319 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 4
11320 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
11321 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 5
11322 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
11323 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 6
11324 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
11325 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7
11327 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
11328 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
11329 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
11330 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1
11331 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
11332 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2
11333 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
11334 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3
11335 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
11336 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4
11337 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
11338 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5
11339 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
11340 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6
11341 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
11342 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7
11355 /* The iscsi storm connection context of Tstorm */
11356 struct tstorm_iscsi_conn_st_ctx {
11357 __le32 reserved[44];
11360 struct e4_mstorm_iscsi_conn_ag_ctx {
11364 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
11365 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
11366 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
11367 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
11368 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
11369 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
11370 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
11371 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
11372 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
11373 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
11375 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
11376 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
11377 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
11378 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
11379 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
11380 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
11381 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
11382 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
11383 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
11384 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
11385 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
11386 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
11387 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
11388 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
11389 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
11390 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
11397 /* Combined iSCSI and TCP storm connection of Mstorm */
11398 struct mstorm_iscsi_tcp_conn_st_ctx {
11399 __le32 reserved_tcp[20];
11400 __le32 reserved_iscsi[12];
11403 /* The iscsi storm context of Ustorm */
11404 struct ustorm_iscsi_conn_st_ctx {
11405 __le32 reserved[52];
11408 /* iscsi connection context */
11409 struct e4_iscsi_conn_context {
11410 struct ystorm_iscsi_conn_st_ctx ystorm_st_context;
11411 struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context;
11412 struct regpair pstorm_st_padding[2];
11413 struct pb_context xpb2_context;
11414 struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context;
11415 struct regpair xstorm_st_padding[2];
11416 struct e4_xstorm_iscsi_conn_ag_ctx xstorm_ag_context;
11417 struct e4_tstorm_iscsi_conn_ag_ctx tstorm_ag_context;
11418 struct regpair tstorm_ag_padding[2];
11419 struct timers_context timer_context;
11420 struct e4_ustorm_iscsi_conn_ag_ctx ustorm_ag_context;
11421 struct pb_context upb_context;
11422 struct tstorm_iscsi_conn_st_ctx tstorm_st_context;
11423 struct regpair tstorm_st_padding[2];
11424 struct e4_mstorm_iscsi_conn_ag_ctx mstorm_ag_context;
11425 struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context;
11426 struct ustorm_iscsi_conn_st_ctx ustorm_st_context;
11429 /* iSCSI init params passed by driver to FW in iSCSI init ramrod */
11430 struct iscsi_init_ramrod_params {
11431 struct iscsi_spe_func_init iscsi_init_spe;
11432 struct tcp_init_params tcp_init;
11435 struct e4_ystorm_iscsi_conn_ag_ctx {
11439 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
11440 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
11441 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
11442 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1
11443 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
11444 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2
11445 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
11446 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4
11447 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
11448 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6
11450 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
11451 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
11452 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
11453 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1
11454 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
11455 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2
11456 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
11457 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3
11458 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
11459 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4
11460 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
11461 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5
11462 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
11463 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6
11464 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
11465 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7
11479 #define MFW_TRACE_SIGNATURE 0x25071946
11481 /* The trace in the buffer */
11482 #define MFW_TRACE_EVENTID_MASK 0x00ffff
11483 #define MFW_TRACE_PRM_SIZE_MASK 0x0f0000
11484 #define MFW_TRACE_PRM_SIZE_OFFSET 16
11485 #define MFW_TRACE_ENTRY_SIZE 3
11488 u32 signature; /* Help to identify that the trace is valid */
11489 u32 size; /* the size of the trace buffer in bytes */
11490 u32 curr_level; /* 2 - all will be written to the buffer
11491 * 1 - debug trace will not be written
11492 * 0 - just errors will be written to the buffer
11494 u32 modules_mask[2]; /* a bit per module, 1 means write it, 0 means
11498 /* Warning: the following pointers are assumed to be 32bits as they are
11499 * used only in the MFW.
11501 u32 trace_prod; /* The next trace will be written to this offset */
11502 u32 trace_oldest; /* The oldest valid trace starts at this offset
11503 * (usually very close after the current producer).
11507 #define VF_MAX_STATIC 192
11509 #define MCP_GLOB_PATH_MAX 2
11510 #define MCP_PORT_MAX 2
11511 #define MCP_GLOB_PORT_MAX 4
11512 #define MCP_GLOB_FUNC_MAX 16
11514 typedef u32 offsize_t; /* In DWORDS !!! */
11515 /* Offset from the beginning of the MCP scratchpad */
11516 #define OFFSIZE_OFFSET_SHIFT 0
11517 #define OFFSIZE_OFFSET_MASK 0x0000ffff
11518 /* Size of specific element (not the whole array if any) */
11519 #define OFFSIZE_SIZE_SHIFT 16
11520 #define OFFSIZE_SIZE_MASK 0xffff0000
11522 #define SECTION_OFFSET(_offsize) ((((_offsize & \
11523 OFFSIZE_OFFSET_MASK) >> \
11524 OFFSIZE_OFFSET_SHIFT) << 2))
11526 #define QED_SECTION_SIZE(_offsize) (((_offsize & \
11527 OFFSIZE_SIZE_MASK) >> \
11528 OFFSIZE_SIZE_SHIFT) << 2)
11530 #define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + \
11531 SECTION_OFFSET(_offsize) + \
11532 (QED_SECTION_SIZE(_offsize) * idx))
11534 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \
11535 (_pub_base + offsetof(struct mcp_public_data, sections[_section]))
11537 /* PHY configuration */
11538 struct eth_phy_cfg {
11540 #define ETH_SPEED_AUTONEG 0x0
11541 #define ETH_SPEED_SMARTLINQ 0x8
11544 #define ETH_PAUSE_NONE 0x0
11545 #define ETH_PAUSE_AUTONEG 0x1
11546 #define ETH_PAUSE_RX 0x2
11547 #define ETH_PAUSE_TX 0x4
11552 #define ETH_LOOPBACK_NONE 0x0
11553 #define ETH_LOOPBACK_INT_PHY 0x1
11554 #define ETH_LOOPBACK_EXT_PHY 0x2
11555 #define ETH_LOOPBACK_EXT 0x3
11556 #define ETH_LOOPBACK_MAC 0x4
11557 #define ETH_LOOPBACK_CNIG_AH_ONLY_0123 0x5
11558 #define ETH_LOOPBACK_CNIG_AH_ONLY_2301 0x6
11559 #define ETH_LOOPBACK_PCS_AH_ONLY 0x7
11560 #define ETH_LOOPBACK_REVERSE_MAC_AH_ONLY 0x8
11561 #define ETH_LOOPBACK_INT_PHY_FEA_AH_ONLY 0x9
11564 #define EEE_CFG_EEE_ENABLED BIT(0)
11565 #define EEE_CFG_TX_LPI BIT(1)
11566 #define EEE_CFG_ADV_SPEED_1G BIT(2)
11567 #define EEE_CFG_ADV_SPEED_10G BIT(3)
11568 #define EEE_TX_TIMER_USEC_MASK 0xfffffff0
11569 #define EEE_TX_TIMER_USEC_OFFSET 4
11570 #define EEE_TX_TIMER_USEC_BALANCED_TIME 0xa00
11571 #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME 0x100
11572 #define EEE_TX_TIMER_USEC_LATENCY_TIME 0x6000
11577 #define FEC_FORCE_MODE_MASK 0x000000ff
11578 #define FEC_FORCE_MODE_OFFSET 0
11579 #define FEC_FORCE_MODE_NONE 0x00
11580 #define FEC_FORCE_MODE_FIRECODE 0x01
11581 #define FEC_FORCE_MODE_RS 0x02
11582 #define FEC_FORCE_MODE_AUTO 0x07
11583 #define FEC_EXTENDED_MODE_MASK 0xffffff00
11584 #define FEC_EXTENDED_MODE_OFFSET 8
11585 #define ETH_EXT_FEC_NONE 0x00000100
11586 #define ETH_EXT_FEC_10G_NONE 0x00000200
11587 #define ETH_EXT_FEC_10G_BASE_R 0x00000400
11588 #define ETH_EXT_FEC_20G_NONE 0x00000800
11589 #define ETH_EXT_FEC_20G_BASE_R 0x00001000
11590 #define ETH_EXT_FEC_25G_NONE 0x00002000
11591 #define ETH_EXT_FEC_25G_BASE_R 0x00004000
11592 #define ETH_EXT_FEC_25G_RS528 0x00008000
11593 #define ETH_EXT_FEC_40G_NONE 0x00010000
11594 #define ETH_EXT_FEC_40G_BASE_R 0x00020000
11595 #define ETH_EXT_FEC_50G_NONE 0x00040000
11596 #define ETH_EXT_FEC_50G_BASE_R 0x00080000
11597 #define ETH_EXT_FEC_50G_RS528 0x00100000
11598 #define ETH_EXT_FEC_50G_RS544 0x00200000
11599 #define ETH_EXT_FEC_100G_NONE 0x00400000
11600 #define ETH_EXT_FEC_100G_BASE_R 0x00800000
11601 #define ETH_EXT_FEC_100G_RS528 0x01000000
11602 #define ETH_EXT_FEC_100G_RS544 0x02000000
11604 u32 extended_speed;
11605 #define ETH_EXT_SPEED_MASK 0x0000ffff
11606 #define ETH_EXT_SPEED_OFFSET 0
11607 #define ETH_EXT_SPEED_AN 0x00000001
11608 #define ETH_EXT_SPEED_1G 0x00000002
11609 #define ETH_EXT_SPEED_10G 0x00000004
11610 #define ETH_EXT_SPEED_20G 0x00000008
11611 #define ETH_EXT_SPEED_25G 0x00000010
11612 #define ETH_EXT_SPEED_40G 0x00000020
11613 #define ETH_EXT_SPEED_50G_BASE_R 0x00000040
11614 #define ETH_EXT_SPEED_50G_BASE_R2 0x00000080
11615 #define ETH_EXT_SPEED_100G_BASE_R2 0x00000100
11616 #define ETH_EXT_SPEED_100G_BASE_R4 0x00000200
11617 #define ETH_EXT_SPEED_100G_BASE_P4 0x00000400
11618 #define ETH_EXT_ADV_SPEED_MASK 0xffff0000
11619 #define ETH_EXT_ADV_SPEED_OFFSET 16
11620 #define ETH_EXT_ADV_SPEED_RESERVED 0x00010000
11621 #define ETH_EXT_ADV_SPEED_1G 0x00020000
11622 #define ETH_EXT_ADV_SPEED_10G 0x00040000
11623 #define ETH_EXT_ADV_SPEED_20G 0x00080000
11624 #define ETH_EXT_ADV_SPEED_25G 0x00100000
11625 #define ETH_EXT_ADV_SPEED_40G 0x00200000
11626 #define ETH_EXT_ADV_SPEED_50G_BASE_R 0x00400000
11627 #define ETH_EXT_ADV_SPEED_50G_BASE_R2 0x00800000
11628 #define ETH_EXT_ADV_SPEED_100G_BASE_R2 0x01000000
11629 #define ETH_EXT_ADV_SPEED_100G_BASE_R4 0x02000000
11630 #define ETH_EXT_ADV_SPEED_100G_BASE_P4 0x04000000
11633 struct port_mf_cfg {
11635 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
11636 #define PORT_MF_CFG_OV_TAG_SHIFT 0
11637 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK
11726 u64 brb_truncate[8];
11727 u64 brb_discard[8];
11730 struct port_stats {
11731 struct brb_stats brb;
11732 struct eth_stats eth;
11735 struct couple_mode_teaming {
11736 u8 port_cmt[MCP_GLOB_PORT_MAX];
11737 #define PORT_CMT_IN_TEAM (1 << 0)
11739 #define PORT_CMT_PORT_ROLE (1 << 1)
11740 #define PORT_CMT_PORT_INACTIVE (0 << 1)
11741 #define PORT_CMT_PORT_ACTIVE (1 << 1)
11743 #define PORT_CMT_TEAM_MASK (1 << 2)
11744 #define PORT_CMT_TEAM0 (0 << 2)
11745 #define PORT_CMT_TEAM1 (1 << 2)
11748 #define LLDP_CHASSIS_ID_STAT_LEN 4
11749 #define LLDP_PORT_ID_STAT_LEN 4
11750 #define DCBX_MAX_APP_PROTOCOL 32
11751 #define MAX_SYSTEM_LLDP_TLV_DATA 32
11754 LLDP_NEAREST_BRIDGE = 0,
11755 LLDP_NEAREST_NON_TPMR_BRIDGE,
11756 LLDP_NEAREST_CUSTOMER_BRIDGE,
11757 LLDP_MAX_LLDP_AGENTS
11760 struct lldp_config_params_s {
11762 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff
11763 #define LLDP_CONFIG_TX_INTERVAL_SHIFT 0
11764 #define LLDP_CONFIG_HOLD_MASK 0x00000f00
11765 #define LLDP_CONFIG_HOLD_SHIFT 8
11766 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000
11767 #define LLDP_CONFIG_MAX_CREDIT_SHIFT 12
11768 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000
11769 #define LLDP_CONFIG_ENABLE_RX_SHIFT 30
11770 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000
11771 #define LLDP_CONFIG_ENABLE_TX_SHIFT 31
11772 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
11773 u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
11776 struct lldp_status_params_s {
11777 u32 prefix_seq_num;
11779 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
11780 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
11781 u32 suffix_seq_num;
11784 struct dcbx_ets_feature {
11786 #define DCBX_ETS_ENABLED_MASK 0x00000001
11787 #define DCBX_ETS_ENABLED_SHIFT 0
11788 #define DCBX_ETS_WILLING_MASK 0x00000002
11789 #define DCBX_ETS_WILLING_SHIFT 1
11790 #define DCBX_ETS_ERROR_MASK 0x00000004
11791 #define DCBX_ETS_ERROR_SHIFT 2
11792 #define DCBX_ETS_CBS_MASK 0x00000008
11793 #define DCBX_ETS_CBS_SHIFT 3
11794 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0
11795 #define DCBX_ETS_MAX_TCS_SHIFT 4
11796 #define DCBX_OOO_TC_MASK 0x00000f00
11797 #define DCBX_OOO_TC_SHIFT 8
11799 #define DCBX_TCP_OOO_TC (4)
11801 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_TCP_OOO_TC + 1)
11802 #define DCBX_CEE_STRICT_PRIORITY 0xf
11805 #define DCBX_ETS_TSA_STRICT 0
11806 #define DCBX_ETS_TSA_CBS 1
11807 #define DCBX_ETS_TSA_ETS 2
11810 #define DCBX_TCP_OOO_TC (4)
11811 #define DCBX_TCP_OOO_K2_4PORT_TC (3)
11813 struct dcbx_app_priority_entry {
11815 #define DCBX_APP_PRI_MAP_MASK 0x000000ff
11816 #define DCBX_APP_PRI_MAP_SHIFT 0
11817 #define DCBX_APP_PRI_0 0x01
11818 #define DCBX_APP_PRI_1 0x02
11819 #define DCBX_APP_PRI_2 0x04
11820 #define DCBX_APP_PRI_3 0x08
11821 #define DCBX_APP_PRI_4 0x10
11822 #define DCBX_APP_PRI_5 0x20
11823 #define DCBX_APP_PRI_6 0x40
11824 #define DCBX_APP_PRI_7 0x80
11825 #define DCBX_APP_SF_MASK 0x00000300
11826 #define DCBX_APP_SF_SHIFT 8
11827 #define DCBX_APP_SF_ETHTYPE 0
11828 #define DCBX_APP_SF_PORT 1
11829 #define DCBX_APP_SF_IEEE_MASK 0x0000f000
11830 #define DCBX_APP_SF_IEEE_SHIFT 12
11831 #define DCBX_APP_SF_IEEE_RESERVED 0
11832 #define DCBX_APP_SF_IEEE_ETHTYPE 1
11833 #define DCBX_APP_SF_IEEE_TCP_PORT 2
11834 #define DCBX_APP_SF_IEEE_UDP_PORT 3
11835 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4
11837 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
11838 #define DCBX_APP_PROTOCOL_ID_SHIFT 16
11841 struct dcbx_app_priority_feature {
11843 #define DCBX_APP_ENABLED_MASK 0x00000001
11844 #define DCBX_APP_ENABLED_SHIFT 0
11845 #define DCBX_APP_WILLING_MASK 0x00000002
11846 #define DCBX_APP_WILLING_SHIFT 1
11847 #define DCBX_APP_ERROR_MASK 0x00000004
11848 #define DCBX_APP_ERROR_SHIFT 2
11849 #define DCBX_APP_MAX_TCS_MASK 0x0000f000
11850 #define DCBX_APP_MAX_TCS_SHIFT 12
11851 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
11852 #define DCBX_APP_NUM_ENTRIES_SHIFT 16
11853 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
11856 struct dcbx_features {
11857 struct dcbx_ets_feature ets;
11859 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff
11860 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0
11861 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01
11862 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02
11863 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04
11864 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08
11865 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10
11866 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20
11867 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40
11868 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80
11870 #define DCBX_PFC_FLAGS_MASK 0x0000ff00
11871 #define DCBX_PFC_FLAGS_SHIFT 8
11872 #define DCBX_PFC_CAPS_MASK 0x00000f00
11873 #define DCBX_PFC_CAPS_SHIFT 8
11874 #define DCBX_PFC_MBC_MASK 0x00004000
11875 #define DCBX_PFC_MBC_SHIFT 14
11876 #define DCBX_PFC_WILLING_MASK 0x00008000
11877 #define DCBX_PFC_WILLING_SHIFT 15
11878 #define DCBX_PFC_ENABLED_MASK 0x00010000
11879 #define DCBX_PFC_ENABLED_SHIFT 16
11880 #define DCBX_PFC_ERROR_MASK 0x00020000
11881 #define DCBX_PFC_ERROR_SHIFT 17
11883 struct dcbx_app_priority_feature app;
11886 struct dcbx_local_params {
11888 #define DCBX_CONFIG_VERSION_MASK 0x00000007
11889 #define DCBX_CONFIG_VERSION_SHIFT 0
11890 #define DCBX_CONFIG_VERSION_DISABLED 0
11891 #define DCBX_CONFIG_VERSION_IEEE 1
11892 #define DCBX_CONFIG_VERSION_CEE 2
11893 #define DCBX_CONFIG_VERSION_STATIC 4
11896 struct dcbx_features features;
11900 u32 prefix_seq_num;
11902 struct dcbx_features features;
11903 u32 suffix_seq_num;
11906 struct lldp_system_tlvs_buffer_s {
11909 u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
11912 struct dcb_dscp_map {
11914 #define DCB_DSCP_ENABLE_MASK 0x1
11915 #define DCB_DSCP_ENABLE_SHIFT 0
11916 #define DCB_DSCP_ENABLE 1
11917 u32 dscp_pri_map[8];
11920 struct public_global {
11927 u32 debug_mb_offset;
11928 u32 phymod_dbg_mb_offset;
11929 struct couple_mode_teaming cmt;
11930 s32 internal_temperature;
11932 u32 running_bundle_id;
11933 s32 external_temperature;
11946 struct public_path {
11947 struct fw_flr_mb flr_mb;
11948 u32 mcp_vf_disabled[VF_MAX_STATIC / 32];
11951 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff
11952 #define PROCESS_KILL_COUNTER_SHIFT 0
11953 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
11954 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16
11955 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
11958 struct public_port {
11962 #define LINK_STATUS_LINK_UP 0x00000001
11963 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
11964 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1)
11965 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1)
11966 #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1)
11967 #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1)
11968 #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1)
11969 #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1)
11970 #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1)
11971 #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1)
11972 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
11973 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
11974 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
11975 #define LINK_STATUS_PFC_ENABLED 0x00000100
11976 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
11977 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
11978 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
11979 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
11980 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
11981 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
11982 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
11983 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
11984 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000c0000
11985 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
11986 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18)
11987 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18)
11988 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18)
11989 #define LINK_STATUS_SFP_TX_FAULT 0x00100000
11990 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
11991 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
11992 #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000
11993 #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000
11994 #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000
11995 #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000
11997 #define LINK_STATUS_FEC_MODE_MASK 0x38000000
11998 #define LINK_STATUS_FEC_MODE_NONE (0 << 27)
11999 #define LINK_STATUS_FEC_MODE_FIRECODE_CL74 (1 << 27)
12000 #define LINK_STATUS_FEC_MODE_RS_CL91 (2 << 27)
12003 u32 ext_phy_fw_version;
12004 u32 drv_phy_cfg_addr;
12008 u32 stat_nig_timer;
12010 struct port_mf_cfg port_mf_config;
12011 struct port_stats stats;
12014 #define MEDIA_UNSPECIFIED 0x0
12015 #define MEDIA_SFPP_10G_FIBER 0x1
12016 #define MEDIA_XFP_FIBER 0x2
12017 #define MEDIA_DA_TWINAX 0x3
12018 #define MEDIA_BASE_T 0x4
12019 #define MEDIA_SFP_1G_FIBER 0x5
12020 #define MEDIA_MODULE_FIBER 0x6
12021 #define MEDIA_KR 0xf0
12022 #define MEDIA_NOT_PRESENT 0xff
12025 u32 link_change_count;
12027 struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS];
12028 struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];
12029 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
12031 /* DCBX related MIB */
12032 struct dcbx_local_params local_admin_dcbx_mib;
12033 struct dcbx_mib remote_dcbx_mib;
12034 struct dcbx_mib operational_dcbx_mib;
12038 u32 transceiver_data;
12039 #define ETH_TRANSCEIVER_STATE_MASK 0x000000ff
12040 #define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000
12041 #define ETH_TRANSCEIVER_STATE_OFFSET 0x00000000
12042 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
12043 #define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001
12044 #define ETH_TRANSCEIVER_STATE_VALID 0x00000003
12045 #define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008
12046 #define ETH_TRANSCEIVER_TYPE_MASK 0x0000ff00
12047 #define ETH_TRANSCEIVER_TYPE_OFFSET 0x8
12048 #define ETH_TRANSCEIVER_TYPE_NONE 0x00
12049 #define ETH_TRANSCEIVER_TYPE_UNKNOWN 0xff
12050 #define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01
12051 #define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02
12052 #define ETH_TRANSCEIVER_TYPE_1G_LX 0x03
12053 #define ETH_TRANSCEIVER_TYPE_1G_SX 0x04
12054 #define ETH_TRANSCEIVER_TYPE_10G_SR 0x05
12055 #define ETH_TRANSCEIVER_TYPE_10G_LR 0x06
12056 #define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07
12057 #define ETH_TRANSCEIVER_TYPE_10G_ER 0x08
12058 #define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09
12059 #define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a
12060 #define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b
12061 #define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c
12062 #define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d
12063 #define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e
12064 #define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f
12065 #define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10
12066 #define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11
12067 #define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12
12068 #define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13
12069 #define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14
12070 #define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15
12071 #define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16
12072 #define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17
12073 #define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18
12074 #define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19
12075 #define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a
12076 #define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b
12077 #define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c
12078 #define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d
12079 #define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e
12080 #define ETH_TRANSCEIVER_TYPE_4x10G 0x1f
12081 #define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20
12082 #define ETH_TRANSCEIVER_TYPE_1000BASET 0x21
12083 #define ETH_TRANSCEIVER_TYPE_10G_BASET 0x22
12084 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30
12085 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31
12086 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32
12087 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33
12088 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34
12089 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35
12090 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36
12091 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_SR 0x37
12092 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_25G_LR 0x38
12093 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_SR 0x39
12094 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_1G_10G_LR 0x3a
12098 u32 wol_pkt_details;
12099 struct dcb_dscp_map dcb_dscp_map;
12102 #define EEE_ACTIVE_BIT BIT(0)
12103 #define EEE_LD_ADV_STATUS_MASK 0x000000f0
12104 #define EEE_LD_ADV_STATUS_OFFSET 4
12105 #define EEE_1G_ADV BIT(1)
12106 #define EEE_10G_ADV BIT(2)
12107 #define EEE_LP_ADV_STATUS_MASK 0x00000f00
12108 #define EEE_LP_ADV_STATUS_OFFSET 8
12109 #define EEE_SUPPORTED_SPEED_MASK 0x0000f000
12110 #define EEE_SUPPORTED_SPEED_OFFSET 12
12111 #define EEE_1G_SUPPORTED BIT(1)
12112 #define EEE_10G_SUPPORTED BIT(2)
12115 #define EEE_REMOTE_TW_TX_MASK 0x0000ffff
12116 #define EEE_REMOTE_TW_TX_OFFSET 0
12117 #define EEE_REMOTE_TW_RX_MASK 0xffff0000
12118 #define EEE_REMOTE_TW_RX_OFFSET 16
12122 #define OEM_CFG_CHANNEL_TYPE_MASK 0x00000003
12123 #define OEM_CFG_CHANNEL_TYPE_OFFSET 0
12124 #define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION 0x1
12125 #define OEM_CFG_CHANNEL_TYPE_STAGGED 0x2
12126 #define OEM_CFG_SCHED_TYPE_MASK 0x0000000C
12127 #define OEM_CFG_SCHED_TYPE_OFFSET 2
12128 #define OEM_CFG_SCHED_TYPE_ETS 0x1
12129 #define OEM_CFG_SCHED_TYPE_VNIC_BW 0x2
12132 struct public_func {
12140 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
12141 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
12142 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001
12144 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
12145 #define FUNC_MF_CFG_PROTOCOL_SHIFT 4
12146 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
12147 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
12148 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020
12149 #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030
12150 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030
12152 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
12153 #define FUNC_MF_CFG_MIN_BW_SHIFT 8
12154 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
12155 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
12156 #define FUNC_MF_CFG_MAX_BW_SHIFT 16
12157 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
12160 #define FUNC_STATUS_VIRTUAL_LINK_UP 0x00000001
12163 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
12164 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
12165 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
12167 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
12169 u32 fcoe_wwn_port_name_upper;
12170 u32 fcoe_wwn_port_name_lower;
12172 u32 fcoe_wwn_node_name_upper;
12173 u32 fcoe_wwn_node_name_lower;
12176 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
12177 #define FUNC_MF_CFG_OV_STAG_SHIFT 0
12178 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK
12184 u32 driver_last_activity_ts;
12186 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32];
12189 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
12190 #define DRV_ID_PDA_COMP_VER_SHIFT 0
12192 #define LOAD_REQ_HSI_VERSION 2
12193 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
12194 #define DRV_ID_MCP_HSI_VER_SHIFT 16
12195 #define DRV_ID_MCP_HSI_VER_CURRENT (LOAD_REQ_HSI_VERSION << \
12196 DRV_ID_MCP_HSI_VER_SHIFT)
12198 #define DRV_ID_DRV_TYPE_MASK 0x7f000000
12199 #define DRV_ID_DRV_TYPE_SHIFT 24
12200 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT)
12201 #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT)
12203 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000
12204 #define DRV_ID_DRV_INIT_HW_SHIFT 31
12205 #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT)
12208 #define OEM_CFG_FUNC_TC_MASK 0x0000000F
12209 #define OEM_CFG_FUNC_TC_OFFSET 0
12210 #define OEM_CFG_FUNC_TC_0 0x0
12211 #define OEM_CFG_FUNC_TC_1 0x1
12212 #define OEM_CFG_FUNC_TC_2 0x2
12213 #define OEM_CFG_FUNC_TC_3 0x3
12214 #define OEM_CFG_FUNC_TC_4 0x4
12215 #define OEM_CFG_FUNC_TC_5 0x5
12216 #define OEM_CFG_FUNC_TC_6 0x6
12217 #define OEM_CFG_FUNC_TC_7 0x7
12219 #define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK 0x00000030
12220 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET 4
12221 #define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC 0x1
12222 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OS 0x2
12235 struct mcp_file_att {
12236 u32 nvm_start_addr;
12240 struct bist_nvm_image_att {
12243 u32 nvm_start_addr;
12247 #define MCP_DRV_VER_STR_SIZE 16
12248 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
12249 #define MCP_DRV_NVM_BUF_LEN 32
12250 struct drv_version_stc {
12252 u8 name[MCP_DRV_VER_STR_SIZE - 4];
12255 struct lan_stats_stc {
12262 struct fcoe_stats_stc {
12269 struct ocbb_data_stc {
12270 u32 ocbb_host_addr;
12271 u32 ocsd_host_addr;
12272 u32 ocsd_req_update_interval;
12275 #define MAX_NUM_OF_SENSORS 7
12276 struct temperature_status_stc {
12277 u32 num_of_sensors;
12278 u32 sensor[MAX_NUM_OF_SENSORS];
12281 /* crash dump configuration header */
12282 struct mdump_config_stc {
12290 enum resource_id_enum {
12291 RESOURCE_NUM_SB_E = 0,
12292 RESOURCE_NUM_L2_QUEUE_E = 1,
12293 RESOURCE_NUM_VPORT_E = 2,
12294 RESOURCE_NUM_VMQ_E = 3,
12295 RESOURCE_FACTOR_NUM_RSS_PF_E = 4,
12296 RESOURCE_FACTOR_RSS_PER_VF_E = 5,
12297 RESOURCE_NUM_RL_E = 6,
12298 RESOURCE_NUM_PQ_E = 7,
12299 RESOURCE_NUM_VF_E = 8,
12300 RESOURCE_VFC_FILTER_E = 9,
12301 RESOURCE_ILT_E = 10,
12302 RESOURCE_CQS_E = 11,
12303 RESOURCE_GFT_PROFILES_E = 12,
12304 RESOURCE_NUM_TC_E = 13,
12305 RESOURCE_NUM_RSS_ENGINES_E = 14,
12306 RESOURCE_LL2_QUEUE_E = 15,
12307 RESOURCE_RDMA_STATS_QUEUE_E = 16,
12308 RESOURCE_BDQ_E = 17,
12309 RESOURCE_QCN_E = 18,
12310 RESOURCE_LLH_FILTER_E = 19,
12311 RESOURCE_VF_MAC_ADDR = 20,
12312 RESOURCE_LL2_CQS_E = 21,
12313 RESOURCE_VF_CNQS = 22,
12315 RESOURCE_NUM_INVALID = 0xFFFFFFFF
12318 /* Resource ID is to be filled by the driver in the MB request
12319 * Size, offset & flags to be filled by the MFW in the MB response
12321 struct resource_info {
12322 enum resource_id_enum res_id;
12323 u32 size; /* number of allocated resources */
12324 u32 offset; /* Offset of the 1st resource */
12328 #define RESOURCE_ELEMENT_STRICT (1 << 0)
12331 #define DRV_ROLE_NONE 0
12332 #define DRV_ROLE_PREBOOT 1
12333 #define DRV_ROLE_OS 2
12334 #define DRV_ROLE_KDUMP 3
12336 struct load_req_stc {
12341 #define LOAD_REQ_ROLE_MASK 0x000000FF
12342 #define LOAD_REQ_ROLE_SHIFT 0
12343 #define LOAD_REQ_LOCK_TO_MASK 0x0000FF00
12344 #define LOAD_REQ_LOCK_TO_SHIFT 8
12345 #define LOAD_REQ_LOCK_TO_DEFAULT 0
12346 #define LOAD_REQ_LOCK_TO_NONE 255
12347 #define LOAD_REQ_FORCE_MASK 0x000F0000
12348 #define LOAD_REQ_FORCE_SHIFT 16
12349 #define LOAD_REQ_FORCE_NONE 0
12350 #define LOAD_REQ_FORCE_PF 1
12351 #define LOAD_REQ_FORCE_ALL 2
12352 #define LOAD_REQ_FLAGS0_MASK 0x00F00000
12353 #define LOAD_REQ_FLAGS0_SHIFT 20
12354 #define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0)
12357 struct load_rsp_stc {
12362 #define LOAD_RSP_ROLE_MASK 0x000000FF
12363 #define LOAD_RSP_ROLE_SHIFT 0
12364 #define LOAD_RSP_HSI_MASK 0x0000FF00
12365 #define LOAD_RSP_HSI_SHIFT 8
12366 #define LOAD_RSP_FLAGS0_MASK 0x000F0000
12367 #define LOAD_RSP_FLAGS0_SHIFT 16
12368 #define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0)
12371 struct mdump_retain_data_stc {
12378 union drv_union_data {
12379 u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
12380 struct mcp_mac wol_mac;
12382 struct eth_phy_cfg drv_phy_cfg;
12384 struct mcp_val64 val64;
12386 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
12388 struct mcp_file_att file_att;
12390 u32 ack_vf_disabled[VF_MAX_STATIC / 32];
12392 struct drv_version_stc drv_version;
12394 struct lan_stats_stc lan_stats;
12395 struct fcoe_stats_stc fcoe_stats;
12396 struct ocbb_data_stc ocbb_info;
12397 struct temperature_status_stc temp_info;
12398 struct resource_info resource;
12399 struct bist_nvm_image_att nvm_image_att;
12400 struct mdump_config_stc mdump_config;
12403 struct public_drv_mb {
12405 #define DRV_MSG_CODE_MASK 0xffff0000
12406 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
12407 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
12408 #define DRV_MSG_CODE_INIT_HW 0x12000000
12409 #define DRV_MSG_CODE_CANCEL_LOAD_REQ 0x13000000
12410 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000
12411 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
12412 #define DRV_MSG_CODE_INIT_PHY 0x22000000
12413 #define DRV_MSG_CODE_LINK_RESET 0x23000000
12414 #define DRV_MSG_CODE_SET_DCBX 0x25000000
12415 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000
12416 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000
12417 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000
12418 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000
12419 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000
12420 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
12421 #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000
12422 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000
12423 #define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000
12424 #define DRV_MSG_CODE_OV_UPDATE_WOL 0x38000000
12425 #define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE 0x39000000
12426 #define DRV_MSG_CODE_GET_OEM_UPDATES 0x41000000
12428 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000
12429 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000
12430 #define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000
12431 #define DRV_MSG_CODE_GET_NVM_CFG_OPTION 0x003e0000
12432 #define DRV_MSG_CODE_SET_NVM_CFG_OPTION 0x003f0000
12433 #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000
12434 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
12435 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
12436 #define DRV_MSG_CODE_CFG_PF_VFS_MSIX 0xc0020000
12437 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000
12438 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000
12439 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000
12440 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000
12441 #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000
12442 #define DRV_MSG_CODE_MCP_RESET 0x00090000
12443 #define DRV_MSG_CODE_SET_VERSION 0x000f0000
12444 #define DRV_MSG_CODE_MCP_HALT 0x00100000
12445 #define DRV_MSG_CODE_SET_VMAC 0x00110000
12446 #define DRV_MSG_CODE_GET_VMAC 0x00120000
12447 #define DRV_MSG_CODE_VMAC_TYPE_SHIFT 4
12448 #define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30
12449 #define DRV_MSG_CODE_VMAC_TYPE_MAC 1
12450 #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2
12451 #define DRV_MSG_CODE_VMAC_TYPE_WWPN 3
12453 #define DRV_MSG_CODE_GET_STATS 0x00130000
12454 #define DRV_MSG_CODE_STATS_TYPE_LAN 1
12455 #define DRV_MSG_CODE_STATS_TYPE_FCOE 2
12456 #define DRV_MSG_CODE_STATS_TYPE_ISCSI 3
12457 #define DRV_MSG_CODE_STATS_TYPE_RDMA 4
12459 #define DRV_MSG_CODE_TRANSCEIVER_READ 0x00160000
12461 #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000
12463 #define DRV_MSG_CODE_BIST_TEST 0x001e0000
12464 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000
12465 #define DRV_MSG_CODE_RESOURCE_CMD 0x00230000
12466 /* Send crash dump commands with param[3:0] - opcode */
12467 #define DRV_MSG_CODE_MDUMP_CMD 0x00250000
12468 #define DRV_MSG_CODE_GET_TLV_DONE 0x002f0000
12469 #define DRV_MSG_CODE_GET_ENGINE_CONFIG 0x00370000
12470 #define DRV_MSG_CODE_GET_PPFID_BITMAP 0x43000000
12472 #define DRV_MSG_CODE_DEBUG_DATA_SEND 0xc0040000
12474 #define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F
12475 #define RESOURCE_CMD_REQ_RESC_SHIFT 0
12476 #define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0
12477 #define RESOURCE_CMD_REQ_OPCODE_SHIFT 5
12478 #define RESOURCE_OPCODE_REQ 1
12479 #define RESOURCE_OPCODE_REQ_WO_AGING 2
12480 #define RESOURCE_OPCODE_REQ_W_AGING 3
12481 #define RESOURCE_OPCODE_RELEASE 4
12482 #define RESOURCE_OPCODE_FORCE_RELEASE 5
12483 #define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00
12484 #define RESOURCE_CMD_REQ_AGE_SHIFT 8
12486 #define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF
12487 #define RESOURCE_CMD_RSP_OWNER_SHIFT 0
12488 #define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700
12489 #define RESOURCE_CMD_RSP_OPCODE_SHIFT 8
12490 #define RESOURCE_OPCODE_GNT 1
12491 #define RESOURCE_OPCODE_BUSY 2
12492 #define RESOURCE_OPCODE_RELEASED 3
12493 #define RESOURCE_OPCODE_RELEASED_PREVIOUS 4
12494 #define RESOURCE_OPCODE_WRONG_OWNER 5
12495 #define RESOURCE_OPCODE_UNKNOWN_CMD 255
12497 #define RESOURCE_DUMP 0
12499 /* DRV_MSG_CODE_MDUMP_CMD parameters */
12500 #define MDUMP_DRV_PARAM_OPCODE_MASK 0x0000000f
12501 #define DRV_MSG_CODE_MDUMP_ACK 0x01
12502 #define DRV_MSG_CODE_MDUMP_SET_VALUES 0x02
12503 #define DRV_MSG_CODE_MDUMP_TRIGGER 0x03
12504 #define DRV_MSG_CODE_MDUMP_GET_CONFIG 0x04
12505 #define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05
12506 #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06
12507 #define DRV_MSG_CODE_MDUMP_GET_RETAIN 0x07
12508 #define DRV_MSG_CODE_MDUMP_CLR_RETAIN 0x08
12510 #define DRV_MSG_CODE_HW_DUMP_TRIGGER 0x0a
12511 #define DRV_MSG_CODE_MDUMP_GEN_MDUMP2 0x0b
12512 #define DRV_MSG_CODE_MDUMP_FREE_MDUMP2 0x0c
12514 #define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL 0x002b0000
12515 #define DRV_MSG_CODE_OS_WOL 0x002e0000
12517 #define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000
12518 #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000
12519 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
12522 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
12523 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
12524 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
12525 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
12526 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x000000FF
12527 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3
12529 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MBI 0x3
12530 #define DRV_MB_PARAM_NVM_OFFSET_OFFSET 0
12531 #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF
12532 #define DRV_MB_PARAM_NVM_LEN_OFFSET 24
12533 #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000
12535 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
12536 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
12537 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8
12538 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
12539 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
12540 #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0
12542 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0
12543 #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F
12544 #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0
12545 #define DRV_MB_PARAM_OV_CURR_CFG_OS 1
12546 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2
12547 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3
12549 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0
12550 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF
12551 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000
12552 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000
12553 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00
12554 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF
12556 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0
12557 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF
12558 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1
12559 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2
12560 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3
12561 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4
12562 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5
12564 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0
12565 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF
12567 #define DRV_MB_PARAM_WOL_MASK (DRV_MB_PARAM_WOL_DEFAULT | \
12568 DRV_MB_PARAM_WOL_DISABLED | \
12569 DRV_MB_PARAM_WOL_ENABLED)
12570 #define DRV_MB_PARAM_WOL_DEFAULT DRV_MB_PARAM_UNLOAD_WOL_MCP
12571 #define DRV_MB_PARAM_WOL_DISABLED DRV_MB_PARAM_UNLOAD_WOL_DISABLED
12572 #define DRV_MB_PARAM_WOL_ENABLED DRV_MB_PARAM_UNLOAD_WOL_ENABLED
12574 #define DRV_MB_PARAM_ESWITCH_MODE_MASK (DRV_MB_PARAM_ESWITCH_MODE_NONE | \
12575 DRV_MB_PARAM_ESWITCH_MODE_VEB | \
12576 DRV_MB_PARAM_ESWITCH_MODE_VEPA)
12577 #define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0
12578 #define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1
12579 #define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2
12581 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK 0x1
12582 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET 0
12584 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
12585 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
12586 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
12588 #define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0
12589 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003
12590 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET 2
12591 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000fc
12592 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET 8
12593 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000ff00
12594 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET 16
12595 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xffff0000
12597 /* Resource Allocation params - Driver version support */
12598 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xffff0000
12599 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
12600 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000ffff
12601 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
12603 #define DRV_MB_PARAM_BIST_REGISTER_TEST 1
12604 #define DRV_MB_PARAM_BIST_CLOCK_TEST 2
12605 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3
12606 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4
12608 #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
12609 #define DRV_MB_PARAM_BIST_RC_PASSED 1
12610 #define DRV_MB_PARAM_BIST_RC_FAILED 2
12611 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3
12613 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0
12614 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000ff
12615 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8
12616 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000ff00
12618 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000ffff
12619 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0
12620 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002
12621 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_FEC_CONTROL 0x00000004
12622 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EXT_SPEED_FEC_CONTROL 0x00000008
12623 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000
12625 /* DRV_MSG_CODE_DEBUG_DATA_SEND parameters */
12626 #define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_OFFSET 0
12627 #define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_MASK 0xff
12629 /* Driver attributes params */
12630 #define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET 0
12631 #define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK 0x00ffffff
12632 #define DRV_MB_PARAM_ATTRIBUTE_CMD_OFFSET 24
12633 #define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK 0xff000000
12635 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_OFFSET 0
12636 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_SHIFT 0
12637 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK 0x0000ffff
12638 #define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_SHIFT 16
12639 #define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK 0x00010000
12640 #define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_SHIFT 17
12641 #define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK 0x00020000
12642 #define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_SHIFT 18
12643 #define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK 0x00040000
12644 #define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_SHIFT 19
12645 #define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK 0x00080000
12646 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_SHIFT 20
12647 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_MASK 0x00100000
12648 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_SHIFT 24
12649 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_MASK 0x0f000000
12652 #define FW_MSG_CODE_MASK 0xffff0000
12653 #define FW_MSG_CODE_UNSUPPORTED 0x00000000
12654 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000
12655 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
12656 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
12657 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000
12658 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 0x10210000
12659 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000
12660 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10230000
12661 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000
12662 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT 0x10310000
12663 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
12664 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000
12665 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000
12666 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000
12667 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
12668 #define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000
12669 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000
12670 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000
12671 #define FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE 0x3b000000
12672 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
12674 #define FW_MSG_CODE_NVM_OK 0x00010000
12675 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000
12676 #define FW_MSG_CODE_PHY_OK 0x00110000
12677 #define FW_MSG_CODE_OK 0x00160000
12678 #define FW_MSG_CODE_ERROR 0x00170000
12679 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000
12680 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000
12681 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000
12683 #define FW_MSG_CODE_OS_WOL_SUPPORTED 0x00800000
12684 #define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED 0x00810000
12685 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000
12686 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
12688 #define FW_MSG_CODE_DEBUG_DATA_SEND_INV_ARG 0xb0070000
12689 #define FW_MSG_CODE_DEBUG_DATA_SEND_BUF_FULL 0xb0080000
12690 #define FW_MSG_CODE_DEBUG_DATA_SEND_NO_BUF 0xb0090000
12691 #define FW_MSG_CODE_DEBUG_NOT_ENABLED 0xb00a0000
12692 #define FW_MSG_CODE_DEBUG_DATA_SEND_OK 0xb00b0000
12694 #define FW_MSG_CODE_MDUMP_INVALID_CMD 0x00030000
12697 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xffff0000
12698 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
12699 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000ffff
12700 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
12702 /* Get PF RDMA protocol command response */
12703 #define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0
12704 #define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1
12705 #define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2
12706 #define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3
12708 /* Get MFW feature support response */
12709 #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ BIT(0)
12710 #define FW_MB_PARAM_FEATURE_SUPPORT_EEE BIT(1)
12711 #define FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL BIT(5)
12712 #define FW_MB_PARAM_FEATURE_SUPPORT_EXT_SPEED_FEC_CONTROL BIT(6)
12713 #define FW_MB_PARAM_FEATURE_SUPPORT_VLINK BIT(16)
12715 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR BIT(0)
12717 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK 0x00000001
12718 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_SHIFT 0
12719 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK 0x00000002
12720 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_SHIFT 1
12721 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK 0x00000004
12722 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_SHIFT 2
12723 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK 0x00000008
12724 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_SHIFT 3
12726 #define FW_MB_PARAM_PPFID_BITMAP_MASK 0xff
12727 #define FW_MB_PARAM_PPFID_BITMAP_SHIFT 0
12730 #define DRV_PULSE_SEQ_MASK 0x00007fff
12731 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
12732 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
12735 #define MCP_PULSE_SEQ_MASK 0x00007fff
12736 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
12737 #define MCP_EVENT_MASK 0xffff0000
12738 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
12740 union drv_union_data union_data;
12743 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_MASK 0x00ffffff
12744 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_SHIFT 0
12745 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_MASK 0xff000000
12746 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_SHIFT 24
12748 enum MFW_DRV_MSG_TYPE {
12749 MFW_DRV_MSG_LINK_CHANGE,
12750 MFW_DRV_MSG_FLR_FW_ACK_FAILED,
12751 MFW_DRV_MSG_VF_DISABLED,
12752 MFW_DRV_MSG_LLDP_DATA_UPDATED,
12753 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
12754 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
12755 MFW_DRV_MSG_ERROR_RECOVERY,
12756 MFW_DRV_MSG_BW_UPDATE,
12757 MFW_DRV_MSG_S_TAG_UPDATE,
12758 MFW_DRV_MSG_GET_LAN_STATS,
12759 MFW_DRV_MSG_GET_FCOE_STATS,
12760 MFW_DRV_MSG_GET_ISCSI_STATS,
12761 MFW_DRV_MSG_GET_RDMA_STATS,
12762 MFW_DRV_MSG_FAILURE_DETECTED,
12763 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
12764 MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED,
12765 MFW_DRV_MSG_RESERVED,
12766 MFW_DRV_MSG_GET_TLV_REQ,
12767 MFW_DRV_MSG_OEM_CFG_UPDATE,
12771 #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1)
12772 #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2)
12773 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3)
12774 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id))
12776 struct public_mfw_mb {
12778 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
12779 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
12782 enum public_sections {
12789 PUBLIC_MAX_SECTIONS
12792 struct mcp_public_data {
12794 u32 sections[PUBLIC_MAX_SECTIONS];
12795 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
12796 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
12797 struct public_global global;
12798 struct public_path path[MCP_GLOB_PATH_MAX];
12799 struct public_port port[MCP_GLOB_PORT_MAX];
12800 struct public_func func[MCP_GLOB_FUNC_MAX];
12803 #define MAX_I2C_TRANSACTION_SIZE 16
12805 /* OCBB definitions */
12807 /* Category 1: Device Properties */
12809 DRV_TLV_CLP_STR_CTD,
12810 /* Category 6: Device Configuration */
12817 /* Category 8: Port Configuration */
12818 DRV_TLV_NPIV_ENABLED,
12819 /* Category 10: Function Configuration */
12820 DRV_TLV_FEATURE_FLAGS,
12821 DRV_TLV_LOCAL_ADMIN_ADDR,
12822 DRV_TLV_ADDITIONAL_MAC_ADDR_1,
12823 DRV_TLV_ADDITIONAL_MAC_ADDR_2,
12824 DRV_TLV_LSO_MAX_OFFLOAD_SIZE,
12825 DRV_TLV_LSO_MIN_SEGMENT_COUNT,
12826 DRV_TLV_PROMISCUOUS_MODE,
12827 DRV_TLV_TX_DESCRIPTORS_QUEUE_SIZE,
12828 DRV_TLV_RX_DESCRIPTORS_QUEUE_SIZE,
12829 DRV_TLV_NUM_OF_NET_QUEUE_VMQ_CFG,
12830 DRV_TLV_FLEX_NIC_OUTER_VLAN_ID,
12831 DRV_TLV_OS_DRIVER_STATES,
12832 DRV_TLV_PXE_BOOT_PROGRESS,
12833 /* Category 12: FC/FCoE Configuration */
12834 DRV_TLV_NPIV_STATE,
12835 DRV_TLV_NUM_OF_NPIV_IDS,
12836 DRV_TLV_SWITCH_NAME,
12837 DRV_TLV_SWITCH_PORT_NUM,
12838 DRV_TLV_SWITCH_PORT_ID,
12839 DRV_TLV_VENDOR_NAME,
12840 DRV_TLV_SWITCH_MODEL,
12841 DRV_TLV_SWITCH_FW_VER,
12842 DRV_TLV_QOS_PRIORITY_PER_802_1P,
12843 DRV_TLV_PORT_ALIAS,
12844 DRV_TLV_PORT_STATE,
12845 DRV_TLV_FIP_TX_DESCRIPTORS_QUEUE_SIZE,
12846 DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_SIZE,
12847 DRV_TLV_LINK_FAILURE_COUNT,
12848 DRV_TLV_FCOE_BOOT_PROGRESS,
12849 /* Category 13: iSCSI Configuration */
12850 DRV_TLV_TARGET_LLMNR_ENABLED,
12851 DRV_TLV_HEADER_DIGEST_FLAG_ENABLED,
12852 DRV_TLV_DATA_DIGEST_FLAG_ENABLED,
12853 DRV_TLV_AUTHENTICATION_METHOD,
12854 DRV_TLV_ISCSI_BOOT_TARGET_PORTAL,
12855 DRV_TLV_MAX_FRAME_SIZE,
12856 DRV_TLV_PDU_TX_DESCRIPTORS_QUEUE_SIZE,
12857 DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_SIZE,
12858 DRV_TLV_ISCSI_BOOT_PROGRESS,
12859 /* Category 20: Device Data */
12860 DRV_TLV_PCIE_BUS_RX_UTILIZATION,
12861 DRV_TLV_PCIE_BUS_TX_UTILIZATION,
12862 DRV_TLV_DEVICE_CPU_CORES_UTILIZATION,
12863 DRV_TLV_LAST_VALID_DCC_TLV_RECEIVED,
12864 DRV_TLV_NCSI_RX_BYTES_RECEIVED,
12865 DRV_TLV_NCSI_TX_BYTES_SENT,
12866 /* Category 22: Base Port Data */
12867 DRV_TLV_RX_DISCARDS,
12870 DRV_TLV_TX_DISCARDS,
12871 DRV_TLV_RX_FRAMES_RECEIVED,
12872 DRV_TLV_TX_FRAMES_SENT,
12873 /* Category 23: FC/FCoE Port Data */
12874 DRV_TLV_RX_BROADCAST_PACKETS,
12875 DRV_TLV_TX_BROADCAST_PACKETS,
12876 /* Category 28: Base Function Data */
12877 DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV4,
12878 DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV6,
12879 DRV_TLV_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
12880 DRV_TLV_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
12881 DRV_TLV_PF_RX_FRAMES_RECEIVED,
12882 DRV_TLV_RX_BYTES_RECEIVED,
12883 DRV_TLV_PF_TX_FRAMES_SENT,
12884 DRV_TLV_TX_BYTES_SENT,
12885 DRV_TLV_IOV_OFFLOAD,
12886 DRV_TLV_PCI_ERRORS_CAP_ID,
12887 DRV_TLV_UNCORRECTABLE_ERROR_STATUS,
12888 DRV_TLV_UNCORRECTABLE_ERROR_MASK,
12889 DRV_TLV_CORRECTABLE_ERROR_STATUS,
12890 DRV_TLV_CORRECTABLE_ERROR_MASK,
12891 DRV_TLV_PCI_ERRORS_AECC_REGISTER,
12892 DRV_TLV_TX_QUEUES_EMPTY,
12893 DRV_TLV_RX_QUEUES_EMPTY,
12894 DRV_TLV_TX_QUEUES_FULL,
12895 DRV_TLV_RX_QUEUES_FULL,
12896 /* Category 29: FC/FCoE Function Data */
12897 DRV_TLV_FCOE_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
12898 DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
12899 DRV_TLV_FCOE_RX_FRAMES_RECEIVED,
12900 DRV_TLV_FCOE_RX_BYTES_RECEIVED,
12901 DRV_TLV_FCOE_TX_FRAMES_SENT,
12902 DRV_TLV_FCOE_TX_BYTES_SENT,
12903 DRV_TLV_CRC_ERROR_COUNT,
12904 DRV_TLV_CRC_ERROR_1_RECEIVED_SOURCE_FC_ID,
12905 DRV_TLV_CRC_ERROR_1_TIMESTAMP,
12906 DRV_TLV_CRC_ERROR_2_RECEIVED_SOURCE_FC_ID,
12907 DRV_TLV_CRC_ERROR_2_TIMESTAMP,
12908 DRV_TLV_CRC_ERROR_3_RECEIVED_SOURCE_FC_ID,
12909 DRV_TLV_CRC_ERROR_3_TIMESTAMP,
12910 DRV_TLV_CRC_ERROR_4_RECEIVED_SOURCE_FC_ID,
12911 DRV_TLV_CRC_ERROR_4_TIMESTAMP,
12912 DRV_TLV_CRC_ERROR_5_RECEIVED_SOURCE_FC_ID,
12913 DRV_TLV_CRC_ERROR_5_TIMESTAMP,
12914 DRV_TLV_LOSS_OF_SYNC_ERROR_COUNT,
12915 DRV_TLV_LOSS_OF_SIGNAL_ERRORS,
12916 DRV_TLV_PRIMITIVE_SEQUENCE_PROTOCOL_ERROR_COUNT,
12917 DRV_TLV_DISPARITY_ERROR_COUNT,
12918 DRV_TLV_CODE_VIOLATION_ERROR_COUNT,
12919 DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_1,
12920 DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_2,
12921 DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_3,
12922 DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_4,
12923 DRV_TLV_LAST_FLOGI_TIMESTAMP,
12924 DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_1,
12925 DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_2,
12926 DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_3,
12927 DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_4,
12928 DRV_TLV_LAST_FLOGI_ACC_TIMESTAMP,
12929 DRV_TLV_LAST_FLOGI_RJT,
12930 DRV_TLV_LAST_FLOGI_RJT_TIMESTAMP,
12931 DRV_TLV_FDISCS_SENT_COUNT,
12932 DRV_TLV_FDISC_ACCS_RECEIVED,
12933 DRV_TLV_FDISC_RJTS_RECEIVED,
12934 DRV_TLV_PLOGI_SENT_COUNT,
12935 DRV_TLV_PLOGI_ACCS_RECEIVED,
12936 DRV_TLV_PLOGI_RJTS_RECEIVED,
12937 DRV_TLV_PLOGI_1_SENT_DESTINATION_FC_ID,
12938 DRV_TLV_PLOGI_1_TIMESTAMP,
12939 DRV_TLV_PLOGI_2_SENT_DESTINATION_FC_ID,
12940 DRV_TLV_PLOGI_2_TIMESTAMP,
12941 DRV_TLV_PLOGI_3_SENT_DESTINATION_FC_ID,
12942 DRV_TLV_PLOGI_3_TIMESTAMP,
12943 DRV_TLV_PLOGI_4_SENT_DESTINATION_FC_ID,
12944 DRV_TLV_PLOGI_4_TIMESTAMP,
12945 DRV_TLV_PLOGI_5_SENT_DESTINATION_FC_ID,
12946 DRV_TLV_PLOGI_5_TIMESTAMP,
12947 DRV_TLV_PLOGI_1_ACC_RECEIVED_SOURCE_FC_ID,
12948 DRV_TLV_PLOGI_1_ACC_TIMESTAMP,
12949 DRV_TLV_PLOGI_2_ACC_RECEIVED_SOURCE_FC_ID,
12950 DRV_TLV_PLOGI_2_ACC_TIMESTAMP,
12951 DRV_TLV_PLOGI_3_ACC_RECEIVED_SOURCE_FC_ID,
12952 DRV_TLV_PLOGI_3_ACC_TIMESTAMP,
12953 DRV_TLV_PLOGI_4_ACC_RECEIVED_SOURCE_FC_ID,
12954 DRV_TLV_PLOGI_4_ACC_TIMESTAMP,
12955 DRV_TLV_PLOGI_5_ACC_RECEIVED_SOURCE_FC_ID,
12956 DRV_TLV_PLOGI_5_ACC_TIMESTAMP,
12957 DRV_TLV_LOGOS_ISSUED,
12958 DRV_TLV_LOGO_ACCS_RECEIVED,
12959 DRV_TLV_LOGO_RJTS_RECEIVED,
12960 DRV_TLV_LOGO_1_RECEIVED_SOURCE_FC_ID,
12961 DRV_TLV_LOGO_1_TIMESTAMP,
12962 DRV_TLV_LOGO_2_RECEIVED_SOURCE_FC_ID,
12963 DRV_TLV_LOGO_2_TIMESTAMP,
12964 DRV_TLV_LOGO_3_RECEIVED_SOURCE_FC_ID,
12965 DRV_TLV_LOGO_3_TIMESTAMP,
12966 DRV_TLV_LOGO_4_RECEIVED_SOURCE_FC_ID,
12967 DRV_TLV_LOGO_4_TIMESTAMP,
12968 DRV_TLV_LOGO_5_RECEIVED_SOURCE_FC_ID,
12969 DRV_TLV_LOGO_5_TIMESTAMP,
12970 DRV_TLV_LOGOS_RECEIVED,
12971 DRV_TLV_ACCS_ISSUED,
12972 DRV_TLV_PRLIS_ISSUED,
12973 DRV_TLV_ACCS_RECEIVED,
12974 DRV_TLV_ABTS_SENT_COUNT,
12975 DRV_TLV_ABTS_ACCS_RECEIVED,
12976 DRV_TLV_ABTS_RJTS_RECEIVED,
12977 DRV_TLV_ABTS_1_SENT_DESTINATION_FC_ID,
12978 DRV_TLV_ABTS_1_TIMESTAMP,
12979 DRV_TLV_ABTS_2_SENT_DESTINATION_FC_ID,
12980 DRV_TLV_ABTS_2_TIMESTAMP,
12981 DRV_TLV_ABTS_3_SENT_DESTINATION_FC_ID,
12982 DRV_TLV_ABTS_3_TIMESTAMP,
12983 DRV_TLV_ABTS_4_SENT_DESTINATION_FC_ID,
12984 DRV_TLV_ABTS_4_TIMESTAMP,
12985 DRV_TLV_ABTS_5_SENT_DESTINATION_FC_ID,
12986 DRV_TLV_ABTS_5_TIMESTAMP,
12987 DRV_TLV_RSCNS_RECEIVED,
12988 DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_1,
12989 DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_2,
12990 DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_3,
12991 DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_4,
12992 DRV_TLV_LUN_RESETS_ISSUED,
12993 DRV_TLV_ABORT_TASK_SETS_ISSUED,
12994 DRV_TLV_TPRLOS_SENT,
12995 DRV_TLV_NOS_SENT_COUNT,
12996 DRV_TLV_NOS_RECEIVED_COUNT,
13000 DRV_TLV_LIP_SENT_COUNT,
13001 DRV_TLV_LIP_RECEIVED_COUNT,
13002 DRV_TLV_EOFA_COUNT,
13003 DRV_TLV_EOFNI_COUNT,
13004 DRV_TLV_SCSI_STATUS_CHECK_CONDITION_COUNT,
13005 DRV_TLV_SCSI_STATUS_CONDITION_MET_COUNT,
13006 DRV_TLV_SCSI_STATUS_BUSY_COUNT,
13007 DRV_TLV_SCSI_STATUS_INTERMEDIATE_COUNT,
13008 DRV_TLV_SCSI_STATUS_INTERMEDIATE_CONDITION_MET_COUNT,
13009 DRV_TLV_SCSI_STATUS_RESERVATION_CONFLICT_COUNT,
13010 DRV_TLV_SCSI_STATUS_TASK_SET_FULL_COUNT,
13011 DRV_TLV_SCSI_STATUS_ACA_ACTIVE_COUNT,
13012 DRV_TLV_SCSI_STATUS_TASK_ABORTED_COUNT,
13013 DRV_TLV_SCSI_CHECK_CONDITION_1_RECEIVED_SK_ASC_ASCQ,
13014 DRV_TLV_SCSI_CHECK_1_TIMESTAMP,
13015 DRV_TLV_SCSI_CHECK_CONDITION_2_RECEIVED_SK_ASC_ASCQ,
13016 DRV_TLV_SCSI_CHECK_2_TIMESTAMP,
13017 DRV_TLV_SCSI_CHECK_CONDITION_3_RECEIVED_SK_ASC_ASCQ,
13018 DRV_TLV_SCSI_CHECK_3_TIMESTAMP,
13019 DRV_TLV_SCSI_CHECK_CONDITION_4_RECEIVED_SK_ASC_ASCQ,
13020 DRV_TLV_SCSI_CHECK_4_TIMESTAMP,
13021 DRV_TLV_SCSI_CHECK_CONDITION_5_RECEIVED_SK_ASC_ASCQ,
13022 DRV_TLV_SCSI_CHECK_5_TIMESTAMP,
13023 /* Category 30: iSCSI Function Data */
13024 DRV_TLV_PDU_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
13025 DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
13026 DRV_TLV_ISCSI_PDU_RX_FRAMES_RECEIVED,
13027 DRV_TLV_ISCSI_PDU_RX_BYTES_RECEIVED,
13028 DRV_TLV_ISCSI_PDU_TX_FRAMES_SENT,
13029 DRV_TLV_ISCSI_PDU_TX_BYTES_SENT
13032 struct nvm_cfg_mac_address {
13034 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000ffff
13035 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
13040 struct nvm_cfg1_glob {
13042 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000ff0
13043 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
13044 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
13045 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
13046 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
13047 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
13048 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
13049 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
13050 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6
13051 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
13053 u32 engineering_change[3];
13054 u32 manufacturing_id;
13055 u32 serial_number[4];
13060 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000ff
13061 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
13062 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0
13063 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1
13064 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2
13065 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3
13066 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4
13067 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5
13068 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xb
13069 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xc
13070 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xd
13071 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xe
13072 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xf
13073 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X50G_R1 0x11
13074 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_4X50G_R1 0x12
13075 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R2 0x13
13076 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X100G_R2 0x14
13077 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R4 0x15
13083 u32 mps10_preemphasis;
13084 u32 mps10_driver_current;
13085 u32 mps25_preemphasis;
13086 u32 mps25_driver_current;
13090 u32 mps10_txfir_main;
13091 u32 mps10_txfir_post;
13092 u32 mps25_txfir_main;
13093 u32 mps25_txfir_post;
13094 u32 manufacture_ver;
13095 u32 manufacture_time;
13096 u32 led_global_settings;
13100 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000ff
13101 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
13102 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000ff00
13103 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
13104 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00ff0000
13105 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
13110 u32 device_capabilities;
13111 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
13112 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2
13113 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
13114 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
13116 u32 power_dissipated;
13117 u32 power_consumed;
13119 u32 multi_net_modes_cap;
13123 struct nvm_cfg1_path {
13127 struct nvm_cfg1_port {
13132 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000f0000
13133 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
13134 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
13135 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
13136 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
13137 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
13138 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00f00000
13139 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
13140 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
13141 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2
13142 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4
13147 u32 speed_cap_mask;
13148 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000ffff
13149 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
13150 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
13151 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
13152 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G 0x4
13153 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
13154 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
13155 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
13156 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
13159 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000f
13160 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
13161 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
13162 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
13163 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
13164 #define NVM_CFG1_PORT_DRV_LINK_SPEED_20G 0x3
13165 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
13166 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
13167 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
13168 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7
13169 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8
13170 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
13171 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
13172 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
13173 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
13174 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
13175 #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000e0000
13176 #define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17
13177 #define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE 0x0
13178 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE 0x1
13179 #define NVM_CFG1_PORT_FEC_FORCE_MODE_RS 0x2
13180 #define NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO 0x7
13186 /* EEE power saving mode */
13187 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00ff0000
13188 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16
13189 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0
13190 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1
13191 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2
13192 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3
13197 struct nvm_cfg_mac_address lldp_mac_address;
13198 u32 led_port_settings;
13199 u32 transceiver_00;
13203 #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000ff
13204 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0
13205 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0
13206 #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1
13207 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2
13208 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3
13209 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4
13230 u32 extended_speed;
13231 #define NVM_CFG1_PORT_EXTENDED_SPEED_MASK 0x0000ffff
13232 #define NVM_CFG1_PORT_EXTENDED_SPEED_OFFSET 0
13233 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_AN 0x1
13234 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_1G 0x2
13235 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_10G 0x4
13236 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_20G 0x8
13237 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_25G 0x10
13238 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_40G 0x20
13239 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R 0x40
13240 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R2 0x80
13241 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R2 0x100
13242 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R4 0x200
13243 #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_P4 0x400
13244 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_MASK 0xffff0000
13245 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_OFFSET 16
13246 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_RESERVED 0x1
13247 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_1G 0x2
13248 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_10G 0x4
13249 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_20G 0x8
13250 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_25G 0x10
13251 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_40G 0x20
13252 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R 0x40
13253 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R2 0x80
13254 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R2 0x100
13255 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R4 0x200
13256 #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_P4 0x400
13258 u32 extended_fec_mode;
13263 struct nvm_cfg1_func {
13264 struct nvm_cfg_mac_address mac_address;
13270 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr;
13271 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr;
13272 u32 preboot_generic_cfg;
13277 struct nvm_cfg1_glob glob;
13278 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX];
13279 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX];
13280 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX];
13283 enum spad_sections {
13284 SPAD_SECTION_TRACE,
13285 SPAD_SECTION_NVM_CFG,
13286 SPAD_SECTION_PUBLIC,
13287 SPAD_SECTION_PRIVATE,
13291 #define MCP_TRACE_SIZE 2048 /* 2kb */
13293 /* This section is located at a fixed location in the beginning of the
13294 * scratchpad, to ensure that the MCP trace is not run over during MFW upgrade.
13295 * All the rest of data has a floating location which differs from version to
13296 * version, and is pointed by the mcp_meta_data below.
13297 * Moreover, the spad_layout section is part of the MFW firmware, and is loaded
13298 * with it from nvram in order to clear this portion.
13300 struct static_init {
13302 offsize_t sections[SPAD_SECTION_MAX];
13303 #define SECTION(_sec_) (*((offsize_t *)(STRUCT_OFFSET(sections[_sec_]))))
13305 struct mcp_trace trace;
13306 #define MCP_TRACE_P ((struct mcp_trace *)(STRUCT_OFFSET(trace)))
13307 u8 trace_buffer[MCP_TRACE_SIZE];
13308 #define MCP_TRACE_BUF ((u8 *)(STRUCT_OFFSET(trace_buffer)))
13309 /* running_mfw has the same definition as in nvm_map.h.
13310 * This bit indicate both the running dir, and the running bundle.
13311 * It is set once when the LIM is loaded.
13314 #define RUNNING_MFW (*((u32 *)(STRUCT_OFFSET(running_mfw))))
13316 #define MFW_BUILD_TIME (*((u32 *)(STRUCT_OFFSET(build_time))))
13318 #define RESET_TYPE (*((u32 *)(STRUCT_OFFSET(reset_type))))
13319 u32 mfw_secure_mode;
13320 #define MFW_SECURE_MODE (*((u32 *)(STRUCT_OFFSET(mfw_secure_mode))))
13321 u16 pme_status_pf_bitmap;
13322 #define PME_STATUS_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_status_pf_bitmap))))
13323 u16 pme_enable_pf_bitmap;
13324 #define PME_ENABLE_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_enable_pf_bitmap))))
13326 u32 mim_start_addr;
13327 u32 ah_pcie_link_params;
13328 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK (0x000000ff)
13329 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT (0)
13330 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK (0x0000ff00)
13331 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT (8)
13332 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK (0x00ff0000)
13333 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT (16)
13334 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK (0xff000000)
13335 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT (24)
13336 #define AH_PCIE_LINK_PARAMS (*((u32 *)(STRUCT_OFFSET(ah_pcie_link_params))))
13338 u32 rsrv_persist[5]; /* Persist reserved for MFW upgrades */
13341 #define NVM_MAGIC_VALUE 0x669955aa
13343 enum nvm_image_type {
13344 NVM_TYPE_TIM1 = 0x01,
13345 NVM_TYPE_TIM2 = 0x02,
13346 NVM_TYPE_MIM1 = 0x03,
13347 NVM_TYPE_MIM2 = 0x04,
13348 NVM_TYPE_MBA = 0x05,
13349 NVM_TYPE_MODULES_PN = 0x06,
13350 NVM_TYPE_VPD = 0x07,
13351 NVM_TYPE_MFW_TRACE1 = 0x08,
13352 NVM_TYPE_MFW_TRACE2 = 0x09,
13353 NVM_TYPE_NVM_CFG1 = 0x0a,
13354 NVM_TYPE_L2B = 0x0b,
13355 NVM_TYPE_DIR1 = 0x0c,
13356 NVM_TYPE_EAGLE_FW1 = 0x0d,
13357 NVM_TYPE_FALCON_FW1 = 0x0e,
13358 NVM_TYPE_PCIE_FW1 = 0x0f,
13359 NVM_TYPE_HW_SET = 0x10,
13360 NVM_TYPE_LIM = 0x11,
13361 NVM_TYPE_AVS_FW1 = 0x12,
13362 NVM_TYPE_DIR2 = 0x13,
13363 NVM_TYPE_CCM = 0x14,
13364 NVM_TYPE_EAGLE_FW2 = 0x15,
13365 NVM_TYPE_FALCON_FW2 = 0x16,
13366 NVM_TYPE_PCIE_FW2 = 0x17,
13367 NVM_TYPE_AVS_FW2 = 0x18,
13368 NVM_TYPE_INIT_HW = 0x19,
13369 NVM_TYPE_DEFAULT_CFG = 0x1a,
13370 NVM_TYPE_MDUMP = 0x1b,
13371 NVM_TYPE_META = 0x1c,
13372 NVM_TYPE_ISCSI_CFG = 0x1d,
13373 NVM_TYPE_FCOE_CFG = 0x1f,
13374 NVM_TYPE_ETH_PHY_FW1 = 0x20,
13375 NVM_TYPE_ETH_PHY_FW2 = 0x21,
13376 NVM_TYPE_BDN = 0x22,
13377 NVM_TYPE_8485X_PHY_FW = 0x23,
13378 NVM_TYPE_PUB_KEY = 0x24,
13379 NVM_TYPE_RECOVERY = 0x25,
13380 NVM_TYPE_PLDM = 0x26,
13381 NVM_TYPE_UPK1 = 0x27,
13382 NVM_TYPE_UPK2 = 0x28,
13383 NVM_TYPE_MASTER_KC = 0x29,
13384 NVM_TYPE_BACKUP_KC = 0x2a,
13385 NVM_TYPE_HW_DUMP = 0x2b,
13386 NVM_TYPE_HW_DUMP_OUT = 0x2c,
13387 NVM_TYPE_BIN_NVM_META = 0x30,
13388 NVM_TYPE_ROM_TEST = 0xf0,
13389 NVM_TYPE_88X33X0_PHY_FW = 0x31,
13390 NVM_TYPE_88X33X0_PHY_SLAVE_FW = 0x32,
13394 #define DIR_ID_1 (0)