1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, 2020, Linaro Ltd.
7 #include <linux/debugfs.h>
10 #include <linux/module.h>
11 #include <linux/nvmem-consumer.h>
13 #include <linux/of_address.h>
14 #include <linux/of_platform.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/platform_device.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20 #include <linux/thermal.h>
21 #include "../thermal_hwmon.h"
25 * struct tsens_irq_data - IRQ status and temperature violations
26 * @up_viol: upper threshold violated
27 * @up_thresh: upper threshold temperature value
28 * @up_irq_mask: mask register for upper threshold irqs
29 * @up_irq_clear: clear register for uppper threshold irqs
30 * @low_viol: lower threshold violated
31 * @low_thresh: lower threshold temperature value
32 * @low_irq_mask: mask register for lower threshold irqs
33 * @low_irq_clear: clear register for lower threshold irqs
34 * @crit_viol: critical threshold violated
35 * @crit_thresh: critical threshold temperature value
36 * @crit_irq_mask: mask register for critical threshold irqs
37 * @crit_irq_clear: clear register for critical threshold irqs
39 * Structure containing data about temperature threshold settings and
40 * irq status if they were violated.
42 struct tsens_irq_data {
57 char *qfprom_read(struct device *dev, const char *cname)
59 struct nvmem_cell *cell;
63 cell = nvmem_cell_get(dev, cname);
65 return ERR_CAST(cell);
67 ret = nvmem_cell_read(cell, &data);
73 int tsens_read_calibration(struct tsens_priv *priv, int shift, u32 *p1, u32 *p2, bool backup)
77 char name[] = "sXX_pY_backup"; /* s10_p1_backup */
80 if (priv->num_sensors > MAX_SENSORS)
83 ret = snprintf(name, sizeof(name), "mode%s", backup ? "_backup" : "");
87 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &mode);
89 dev_warn(priv->dev, "Please migrate to separate nvmem cells for calibration data\n");
93 dev_dbg(priv->dev, "calibration mode is %d\n", mode);
95 ret = snprintf(name, sizeof(name), "base1%s", backup ? "_backup" : "");
99 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &base1);
103 ret = snprintf(name, sizeof(name), "base2%s", backup ? "_backup" : "");
107 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &base2);
111 for (i = 0; i < priv->num_sensors; i++) {
112 ret = snprintf(name, sizeof(name), "s%d_p1%s", priv->sensor[i].hw_id,
113 backup ? "_backup" : "");
117 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &p1[i]);
121 ret = snprintf(name, sizeof(name), "s%d_p2%s", priv->sensor[i].hw_id,
122 backup ? "_backup" : "");
126 ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &p2[i]);
133 for (i = 0; i < priv->num_sensors; i++)
134 p1[i] = p1[i] + (base1 << shift);
137 case TWO_PT_CALIB_NO_OFFSET:
138 for (i = 0; i < priv->num_sensors; i++)
139 p2[i] = (p2[i] + base2) << shift;
142 case ONE_PT_CALIB2_NO_OFFSET:
143 for (i = 0; i < priv->num_sensors; i++)
144 p1[i] = (p1[i] + base1) << shift;
147 dev_dbg(priv->dev, "calibrationless mode\n");
148 for (i = 0; i < priv->num_sensors; i++) {
154 /* Apply calibration offset workaround except for _NO_OFFSET modes */
157 for (i = 0; i < priv->num_sensors; i++)
158 p2[i] += priv->sensor[i].p2_calib_offset;
161 for (i = 0; i < priv->num_sensors; i++)
162 p1[i] += priv->sensor[i].p1_calib_offset;
169 int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift)
171 u32 p1[MAX_SENSORS], p2[MAX_SENSORS];
174 mode = tsens_read_calibration(priv, shift, p1, p2, false);
178 compute_intercept_slope(priv, p1, p2, mode);
183 int tsens_calibrate_common(struct tsens_priv *priv)
185 return tsens_calibrate_nvmem(priv, 2);
188 static u32 tsens_read_cell(const struct tsens_single_value *cell, u8 len, u32 *data0, u32 *data1)
191 u32 *data = cell->blob ? data1 : data0;
193 if (cell->shift + len <= 32) {
194 val = data[cell->idx] >> cell->shift;
196 u8 part = 32 - cell->shift;
198 val = data[cell->idx] >> cell->shift;
199 val |= data[cell->idx + 1] << part;
202 return val & ((1 << len) - 1);
205 int tsens_read_calibration_legacy(struct tsens_priv *priv,
206 const struct tsens_legacy_calibration_format *format,
208 u32 *cdata0, u32 *cdata1)
214 mode = tsens_read_cell(&format->mode, 2, cdata0, cdata1);
215 invalid = tsens_read_cell(&format->invalid, 1, cdata0, cdata1);
218 dev_dbg(priv->dev, "calibration mode is %d\n", mode);
220 base1 = tsens_read_cell(&format->base[0], format->base_len, cdata0, cdata1);
221 base2 = tsens_read_cell(&format->base[1], format->base_len, cdata0, cdata1);
223 for (i = 0; i < priv->num_sensors; i++) {
224 p1[i] = tsens_read_cell(&format->sp[i][0], format->sp_len, cdata0, cdata1);
225 p2[i] = tsens_read_cell(&format->sp[i][1], format->sp_len, cdata0, cdata1);
230 for (i = 0; i < priv->num_sensors; i++)
231 p1[i] = p1[i] + (base1 << format->base_shift);
234 for (i = 0; i < priv->num_sensors; i++)
235 p2[i] = (p2[i] + base2) << format->base_shift;
238 for (i = 0; i < priv->num_sensors; i++)
239 p1[i] = (p1[i] + base1) << format->base_shift;
242 dev_dbg(priv->dev, "calibrationless mode\n");
243 for (i = 0; i < priv->num_sensors; i++) {
253 * Use this function on devices where slope and offset calculations
254 * depend on calibration data read from qfprom. On others the slope
255 * and offset values are derived from tz->tzp->slope and tz->tzp->offset
258 void compute_intercept_slope(struct tsens_priv *priv, u32 *p1,
264 for (i = 0; i < priv->num_sensors; i++) {
266 "%s: sensor%d - data_point1:%#x data_point2:%#x\n",
267 __func__, i, p1[i], p2[i]);
269 if (!priv->sensor[i].slope)
270 priv->sensor[i].slope = SLOPE_DEFAULT;
271 if (mode == TWO_PT_CALIB || mode == TWO_PT_CALIB_NO_OFFSET) {
273 * slope (m) = adc_code2 - adc_code1 (y2 - y1)/
274 * temp_120_degc - temp_30_degc (x2 - x1)
278 den = CAL_DEGC_PT2 - CAL_DEGC_PT1;
279 priv->sensor[i].slope = num / den;
282 priv->sensor[i].offset = (p1[i] * SLOPE_FACTOR) -
284 priv->sensor[i].slope);
285 dev_dbg(priv->dev, "%s: offset:%d\n", __func__,
286 priv->sensor[i].offset);
290 static inline u32 degc_to_code(int degc, const struct tsens_sensor *s)
292 u64 code = div_u64(((u64)degc * s->slope + s->offset), SLOPE_FACTOR);
294 pr_debug("%s: raw_code: 0x%llx, degc:%d\n", __func__, code, degc);
295 return clamp_val(code, THRESHOLD_MIN_ADC_CODE, THRESHOLD_MAX_ADC_CODE);
298 static inline int code_to_degc(u32 adc_code, const struct tsens_sensor *s)
302 num = (adc_code * SLOPE_FACTOR) - s->offset;
306 degc = num + (den / 2);
308 degc = num - (den / 2);
318 * tsens_hw_to_mC - Return sign-extended temperature in mCelsius.
319 * @s: Pointer to sensor struct
320 * @field: Index into regmap_field array pointing to temperature data
322 * This function handles temperature returned in ADC code or deciCelsius
323 * depending on IP version.
325 * Return: Temperature in milliCelsius on success, a negative errno will
326 * be returned in error cases
328 static int tsens_hw_to_mC(const struct tsens_sensor *s, int field)
330 struct tsens_priv *priv = s->priv;
335 resolution = priv->fields[LAST_TEMP_0].msb -
336 priv->fields[LAST_TEMP_0].lsb;
338 ret = regmap_field_read(priv->rf[field], &temp);
342 /* Convert temperature from ADC code to milliCelsius */
344 return code_to_degc(temp, s) * 1000;
346 /* deciCelsius -> milliCelsius along with sign extension */
347 return sign_extend32(temp, resolution) * 100;
351 * tsens_mC_to_hw - Convert temperature to hardware register value
352 * @s: Pointer to sensor struct
353 * @temp: temperature in milliCelsius to be programmed to hardware
355 * This function outputs the value to be written to hardware in ADC code
356 * or deciCelsius depending on IP version.
358 * Return: ADC code or temperature in deciCelsius.
360 static int tsens_mC_to_hw(const struct tsens_sensor *s, int temp)
362 struct tsens_priv *priv = s->priv;
364 /* milliC to adc code */
366 return degc_to_code(temp / 1000, s);
368 /* milliC to deciC */
372 static inline enum tsens_ver tsens_version(struct tsens_priv *priv)
374 return priv->feat->ver_major;
377 static void tsens_set_interrupt_v1(struct tsens_priv *priv, u32 hw_id,
378 enum tsens_irq_type irq_type, bool enable)
384 index = UP_INT_CLEAR_0 + hw_id;
387 index = LOW_INT_CLEAR_0 + hw_id;
390 /* No critical interrupts before v2 */
393 regmap_field_write(priv->rf[index], enable ? 0 : 1);
396 static void tsens_set_interrupt_v2(struct tsens_priv *priv, u32 hw_id,
397 enum tsens_irq_type irq_type, bool enable)
399 u32 index_mask = 0, index_clear = 0;
402 * To enable the interrupt flag for a sensor:
403 * - clear the mask bit
404 * To disable the interrupt flag for a sensor:
405 * - Mask further interrupts for this sensor
406 * - Write 1 followed by 0 to clear the interrupt
410 index_mask = UP_INT_MASK_0 + hw_id;
411 index_clear = UP_INT_CLEAR_0 + hw_id;
414 index_mask = LOW_INT_MASK_0 + hw_id;
415 index_clear = LOW_INT_CLEAR_0 + hw_id;
418 index_mask = CRIT_INT_MASK_0 + hw_id;
419 index_clear = CRIT_INT_CLEAR_0 + hw_id;
424 regmap_field_write(priv->rf[index_mask], 0);
426 regmap_field_write(priv->rf[index_mask], 1);
427 regmap_field_write(priv->rf[index_clear], 1);
428 regmap_field_write(priv->rf[index_clear], 0);
433 * tsens_set_interrupt - Set state of an interrupt
434 * @priv: Pointer to tsens controller private data
435 * @hw_id: Hardware ID aka. sensor number
436 * @irq_type: irq_type from enum tsens_irq_type
437 * @enable: false = disable, true = enable
439 * Call IP-specific function to set state of an interrupt
443 static void tsens_set_interrupt(struct tsens_priv *priv, u32 hw_id,
444 enum tsens_irq_type irq_type, bool enable)
446 dev_dbg(priv->dev, "[%u] %s: %s -> %s\n", hw_id, __func__,
447 irq_type ? ((irq_type == 1) ? "UP" : "CRITICAL") : "LOW",
448 enable ? "en" : "dis");
449 if (tsens_version(priv) > VER_1_X)
450 tsens_set_interrupt_v2(priv, hw_id, irq_type, enable);
452 tsens_set_interrupt_v1(priv, hw_id, irq_type, enable);
456 * tsens_threshold_violated - Check if a sensor temperature violated a preset threshold
457 * @priv: Pointer to tsens controller private data
458 * @hw_id: Hardware ID aka. sensor number
459 * @d: Pointer to irq state data
461 * Return: 0 if threshold was not violated, 1 if it was violated and negative
462 * errno in case of errors
464 static int tsens_threshold_violated(struct tsens_priv *priv, u32 hw_id,
465 struct tsens_irq_data *d)
469 ret = regmap_field_read(priv->rf[UPPER_STATUS_0 + hw_id], &d->up_viol);
472 ret = regmap_field_read(priv->rf[LOWER_STATUS_0 + hw_id], &d->low_viol);
476 if (priv->feat->crit_int) {
477 ret = regmap_field_read(priv->rf[CRITICAL_STATUS_0 + hw_id],
483 if (d->up_viol || d->low_viol || d->crit_viol)
489 static int tsens_read_irq_state(struct tsens_priv *priv, u32 hw_id,
490 const struct tsens_sensor *s,
491 struct tsens_irq_data *d)
495 ret = regmap_field_read(priv->rf[UP_INT_CLEAR_0 + hw_id], &d->up_irq_clear);
498 ret = regmap_field_read(priv->rf[LOW_INT_CLEAR_0 + hw_id], &d->low_irq_clear);
501 if (tsens_version(priv) > VER_1_X) {
502 ret = regmap_field_read(priv->rf[UP_INT_MASK_0 + hw_id], &d->up_irq_mask);
505 ret = regmap_field_read(priv->rf[LOW_INT_MASK_0 + hw_id], &d->low_irq_mask);
508 ret = regmap_field_read(priv->rf[CRIT_INT_CLEAR_0 + hw_id],
512 ret = regmap_field_read(priv->rf[CRIT_INT_MASK_0 + hw_id],
517 d->crit_thresh = tsens_hw_to_mC(s, CRIT_THRESH_0 + hw_id);
519 /* No mask register on older TSENS */
522 d->crit_irq_clear = 0;
523 d->crit_irq_mask = 0;
527 d->up_thresh = tsens_hw_to_mC(s, UP_THRESH_0 + hw_id);
528 d->low_thresh = tsens_hw_to_mC(s, LOW_THRESH_0 + hw_id);
530 dev_dbg(priv->dev, "[%u] %s%s: status(%u|%u|%u) | clr(%u|%u|%u) | mask(%u|%u|%u)\n",
532 (d->up_viol || d->low_viol || d->crit_viol) ? "(V)" : "",
533 d->low_viol, d->up_viol, d->crit_viol,
534 d->low_irq_clear, d->up_irq_clear, d->crit_irq_clear,
535 d->low_irq_mask, d->up_irq_mask, d->crit_irq_mask);
536 dev_dbg(priv->dev, "[%u] %s%s: thresh: (%d:%d:%d)\n", hw_id, __func__,
537 (d->up_viol || d->low_viol || d->crit_viol) ? "(V)" : "",
538 d->low_thresh, d->up_thresh, d->crit_thresh);
543 static inline u32 masked_irq(u32 hw_id, u32 mask, enum tsens_ver ver)
546 return mask & (1 << hw_id);
548 /* v1, v0.1 don't have a irq mask register */
553 * tsens_critical_irq_thread() - Threaded handler for critical interrupts
555 * @data: tsens controller private data
557 * Check FSM watchdog bark status and clear if needed.
558 * Check all sensors to find ones that violated their critical threshold limits.
559 * Clear and then re-enable the interrupt.
561 * The level-triggered interrupt might deassert if the temperature returned to
562 * within the threshold limits by the time the handler got scheduled. We
563 * consider the irq to have been handled in that case.
565 * Return: IRQ_HANDLED
567 static irqreturn_t tsens_critical_irq_thread(int irq, void *data)
569 struct tsens_priv *priv = data;
570 struct tsens_irq_data d;
572 u32 wdog_status, wdog_count;
574 if (priv->feat->has_watchdog) {
575 ret = regmap_field_read(priv->rf[WDOG_BARK_STATUS],
581 /* Clear WDOG interrupt */
582 regmap_field_write(priv->rf[WDOG_BARK_CLEAR], 1);
583 regmap_field_write(priv->rf[WDOG_BARK_CLEAR], 0);
584 ret = regmap_field_read(priv->rf[WDOG_BARK_COUNT],
589 dev_dbg(priv->dev, "%s: watchdog count: %d\n",
590 __func__, wdog_count);
592 /* Fall through to handle critical interrupts if any */
596 for (i = 0; i < priv->num_sensors; i++) {
597 const struct tsens_sensor *s = &priv->sensor[i];
598 u32 hw_id = s->hw_id;
602 if (!tsens_threshold_violated(priv, hw_id, &d))
604 ret = get_temp_tsens_valid(s, &temp);
606 dev_err(priv->dev, "[%u] %s: error reading sensor\n",
611 tsens_read_irq_state(priv, hw_id, s, &d);
613 !masked_irq(hw_id, d.crit_irq_mask, tsens_version(priv))) {
614 /* Mask critical interrupts, unused on Linux */
615 tsens_set_interrupt(priv, hw_id, CRITICAL, false);
623 * tsens_irq_thread - Threaded interrupt handler for uplow interrupts
625 * @data: tsens controller private data
627 * Check all sensors to find ones that violated their threshold limits. If the
628 * temperature is still outside the limits, call thermal_zone_device_update() to
629 * update the thresholds, else re-enable the interrupts.
631 * The level-triggered interrupt might deassert if the temperature returned to
632 * within the threshold limits by the time the handler got scheduled. We
633 * consider the irq to have been handled in that case.
635 * Return: IRQ_HANDLED
637 static irqreturn_t tsens_irq_thread(int irq, void *data)
639 struct tsens_priv *priv = data;
640 struct tsens_irq_data d;
643 for (i = 0; i < priv->num_sensors; i++) {
644 const struct tsens_sensor *s = &priv->sensor[i];
645 u32 hw_id = s->hw_id;
649 if (!tsens_threshold_violated(priv, hw_id, &d))
652 thermal_zone_device_update(s->tzd, THERMAL_EVENT_UNSPECIFIED);
654 if (tsens_version(priv) < VER_0_1) {
655 /* Constraint: There is only 1 interrupt control register for all
656 * 11 temperature sensor. So monitoring more than 1 sensor based
657 * on interrupts will yield inconsistent result. To overcome this
658 * issue we will monitor only sensor 0 which is the master sensor.
668 * tsens_combined_irq_thread() - Threaded interrupt handler for combined interrupts
670 * @data: tsens controller private data
672 * Handle the combined interrupt as if it were 2 separate interrupts, so call the
673 * critical handler first and then the up/low one.
675 * Return: IRQ_HANDLED
677 static irqreturn_t tsens_combined_irq_thread(int irq, void *data)
681 ret = tsens_critical_irq_thread(irq, data);
682 if (ret != IRQ_HANDLED)
685 return tsens_irq_thread(irq, data);
688 static int tsens_set_trips(struct thermal_zone_device *tz, int low, int high)
690 struct tsens_sensor *s = thermal_zone_device_priv(tz);
691 struct tsens_priv *priv = s->priv;
692 struct device *dev = priv->dev;
693 struct tsens_irq_data d;
695 int high_val, low_val, cl_high, cl_low;
696 u32 hw_id = s->hw_id;
698 if (tsens_version(priv) < VER_0_1) {
699 /* Pre v0.1 IP had a single register for each type of interrupt
705 dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n",
706 hw_id, __func__, low, high);
708 cl_high = clamp_val(high, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
709 cl_low = clamp_val(low, priv->feat->trip_min_temp, priv->feat->trip_max_temp);
711 high_val = tsens_mC_to_hw(s, cl_high);
712 low_val = tsens_mC_to_hw(s, cl_low);
714 spin_lock_irqsave(&priv->ul_lock, flags);
716 tsens_read_irq_state(priv, hw_id, s, &d);
718 /* Write the new thresholds and clear the status */
719 regmap_field_write(priv->rf[LOW_THRESH_0 + hw_id], low_val);
720 regmap_field_write(priv->rf[UP_THRESH_0 + hw_id], high_val);
721 tsens_set_interrupt(priv, hw_id, LOWER, true);
722 tsens_set_interrupt(priv, hw_id, UPPER, true);
724 spin_unlock_irqrestore(&priv->ul_lock, flags);
726 dev_dbg(dev, "[%u] %s: (%d:%d)->(%d:%d)\n",
727 hw_id, __func__, d.low_thresh, d.up_thresh, cl_low, cl_high);
732 static int tsens_enable_irq(struct tsens_priv *priv)
735 int val = tsens_version(priv) > VER_1_X ? 7 : 1;
737 ret = regmap_field_write(priv->rf[INT_EN], val);
739 dev_err(priv->dev, "%s: failed to enable interrupts\n",
745 static void tsens_disable_irq(struct tsens_priv *priv)
747 regmap_field_write(priv->rf[INT_EN], 0);
750 int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp)
752 struct tsens_priv *priv = s->priv;
753 int hw_id = s->hw_id;
754 u32 temp_idx = LAST_TEMP_0 + hw_id;
755 u32 valid_idx = VALID_0 + hw_id;
759 /* VER_0 doesn't have VALID bit */
760 if (tsens_version(priv) == VER_0)
763 /* Valid bit is 0 for 6 AHB clock cycles.
764 * At 19.2MHz, 1 AHB clock is ~60ns.
765 * We should enter this loop very, very rarely.
766 * Wait 1 us since it's the min of poll_timeout macro.
767 * Old value was 400 ns.
769 ret = regmap_field_read_poll_timeout(priv->rf[valid_idx], valid,
770 valid, 1, 20 * USEC_PER_MSEC);
775 /* Valid bit is set, OK to read the temperature */
776 *temp = tsens_hw_to_mC(s, temp_idx);
781 int get_temp_common(const struct tsens_sensor *s, int *temp)
783 struct tsens_priv *priv = s->priv;
784 int hw_id = s->hw_id;
785 int last_temp = 0, ret, trdy;
786 unsigned long timeout;
788 timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
790 if (tsens_version(priv) == VER_0) {
791 ret = regmap_field_read(priv->rf[TRDY], &trdy);
798 ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp);
802 *temp = code_to_degc(last_temp, s) * 1000;
805 } while (time_before(jiffies, timeout));
810 #ifdef CONFIG_DEBUG_FS
811 static int dbg_sensors_show(struct seq_file *s, void *data)
813 struct platform_device *pdev = s->private;
814 struct tsens_priv *priv = platform_get_drvdata(pdev);
817 seq_printf(s, "max: %2d\nnum: %2d\n\n",
818 priv->feat->max_sensors, priv->num_sensors);
820 seq_puts(s, " id slope offset\n--------------------------\n");
821 for (i = 0; i < priv->num_sensors; i++) {
822 seq_printf(s, "%8d %8d %8d\n", priv->sensor[i].hw_id,
823 priv->sensor[i].slope, priv->sensor[i].offset);
829 static int dbg_version_show(struct seq_file *s, void *data)
831 struct platform_device *pdev = s->private;
832 struct tsens_priv *priv = platform_get_drvdata(pdev);
833 u32 maj_ver, min_ver, step_ver;
836 if (tsens_version(priv) > VER_0_1) {
837 ret = regmap_field_read(priv->rf[VER_MAJOR], &maj_ver);
840 ret = regmap_field_read(priv->rf[VER_MINOR], &min_ver);
843 ret = regmap_field_read(priv->rf[VER_STEP], &step_ver);
846 seq_printf(s, "%d.%d.%d\n", maj_ver, min_ver, step_ver);
848 seq_printf(s, "0.%d.0\n", priv->feat->ver_major);
854 DEFINE_SHOW_ATTRIBUTE(dbg_version);
855 DEFINE_SHOW_ATTRIBUTE(dbg_sensors);
857 static void tsens_debug_init(struct platform_device *pdev)
859 struct tsens_priv *priv = platform_get_drvdata(pdev);
861 priv->debug_root = debugfs_lookup("tsens", NULL);
862 if (!priv->debug_root)
863 priv->debug_root = debugfs_create_dir("tsens", NULL);
865 /* A directory for each instance of the TSENS IP */
866 priv->debug = debugfs_create_dir(dev_name(&pdev->dev), priv->debug_root);
867 debugfs_create_file("version", 0444, priv->debug, pdev, &dbg_version_fops);
868 debugfs_create_file("sensors", 0444, priv->debug, pdev, &dbg_sensors_fops);
871 static inline void tsens_debug_init(struct platform_device *pdev) {}
874 static const struct regmap_config tsens_config = {
881 static const struct regmap_config tsens_srot_config = {
888 int __init init_common(struct tsens_priv *priv)
890 void __iomem *tm_base, *srot_base;
891 struct device *dev = priv->dev;
893 struct resource *res;
896 struct platform_device *op = of_find_device_by_node(priv->dev->of_node);
901 if (op->num_resources > 1) {
902 /* DT with separate SROT and TM address space */
904 res = platform_get_resource(op, IORESOURCE_MEM, 1);
905 srot_base = devm_ioremap_resource(dev, res);
906 if (IS_ERR(srot_base)) {
907 ret = PTR_ERR(srot_base);
911 priv->srot_map = devm_regmap_init_mmio(dev, srot_base,
913 if (IS_ERR(priv->srot_map)) {
914 ret = PTR_ERR(priv->srot_map);
918 /* old DTs where SROT and TM were in a contiguous 2K block */
919 priv->tm_offset = 0x1000;
922 if (tsens_version(priv) >= VER_0_1) {
923 res = platform_get_resource(op, IORESOURCE_MEM, 0);
924 tm_base = devm_ioremap_resource(dev, res);
925 if (IS_ERR(tm_base)) {
926 ret = PTR_ERR(tm_base);
930 priv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config);
931 } else { /* VER_0 share the same gcc regs using a syscon */
932 struct device *parent = priv->dev->parent;
935 priv->tm_map = syscon_node_to_regmap(parent->of_node);
938 if (IS_ERR_OR_NULL(priv->tm_map)) {
942 ret = PTR_ERR(priv->tm_map);
946 /* VER_0 have only tm_map */
948 priv->srot_map = priv->tm_map;
950 if (tsens_version(priv) > VER_0_1) {
951 for (i = VER_MAJOR; i <= VER_STEP; i++) {
952 priv->rf[i] = devm_regmap_field_alloc(dev, priv->srot_map,
954 if (IS_ERR(priv->rf[i])) {
955 ret = PTR_ERR(priv->rf[i]);
959 ret = regmap_field_read(priv->rf[VER_MINOR], &ver_minor);
964 priv->rf[TSENS_EN] = devm_regmap_field_alloc(dev, priv->srot_map,
965 priv->fields[TSENS_EN]);
966 if (IS_ERR(priv->rf[TSENS_EN])) {
967 ret = PTR_ERR(priv->rf[TSENS_EN]);
970 /* in VER_0 TSENS need to be explicitly enabled */
971 if (tsens_version(priv) == VER_0)
972 regmap_field_write(priv->rf[TSENS_EN], 1);
974 ret = regmap_field_read(priv->rf[TSENS_EN], &enabled);
978 dev_err(dev, "%s: device not enabled\n", __func__);
983 priv->rf[SENSOR_EN] = devm_regmap_field_alloc(dev, priv->srot_map,
984 priv->fields[SENSOR_EN]);
985 if (IS_ERR(priv->rf[SENSOR_EN])) {
986 ret = PTR_ERR(priv->rf[SENSOR_EN]);
989 priv->rf[INT_EN] = devm_regmap_field_alloc(dev, priv->tm_map,
990 priv->fields[INT_EN]);
991 if (IS_ERR(priv->rf[INT_EN])) {
992 ret = PTR_ERR(priv->rf[INT_EN]);
996 priv->rf[TSENS_SW_RST] =
997 devm_regmap_field_alloc(dev, priv->srot_map, priv->fields[TSENS_SW_RST]);
998 if (IS_ERR(priv->rf[TSENS_SW_RST])) {
999 ret = PTR_ERR(priv->rf[TSENS_SW_RST]);
1000 goto err_put_device;
1003 priv->rf[TRDY] = devm_regmap_field_alloc(dev, priv->tm_map, priv->fields[TRDY]);
1004 if (IS_ERR(priv->rf[TRDY])) {
1005 ret = PTR_ERR(priv->rf[TRDY]);
1006 goto err_put_device;
1009 /* This loop might need changes if enum regfield_ids is reordered */
1010 for (j = LAST_TEMP_0; j <= UP_THRESH_15; j += 16) {
1011 for (i = 0; i < priv->feat->max_sensors; i++) {
1014 priv->rf[idx] = devm_regmap_field_alloc(dev,
1017 if (IS_ERR(priv->rf[idx])) {
1018 ret = PTR_ERR(priv->rf[idx]);
1019 goto err_put_device;
1024 if (priv->feat->crit_int || tsens_version(priv) < VER_0_1) {
1025 /* Loop might need changes if enum regfield_ids is reordered */
1026 for (j = CRITICAL_STATUS_0; j <= CRIT_THRESH_15; j += 16) {
1027 for (i = 0; i < priv->feat->max_sensors; i++) {
1031 devm_regmap_field_alloc(dev,
1034 if (IS_ERR(priv->rf[idx])) {
1035 ret = PTR_ERR(priv->rf[idx]);
1036 goto err_put_device;
1042 if (tsens_version(priv) > VER_1_X && ver_minor > 2) {
1043 /* Watchdog is present only on v2.3+ */
1044 priv->feat->has_watchdog = 1;
1045 for (i = WDOG_BARK_STATUS; i <= CC_MON_MASK; i++) {
1046 priv->rf[i] = devm_regmap_field_alloc(dev, priv->tm_map,
1048 if (IS_ERR(priv->rf[i])) {
1049 ret = PTR_ERR(priv->rf[i]);
1050 goto err_put_device;
1054 * Watchdog is already enabled, unmask the bark.
1055 * Disable cycle completion monitoring
1057 regmap_field_write(priv->rf[WDOG_BARK_MASK], 0);
1058 regmap_field_write(priv->rf[CC_MON_MASK], 1);
1061 spin_lock_init(&priv->ul_lock);
1063 /* VER_0 interrupt doesn't need to be enabled */
1064 if (tsens_version(priv) >= VER_0_1)
1065 tsens_enable_irq(priv);
1068 put_device(&op->dev);
1072 static int tsens_get_temp(struct thermal_zone_device *tz, int *temp)
1074 struct tsens_sensor *s = thermal_zone_device_priv(tz);
1075 struct tsens_priv *priv = s->priv;
1077 return priv->ops->get_temp(s, temp);
1080 static int __maybe_unused tsens_suspend(struct device *dev)
1082 struct tsens_priv *priv = dev_get_drvdata(dev);
1084 if (priv->ops && priv->ops->suspend)
1085 return priv->ops->suspend(priv);
1090 static int __maybe_unused tsens_resume(struct device *dev)
1092 struct tsens_priv *priv = dev_get_drvdata(dev);
1094 if (priv->ops && priv->ops->resume)
1095 return priv->ops->resume(priv);
1100 static SIMPLE_DEV_PM_OPS(tsens_pm_ops, tsens_suspend, tsens_resume);
1102 static const struct of_device_id tsens_table[] = {
1104 .compatible = "qcom,ipq8064-tsens",
1107 .compatible = "qcom,ipq8074-tsens",
1108 .data = &data_ipq8074,
1110 .compatible = "qcom,mdm9607-tsens",
1113 .compatible = "qcom,msm8226-tsens",
1116 .compatible = "qcom,msm8909-tsens",
1119 .compatible = "qcom,msm8916-tsens",
1122 .compatible = "qcom,msm8939-tsens",
1125 .compatible = "qcom,msm8956-tsens",
1128 .compatible = "qcom,msm8960-tsens",
1131 .compatible = "qcom,msm8974-tsens",
1134 .compatible = "qcom,msm8976-tsens",
1137 .compatible = "qcom,msm8996-tsens",
1140 .compatible = "qcom,tsens-v1",
1141 .data = &data_tsens_v1,
1143 .compatible = "qcom,tsens-v2",
1144 .data = &data_tsens_v2,
1148 MODULE_DEVICE_TABLE(of, tsens_table);
1150 static const struct thermal_zone_device_ops tsens_of_ops = {
1151 .get_temp = tsens_get_temp,
1152 .set_trips = tsens_set_trips,
1155 static int tsens_register_irq(struct tsens_priv *priv, char *irqname,
1156 irq_handler_t thread_fn)
1158 struct platform_device *pdev;
1161 pdev = of_find_device_by_node(priv->dev->of_node);
1165 irq = platform_get_irq_byname(pdev, irqname);
1168 /* For old DTs with no IRQ defined */
1172 /* VER_0 interrupt is TRIGGER_RISING, VER_0_1 and up is ONESHOT */
1173 if (tsens_version(priv) == VER_0)
1174 ret = devm_request_threaded_irq(&pdev->dev, irq,
1176 IRQF_TRIGGER_RISING,
1177 dev_name(&pdev->dev),
1180 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1181 thread_fn, IRQF_ONESHOT,
1182 dev_name(&pdev->dev),
1186 dev_err(&pdev->dev, "%s: failed to get irq\n",
1189 enable_irq_wake(irq);
1192 put_device(&pdev->dev);
1196 static int tsens_register(struct tsens_priv *priv)
1199 struct thermal_zone_device *tzd;
1201 for (i = 0; i < priv->num_sensors; i++) {
1202 priv->sensor[i].priv = priv;
1203 tzd = devm_thermal_of_zone_register(priv->dev, priv->sensor[i].hw_id,
1208 priv->sensor[i].tzd = tzd;
1209 if (priv->ops->enable)
1210 priv->ops->enable(priv, i);
1212 devm_thermal_add_hwmon_sysfs(priv->dev, tzd);
1215 /* VER_0 require to set MIN and MAX THRESH
1216 * These 2 regs are set using the:
1217 * - CRIT_THRESH_0 for MAX THRESH hardcoded to 120°C
1218 * - CRIT_THRESH_1 for MIN THRESH hardcoded to 0°C
1220 if (tsens_version(priv) < VER_0_1) {
1221 regmap_field_write(priv->rf[CRIT_THRESH_0],
1222 tsens_mC_to_hw(priv->sensor, 120000));
1224 regmap_field_write(priv->rf[CRIT_THRESH_1],
1225 tsens_mC_to_hw(priv->sensor, 0));
1228 if (priv->feat->combo_int) {
1229 ret = tsens_register_irq(priv, "combined",
1230 tsens_combined_irq_thread);
1232 ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
1236 if (priv->feat->crit_int)
1237 ret = tsens_register_irq(priv, "critical",
1238 tsens_critical_irq_thread);
1244 static int tsens_probe(struct platform_device *pdev)
1248 struct device_node *np;
1249 struct tsens_priv *priv;
1250 const struct tsens_plat_data *data;
1251 const struct of_device_id *id;
1254 if (pdev->dev.of_node)
1257 dev = pdev->dev.parent;
1261 id = of_match_node(tsens_table, np);
1267 num_sensors = data->num_sensors;
1270 of_property_read_u32(np, "#qcom,sensors", &num_sensors);
1272 if (num_sensors <= 0) {
1273 dev_err(dev, "%s: invalid number of sensors\n", __func__);
1277 priv = devm_kzalloc(dev,
1278 struct_size(priv, sensor, num_sensors),
1284 priv->num_sensors = num_sensors;
1285 priv->ops = data->ops;
1286 for (i = 0; i < priv->num_sensors; i++) {
1288 priv->sensor[i].hw_id = data->hw_ids[i];
1290 priv->sensor[i].hw_id = i;
1292 priv->feat = data->feat;
1293 priv->fields = data->fields;
1295 platform_set_drvdata(pdev, priv);
1297 if (!priv->ops || !priv->ops->init || !priv->ops->get_temp)
1300 ret = priv->ops->init(priv);
1302 dev_err(dev, "%s: init failed\n", __func__);
1306 if (priv->ops->calibrate) {
1307 ret = priv->ops->calibrate(priv);
1309 if (ret != -EPROBE_DEFER)
1310 dev_err(dev, "%s: calibration failed\n", __func__);
1315 ret = tsens_register(priv);
1317 tsens_debug_init(pdev);
1322 static void tsens_remove(struct platform_device *pdev)
1324 struct tsens_priv *priv = platform_get_drvdata(pdev);
1326 debugfs_remove_recursive(priv->debug_root);
1327 tsens_disable_irq(priv);
1328 if (priv->ops->disable)
1329 priv->ops->disable(priv);
1332 static struct platform_driver tsens_driver = {
1333 .probe = tsens_probe,
1334 .remove_new = tsens_remove,
1336 .name = "qcom-tsens",
1337 .pm = &tsens_pm_ops,
1338 .of_match_table = tsens_table,
1341 module_platform_driver(tsens_driver);
1343 MODULE_LICENSE("GPL v2");
1344 MODULE_DESCRIPTION("QCOM Temperature Sensor driver");
1345 MODULE_ALIAS("platform:qcom-tsens");