1 // SPDX-License-Identifier: GPL-2.0-only
3 * The On Chip Memory (OCMEM) allocator allows various clients to allocate
4 * memory from OCMEM based on performance, latency and power requirements.
5 * This is typically used by the GPU, camera/video, and audio components on
6 * some Snapdragon SoCs.
8 * Copyright (C) 2019 Brian Masney <masneyb@onstation.org>
9 * Copyright (C) 2015 Red Hat. Author: Rob Clark <robdclark@gmail.com>
12 #include <linux/bitfield.h>
13 #include <linux/clk.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/qcom_scm.h>
20 #include <linux/sizes.h>
21 #include <linux/slab.h>
22 #include <linux/types.h>
23 #include <soc/qcom/ocmem.h>
28 MODE_DEFAULT = WIDE_MODE,
31 enum ocmem_macro_state {
40 enum region_mode mode;
41 unsigned int num_macros;
42 enum ocmem_macro_state macro_state[4];
43 unsigned long macro_size;
44 unsigned long region_size;
49 unsigned long macro_size;
54 const struct ocmem_config *config;
55 struct resource *memory;
57 unsigned int num_ports;
58 unsigned int num_macros;
60 struct ocmem_region *regions;
61 unsigned long active_allocations;
64 #define OCMEM_MIN_ALIGN SZ_64K
65 #define OCMEM_MIN_ALLOC SZ_64K
67 #define OCMEM_REG_HW_VERSION 0x00000000
68 #define OCMEM_REG_HW_PROFILE 0x00000004
70 #define OCMEM_REG_REGION_MODE_CTL 0x00001000
71 #define OCMEM_REGION_MODE_CTL_REG0_THIN 0x00000001
72 #define OCMEM_REGION_MODE_CTL_REG1_THIN 0x00000002
73 #define OCMEM_REGION_MODE_CTL_REG2_THIN 0x00000004
74 #define OCMEM_REGION_MODE_CTL_REG3_THIN 0x00000008
76 #define OCMEM_REG_GFX_MPU_START 0x00001004
77 #define OCMEM_REG_GFX_MPU_END 0x00001008
79 #define OCMEM_HW_VERSION_MAJOR(val) FIELD_GET(GENMASK(31, 28), val)
80 #define OCMEM_HW_VERSION_MINOR(val) FIELD_GET(GENMASK(27, 16), val)
81 #define OCMEM_HW_VERSION_STEP(val) FIELD_GET(GENMASK(15, 0), val)
83 #define OCMEM_HW_PROFILE_NUM_PORTS(val) FIELD_GET(0x0000000f, (val))
84 #define OCMEM_HW_PROFILE_NUM_MACROS(val) FIELD_GET(0x00003f00, (val))
86 #define OCMEM_HW_PROFILE_LAST_REGN_HALFSIZE 0x00010000
87 #define OCMEM_HW_PROFILE_INTERLEAVING 0x00020000
88 #define OCMEM_REG_GEN_STATUS 0x0000000c
90 #define OCMEM_REG_PSGSC_STATUS 0x00000038
91 #define OCMEM_REG_PSGSC_CTL(i0) (0x0000003c + 0x1*(i0))
93 #define OCMEM_PSGSC_CTL_MACRO0_MODE(val) FIELD_PREP(0x00000007, (val))
94 #define OCMEM_PSGSC_CTL_MACRO1_MODE(val) FIELD_PREP(0x00000070, (val))
95 #define OCMEM_PSGSC_CTL_MACRO2_MODE(val) FIELD_PREP(0x00000700, (val))
96 #define OCMEM_PSGSC_CTL_MACRO3_MODE(val) FIELD_PREP(0x00007000, (val))
98 #define OCMEM_CLK_CORE_IDX 0
99 static struct clk_bulk_data ocmem_clks[] = {
108 static inline void ocmem_write(struct ocmem *ocmem, u32 reg, u32 data)
110 writel(data, ocmem->mmio + reg);
113 static inline u32 ocmem_read(struct ocmem *ocmem, u32 reg)
115 return readl(ocmem->mmio + reg);
118 static void update_ocmem(struct ocmem *ocmem)
120 uint32_t region_mode_ctrl = 0x0;
123 if (!qcom_scm_ocmem_lock_available()) {
124 for (i = 0; i < ocmem->config->num_regions; i++) {
125 struct ocmem_region *region = &ocmem->regions[i];
127 if (region->mode == THIN_MODE)
128 region_mode_ctrl |= BIT(i);
131 dev_dbg(ocmem->dev, "ocmem_region_mode_control %x\n",
133 ocmem_write(ocmem, OCMEM_REG_REGION_MODE_CTL, region_mode_ctrl);
136 for (i = 0; i < ocmem->config->num_regions; i++) {
137 struct ocmem_region *region = &ocmem->regions[i];
140 data = OCMEM_PSGSC_CTL_MACRO0_MODE(region->macro_state[0]) |
141 OCMEM_PSGSC_CTL_MACRO1_MODE(region->macro_state[1]) |
142 OCMEM_PSGSC_CTL_MACRO2_MODE(region->macro_state[2]) |
143 OCMEM_PSGSC_CTL_MACRO3_MODE(region->macro_state[3]);
145 ocmem_write(ocmem, OCMEM_REG_PSGSC_CTL(i), data);
149 static unsigned long phys_to_offset(struct ocmem *ocmem,
152 if (addr < ocmem->memory->start || addr >= ocmem->memory->end)
155 return addr - ocmem->memory->start;
158 static unsigned long device_address(struct ocmem *ocmem,
159 enum ocmem_client client,
162 WARN_ON(client != OCMEM_GRAPHICS);
164 /* TODO: gpu uses phys_to_offset, but others do not.. */
165 return phys_to_offset(ocmem, addr);
168 static void update_range(struct ocmem *ocmem, struct ocmem_buf *buf,
169 enum ocmem_macro_state mstate, enum region_mode rmode)
171 unsigned long offset = 0;
174 for (i = 0; i < ocmem->config->num_regions; i++) {
175 struct ocmem_region *region = &ocmem->regions[i];
177 if (buf->offset <= offset && offset < buf->offset + buf->len)
178 region->mode = rmode;
180 for (j = 0; j < region->num_macros; j++) {
181 if (buf->offset <= offset &&
182 offset < buf->offset + buf->len)
183 region->macro_state[j] = mstate;
185 offset += region->macro_size;
192 struct ocmem *of_get_ocmem(struct device *dev)
194 struct platform_device *pdev;
195 struct device_node *devnode;
198 devnode = of_parse_phandle(dev->of_node, "sram", 0);
199 if (!devnode || !devnode->parent) {
200 dev_err(dev, "Cannot look up sram phandle\n");
201 of_node_put(devnode);
202 return ERR_PTR(-ENODEV);
205 pdev = of_find_device_by_node(devnode->parent);
207 dev_err(dev, "Cannot find device node %s\n", devnode->name);
208 of_node_put(devnode);
209 return ERR_PTR(-EPROBE_DEFER);
211 of_node_put(devnode);
213 ocmem = platform_get_drvdata(pdev);
215 dev_err(dev, "Cannot get ocmem\n");
216 put_device(&pdev->dev);
217 return ERR_PTR(-ENODEV);
221 EXPORT_SYMBOL(of_get_ocmem);
223 struct ocmem_buf *ocmem_allocate(struct ocmem *ocmem, enum ocmem_client client,
226 struct ocmem_buf *buf;
229 /* TODO: add support for other clients... */
230 if (WARN_ON(client != OCMEM_GRAPHICS))
231 return ERR_PTR(-ENODEV);
233 if (size < OCMEM_MIN_ALLOC || !IS_ALIGNED(size, OCMEM_MIN_ALIGN))
234 return ERR_PTR(-EINVAL);
236 if (test_and_set_bit_lock(BIT(client), &ocmem->active_allocations))
237 return ERR_PTR(-EBUSY);
239 buf = kzalloc(sizeof(*buf), GFP_KERNEL);
246 buf->addr = device_address(ocmem, client, buf->offset);
249 update_range(ocmem, buf, CORE_ON, WIDE_MODE);
251 if (qcom_scm_ocmem_lock_available()) {
252 ret = qcom_scm_ocmem_lock(QCOM_SCM_OCMEM_GRAPHICS_ID,
253 buf->offset, buf->len, WIDE_MODE);
255 dev_err(ocmem->dev, "could not lock: %d\n", ret);
260 ocmem_write(ocmem, OCMEM_REG_GFX_MPU_START, buf->offset);
261 ocmem_write(ocmem, OCMEM_REG_GFX_MPU_END,
262 buf->offset + buf->len);
265 dev_dbg(ocmem->dev, "using %ldK of OCMEM at 0x%08lx for client %d\n",
266 size / 1024, buf->addr, client);
273 clear_bit_unlock(BIT(client), &ocmem->active_allocations);
277 EXPORT_SYMBOL(ocmem_allocate);
279 void ocmem_free(struct ocmem *ocmem, enum ocmem_client client,
280 struct ocmem_buf *buf)
282 /* TODO: add support for other clients... */
283 if (WARN_ON(client != OCMEM_GRAPHICS))
286 update_range(ocmem, buf, CLK_OFF, MODE_DEFAULT);
288 if (qcom_scm_ocmem_lock_available()) {
291 ret = qcom_scm_ocmem_unlock(QCOM_SCM_OCMEM_GRAPHICS_ID,
292 buf->offset, buf->len);
294 dev_err(ocmem->dev, "could not unlock: %d\n", ret);
296 ocmem_write(ocmem, OCMEM_REG_GFX_MPU_START, 0x0);
297 ocmem_write(ocmem, OCMEM_REG_GFX_MPU_END, 0x0);
302 clear_bit_unlock(BIT(client), &ocmem->active_allocations);
304 EXPORT_SYMBOL(ocmem_free);
306 static int ocmem_dev_probe(struct platform_device *pdev)
308 struct device *dev = &pdev->dev;
309 unsigned long reg, region_size;
310 int i, j, ret, num_banks;
311 struct resource *res;
314 if (!qcom_scm_is_available())
315 return -EPROBE_DEFER;
317 ocmem = devm_kzalloc(dev, sizeof(*ocmem), GFP_KERNEL);
322 ocmem->config = device_get_match_data(dev);
324 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(ocmem_clks), ocmem_clks);
326 if (ret != -EPROBE_DEFER)
327 dev_err(dev, "Unable to get clocks\n");
332 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
333 ocmem->mmio = devm_ioremap_resource(&pdev->dev, res);
334 if (IS_ERR(ocmem->mmio)) {
335 dev_err(&pdev->dev, "Failed to ioremap ocmem_ctrl resource\n");
336 return PTR_ERR(ocmem->mmio);
339 ocmem->memory = platform_get_resource_byname(pdev, IORESOURCE_MEM,
341 if (!ocmem->memory) {
342 dev_err(dev, "Could not get mem region\n");
346 /* The core clock is synchronous with graphics */
347 WARN_ON(clk_set_rate(ocmem_clks[OCMEM_CLK_CORE_IDX].clk, 1000) < 0);
349 ret = clk_bulk_prepare_enable(ARRAY_SIZE(ocmem_clks), ocmem_clks);
351 dev_info(ocmem->dev, "Failed to enable clocks\n");
355 if (qcom_scm_restore_sec_cfg_available()) {
356 dev_dbg(dev, "configuring scm\n");
357 ret = qcom_scm_restore_sec_cfg(QCOM_SCM_OCMEM_DEV_ID, 0);
359 dev_err(dev, "Could not enable secure configuration\n");
360 goto err_clk_disable;
364 reg = ocmem_read(ocmem, OCMEM_REG_HW_VERSION);
365 dev_dbg(dev, "OCMEM hardware version: %lu.%lu.%lu\n",
366 OCMEM_HW_VERSION_MAJOR(reg),
367 OCMEM_HW_VERSION_MINOR(reg),
368 OCMEM_HW_VERSION_STEP(reg));
370 reg = ocmem_read(ocmem, OCMEM_REG_HW_PROFILE);
371 ocmem->num_ports = OCMEM_HW_PROFILE_NUM_PORTS(reg);
372 ocmem->num_macros = OCMEM_HW_PROFILE_NUM_MACROS(reg);
373 ocmem->interleaved = !!(reg & OCMEM_HW_PROFILE_INTERLEAVING);
375 num_banks = ocmem->num_ports / 2;
376 region_size = ocmem->config->macro_size * num_banks;
378 dev_info(dev, "%u ports, %u regions, %u macros, %sinterleaved\n",
379 ocmem->num_ports, ocmem->config->num_regions,
380 ocmem->num_macros, ocmem->interleaved ? "" : "not ");
382 ocmem->regions = devm_kcalloc(dev, ocmem->config->num_regions,
383 sizeof(struct ocmem_region), GFP_KERNEL);
384 if (!ocmem->regions) {
386 goto err_clk_disable;
389 for (i = 0; i < ocmem->config->num_regions; i++) {
390 struct ocmem_region *region = &ocmem->regions[i];
392 if (WARN_ON(num_banks > ARRAY_SIZE(region->macro_state))) {
394 goto err_clk_disable;
397 region->mode = MODE_DEFAULT;
398 region->num_macros = num_banks;
400 if (i == (ocmem->config->num_regions - 1) &&
401 reg & OCMEM_HW_PROFILE_LAST_REGN_HALFSIZE) {
402 region->macro_size = ocmem->config->macro_size / 2;
403 region->region_size = region_size / 2;
405 region->macro_size = ocmem->config->macro_size;
406 region->region_size = region_size;
409 for (j = 0; j < ARRAY_SIZE(region->macro_state); j++)
410 region->macro_state[j] = CLK_OFF;
413 platform_set_drvdata(pdev, ocmem);
418 clk_bulk_disable_unprepare(ARRAY_SIZE(ocmem_clks), ocmem_clks);
422 static int ocmem_dev_remove(struct platform_device *pdev)
424 clk_bulk_disable_unprepare(ARRAY_SIZE(ocmem_clks), ocmem_clks);
429 static const struct ocmem_config ocmem_8974_config = {
431 .macro_size = SZ_128K,
434 static const struct of_device_id ocmem_of_match[] = {
435 { .compatible = "qcom,msm8974-ocmem", .data = &ocmem_8974_config },
439 MODULE_DEVICE_TABLE(of, ocmem_of_match);
441 static struct platform_driver ocmem_driver = {
442 .probe = ocmem_dev_probe,
443 .remove = ocmem_dev_remove,
446 .of_match_table = ocmem_of_match,
450 module_platform_driver(ocmem_driver);
452 MODULE_DESCRIPTION("On Chip Memory (OCMEM) allocator for some Snapdragon SoCs");
453 MODULE_LICENSE("GPL v2");