1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
3 #include <linux/module.h>
4 #include <crypto/internal/rsa.h>
5 #include <crypto/internal/akcipher.h>
6 #include <crypto/akcipher.h>
7 #include <crypto/kpp.h>
8 #include <crypto/internal/kpp.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/fips.h>
12 #include <crypto/scatterwalk.h>
13 #include "icp_qat_fw_pke.h"
14 #include "adf_accel_devices.h"
15 #include "adf_transport.h"
16 #include "adf_common_drv.h"
17 #include "qat_crypto.h"
19 static DEFINE_MUTEX(algs_lock);
20 static unsigned int active_devs;
22 struct qat_rsa_input_params {
44 } __packed __aligned(64);
46 struct qat_rsa_output_params {
56 } __packed __aligned(64);
77 struct qat_crypto_instance *inst;
78 } __packed __aligned(64);
80 struct qat_dh_input_params {
93 } __packed __aligned(64);
95 struct qat_dh_output_params {
100 } __packed __aligned(64);
111 struct qat_crypto_instance *inst;
112 } __packed __aligned(64);
114 struct qat_asym_request {
116 struct qat_rsa_input_params rsa;
117 struct qat_dh_input_params dh;
120 struct qat_rsa_output_params rsa;
121 struct qat_dh_output_params dh;
127 struct icp_qat_fw_pke_request req;
129 struct qat_rsa_ctx *rsa;
130 struct qat_dh_ctx *dh;
133 struct akcipher_request *rsa;
134 struct kpp_request *dh;
137 void (*cb)(struct icp_qat_fw_pke_resp *resp);
140 static void qat_dh_cb(struct icp_qat_fw_pke_resp *resp)
142 struct qat_asym_request *req = (void *)(__force long)resp->opaque;
143 struct kpp_request *areq = req->areq.dh;
144 struct device *dev = &GET_DEV(req->ctx.dh->inst->accel_dev);
145 int err = ICP_QAT_FW_PKE_RESP_PKE_STAT_GET(
146 resp->pke_resp_hdr.comn_resp_flags);
148 err = (err == ICP_QAT_FW_COMN_STATUS_FLAG_OK) ? 0 : -EINVAL;
152 dma_free_coherent(dev, req->ctx.dh->p_size,
153 req->src_align, req->in.dh.in.b);
155 dma_unmap_single(dev, req->in.dh.in.b,
156 req->ctx.dh->p_size, DMA_TO_DEVICE);
159 areq->dst_len = req->ctx.dh->p_size;
160 if (req->dst_align) {
161 scatterwalk_map_and_copy(req->dst_align, areq->dst, 0,
164 dma_free_coherent(dev, req->ctx.dh->p_size, req->dst_align,
167 dma_unmap_single(dev, req->out.dh.r, req->ctx.dh->p_size,
171 dma_unmap_single(dev, req->phy_in, sizeof(struct qat_dh_input_params),
173 dma_unmap_single(dev, req->phy_out,
174 sizeof(struct qat_dh_output_params),
177 kpp_request_complete(areq, err);
180 #define PKE_DH_1536 0x390c1a49
181 #define PKE_DH_G2_1536 0x2e0b1a3e
182 #define PKE_DH_2048 0x4d0c1a60
183 #define PKE_DH_G2_2048 0x3e0b1a55
184 #define PKE_DH_3072 0x510c1a77
185 #define PKE_DH_G2_3072 0x3a0b1a6c
186 #define PKE_DH_4096 0x690c1a8e
187 #define PKE_DH_G2_4096 0x4a0b1a83
189 static unsigned long qat_dh_fn_id(unsigned int len, bool g2)
191 unsigned int bitslen = len << 3;
195 return g2 ? PKE_DH_G2_1536 : PKE_DH_1536;
197 return g2 ? PKE_DH_G2_2048 : PKE_DH_2048;
199 return g2 ? PKE_DH_G2_3072 : PKE_DH_3072;
201 return g2 ? PKE_DH_G2_4096 : PKE_DH_4096;
207 static int qat_dh_compute_value(struct kpp_request *req)
209 struct crypto_kpp *tfm = crypto_kpp_reqtfm(req);
210 struct qat_dh_ctx *ctx = kpp_tfm_ctx(tfm);
211 struct qat_crypto_instance *inst = ctx->inst;
212 struct device *dev = &GET_DEV(inst->accel_dev);
213 struct qat_asym_request *qat_req =
214 PTR_ALIGN(kpp_request_ctx(req), 64);
215 struct icp_qat_fw_pke_request *msg = &qat_req->req;
217 int n_input_params = 0;
219 if (unlikely(!ctx->xa))
222 if (req->dst_len < ctx->p_size) {
223 req->dst_len = ctx->p_size;
226 memset(msg, '\0', sizeof(*msg));
227 ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET(msg->pke_hdr,
228 ICP_QAT_FW_COMN_REQ_FLAG_SET);
230 msg->pke_hdr.cd_pars.func_id = qat_dh_fn_id(ctx->p_size,
231 !req->src && ctx->g2);
232 if (unlikely(!msg->pke_hdr.cd_pars.func_id))
235 qat_req->cb = qat_dh_cb;
236 qat_req->ctx.dh = ctx;
237 qat_req->areq.dh = req;
238 msg->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_PKE;
239 msg->pke_hdr.comn_req_flags =
240 ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_PTR_TYPE_FLAT,
241 QAT_COMN_CD_FLD_TYPE_64BIT_ADR);
244 * If no source is provided use g as base
247 qat_req->in.dh.in.xa = ctx->dma_xa;
248 qat_req->in.dh.in.p = ctx->dma_p;
252 qat_req->in.dh.in_g2.xa = ctx->dma_xa;
253 qat_req->in.dh.in_g2.p = ctx->dma_p;
256 qat_req->in.dh.in.b = ctx->dma_g;
257 qat_req->in.dh.in.xa = ctx->dma_xa;
258 qat_req->in.dh.in.p = ctx->dma_p;
266 * src can be of any size in valid range, but HW expects it to
267 * be the same as modulo p so in case it is different we need
268 * to allocate a new buf and copy src data.
269 * In other case we just need to map the user provided buffer.
270 * Also need to make sure that it is in contiguous buffer.
272 if (sg_is_last(req->src) && req->src_len == ctx->p_size) {
273 qat_req->src_align = NULL;
274 qat_req->in.dh.in.b = dma_map_single(dev,
278 if (unlikely(dma_mapping_error(dev,
279 qat_req->in.dh.in.b)))
283 int shift = ctx->p_size - req->src_len;
285 qat_req->src_align = dma_alloc_coherent(dev,
287 &qat_req->in.dh.in.b,
289 if (unlikely(!qat_req->src_align))
292 scatterwalk_map_and_copy(qat_req->src_align + shift,
293 req->src, 0, req->src_len, 0);
297 * dst can be of any size in valid range, but HW expects it to be the
298 * same as modulo m so in case it is different we need to allocate a
299 * new buf and copy src data.
300 * In other case we just need to map the user provided buffer.
301 * Also need to make sure that it is in contiguous buffer.
303 if (sg_is_last(req->dst) && req->dst_len == ctx->p_size) {
304 qat_req->dst_align = NULL;
305 qat_req->out.dh.r = dma_map_single(dev, sg_virt(req->dst),
309 if (unlikely(dma_mapping_error(dev, qat_req->out.dh.r)))
313 qat_req->dst_align = dma_alloc_coherent(dev, ctx->p_size,
316 if (unlikely(!qat_req->dst_align))
320 qat_req->in.dh.in_tab[n_input_params] = 0;
321 qat_req->out.dh.out_tab[1] = 0;
322 /* Mapping in.in.b or in.in_g2.xa is the same */
323 qat_req->phy_in = dma_map_single(dev, &qat_req->in.dh.in.b,
324 sizeof(qat_req->in.dh.in.b),
326 if (unlikely(dma_mapping_error(dev, qat_req->phy_in)))
329 qat_req->phy_out = dma_map_single(dev, &qat_req->out.dh.r,
330 sizeof(qat_req->out.dh.r),
332 if (unlikely(dma_mapping_error(dev, qat_req->phy_out)))
333 goto unmap_in_params;
335 msg->pke_mid.src_data_addr = qat_req->phy_in;
336 msg->pke_mid.dest_data_addr = qat_req->phy_out;
337 msg->pke_mid.opaque = (u64)(__force long)qat_req;
338 msg->input_param_count = n_input_params;
339 msg->output_param_count = 1;
342 ret = adf_send_message(ctx->inst->pke_tx, (u32 *)msg);
343 } while (ret == -EBUSY && ctr++ < 100);
348 if (!dma_mapping_error(dev, qat_req->phy_out))
349 dma_unmap_single(dev, qat_req->phy_out,
350 sizeof(struct qat_dh_output_params),
353 if (!dma_mapping_error(dev, qat_req->phy_in))
354 dma_unmap_single(dev, qat_req->phy_in,
355 sizeof(struct qat_dh_input_params),
358 if (qat_req->dst_align)
359 dma_free_coherent(dev, ctx->p_size, qat_req->dst_align,
362 if (!dma_mapping_error(dev, qat_req->out.dh.r))
363 dma_unmap_single(dev, qat_req->out.dh.r, ctx->p_size,
367 if (qat_req->src_align)
368 dma_free_coherent(dev, ctx->p_size, qat_req->src_align,
369 qat_req->in.dh.in.b);
371 if (!dma_mapping_error(dev, qat_req->in.dh.in.b))
372 dma_unmap_single(dev, qat_req->in.dh.in.b,
379 static int qat_dh_check_params_length(unsigned int p_len)
391 static int qat_dh_set_params(struct qat_dh_ctx *ctx, struct dh *params)
393 struct qat_crypto_instance *inst = ctx->inst;
394 struct device *dev = &GET_DEV(inst->accel_dev);
396 if (qat_dh_check_params_length(params->p_size << 3))
399 ctx->p_size = params->p_size;
400 ctx->p = dma_alloc_coherent(dev, ctx->p_size, &ctx->dma_p, GFP_KERNEL);
403 memcpy(ctx->p, params->p, ctx->p_size);
405 /* If g equals 2 don't copy it */
406 if (params->g_size == 1 && *(char *)params->g == 0x02) {
411 ctx->g = dma_alloc_coherent(dev, ctx->p_size, &ctx->dma_g, GFP_KERNEL);
414 memcpy(ctx->g + (ctx->p_size - params->g_size), params->g,
420 static void qat_dh_clear_ctx(struct device *dev, struct qat_dh_ctx *ctx)
423 dma_free_coherent(dev, ctx->p_size, ctx->g, ctx->dma_g);
427 dma_free_coherent(dev, ctx->p_size, ctx->xa, ctx->dma_xa);
431 dma_free_coherent(dev, ctx->p_size, ctx->p, ctx->dma_p);
438 static int qat_dh_set_secret(struct crypto_kpp *tfm, const void *buf,
441 struct qat_dh_ctx *ctx = kpp_tfm_ctx(tfm);
442 struct device *dev = &GET_DEV(ctx->inst->accel_dev);
446 if (crypto_dh_decode_key(buf, len, ¶ms) < 0)
449 /* Free old secret if any */
450 qat_dh_clear_ctx(dev, ctx);
452 ret = qat_dh_set_params(ctx, ¶ms);
456 ctx->xa = dma_alloc_coherent(dev, ctx->p_size, &ctx->dma_xa,
462 memcpy(ctx->xa + (ctx->p_size - params.key_size), params.key,
468 qat_dh_clear_ctx(dev, ctx);
472 static unsigned int qat_dh_max_size(struct crypto_kpp *tfm)
474 struct qat_dh_ctx *ctx = kpp_tfm_ctx(tfm);
479 static int qat_dh_init_tfm(struct crypto_kpp *tfm)
481 struct qat_dh_ctx *ctx = kpp_tfm_ctx(tfm);
482 struct qat_crypto_instance *inst =
483 qat_crypto_get_instance_node(get_current_node());
494 static void qat_dh_exit_tfm(struct crypto_kpp *tfm)
496 struct qat_dh_ctx *ctx = kpp_tfm_ctx(tfm);
497 struct device *dev = &GET_DEV(ctx->inst->accel_dev);
499 qat_dh_clear_ctx(dev, ctx);
500 qat_crypto_put_instance(ctx->inst);
503 static void qat_rsa_cb(struct icp_qat_fw_pke_resp *resp)
505 struct qat_asym_request *req = (void *)(__force long)resp->opaque;
506 struct akcipher_request *areq = req->areq.rsa;
507 struct device *dev = &GET_DEV(req->ctx.rsa->inst->accel_dev);
508 int err = ICP_QAT_FW_PKE_RESP_PKE_STAT_GET(
509 resp->pke_resp_hdr.comn_resp_flags);
511 err = (err == ICP_QAT_FW_COMN_STATUS_FLAG_OK) ? 0 : -EINVAL;
514 dma_free_coherent(dev, req->ctx.rsa->key_sz, req->src_align,
517 dma_unmap_single(dev, req->in.rsa.enc.m, req->ctx.rsa->key_sz,
520 areq->dst_len = req->ctx.rsa->key_sz;
521 if (req->dst_align) {
522 scatterwalk_map_and_copy(req->dst_align, areq->dst, 0,
525 dma_free_coherent(dev, req->ctx.rsa->key_sz, req->dst_align,
528 dma_unmap_single(dev, req->out.rsa.enc.c, req->ctx.rsa->key_sz,
532 dma_unmap_single(dev, req->phy_in, sizeof(struct qat_rsa_input_params),
534 dma_unmap_single(dev, req->phy_out,
535 sizeof(struct qat_rsa_output_params),
538 akcipher_request_complete(areq, err);
541 void qat_alg_asym_callback(void *_resp)
543 struct icp_qat_fw_pke_resp *resp = _resp;
544 struct qat_asym_request *areq = (void *)(__force long)resp->opaque;
549 #define PKE_RSA_EP_512 0x1c161b21
550 #define PKE_RSA_EP_1024 0x35111bf7
551 #define PKE_RSA_EP_1536 0x4d111cdc
552 #define PKE_RSA_EP_2048 0x6e111dba
553 #define PKE_RSA_EP_3072 0x7d111ea3
554 #define PKE_RSA_EP_4096 0xa5101f7e
556 static unsigned long qat_rsa_enc_fn_id(unsigned int len)
558 unsigned int bitslen = len << 3;
562 return PKE_RSA_EP_512;
564 return PKE_RSA_EP_1024;
566 return PKE_RSA_EP_1536;
568 return PKE_RSA_EP_2048;
570 return PKE_RSA_EP_3072;
572 return PKE_RSA_EP_4096;
578 #define PKE_RSA_DP1_512 0x1c161b3c
579 #define PKE_RSA_DP1_1024 0x35111c12
580 #define PKE_RSA_DP1_1536 0x4d111cf7
581 #define PKE_RSA_DP1_2048 0x6e111dda
582 #define PKE_RSA_DP1_3072 0x7d111ebe
583 #define PKE_RSA_DP1_4096 0xa5101f98
585 static unsigned long qat_rsa_dec_fn_id(unsigned int len)
587 unsigned int bitslen = len << 3;
591 return PKE_RSA_DP1_512;
593 return PKE_RSA_DP1_1024;
595 return PKE_RSA_DP1_1536;
597 return PKE_RSA_DP1_2048;
599 return PKE_RSA_DP1_3072;
601 return PKE_RSA_DP1_4096;
607 #define PKE_RSA_DP2_512 0x1c131b57
608 #define PKE_RSA_DP2_1024 0x26131c2d
609 #define PKE_RSA_DP2_1536 0x45111d12
610 #define PKE_RSA_DP2_2048 0x59121dfa
611 #define PKE_RSA_DP2_3072 0x81121ed9
612 #define PKE_RSA_DP2_4096 0xb1111fb2
614 static unsigned long qat_rsa_dec_fn_id_crt(unsigned int len)
616 unsigned int bitslen = len << 3;
620 return PKE_RSA_DP2_512;
622 return PKE_RSA_DP2_1024;
624 return PKE_RSA_DP2_1536;
626 return PKE_RSA_DP2_2048;
628 return PKE_RSA_DP2_3072;
630 return PKE_RSA_DP2_4096;
636 static int qat_rsa_enc(struct akcipher_request *req)
638 struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
639 struct qat_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
640 struct qat_crypto_instance *inst = ctx->inst;
641 struct device *dev = &GET_DEV(inst->accel_dev);
642 struct qat_asym_request *qat_req =
643 PTR_ALIGN(akcipher_request_ctx(req), 64);
644 struct icp_qat_fw_pke_request *msg = &qat_req->req;
647 if (unlikely(!ctx->n || !ctx->e))
650 if (req->dst_len < ctx->key_sz) {
651 req->dst_len = ctx->key_sz;
654 memset(msg, '\0', sizeof(*msg));
655 ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET(msg->pke_hdr,
656 ICP_QAT_FW_COMN_REQ_FLAG_SET);
657 msg->pke_hdr.cd_pars.func_id = qat_rsa_enc_fn_id(ctx->key_sz);
658 if (unlikely(!msg->pke_hdr.cd_pars.func_id))
661 qat_req->cb = qat_rsa_cb;
662 qat_req->ctx.rsa = ctx;
663 qat_req->areq.rsa = req;
664 msg->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_PKE;
665 msg->pke_hdr.comn_req_flags =
666 ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_PTR_TYPE_FLAT,
667 QAT_COMN_CD_FLD_TYPE_64BIT_ADR);
669 qat_req->in.rsa.enc.e = ctx->dma_e;
670 qat_req->in.rsa.enc.n = ctx->dma_n;
674 * src can be of any size in valid range, but HW expects it to be the
675 * same as modulo n so in case it is different we need to allocate a
676 * new buf and copy src data.
677 * In other case we just need to map the user provided buffer.
678 * Also need to make sure that it is in contiguous buffer.
680 if (sg_is_last(req->src) && req->src_len == ctx->key_sz) {
681 qat_req->src_align = NULL;
682 qat_req->in.rsa.enc.m = dma_map_single(dev, sg_virt(req->src),
683 req->src_len, DMA_TO_DEVICE);
684 if (unlikely(dma_mapping_error(dev, qat_req->in.rsa.enc.m)))
688 int shift = ctx->key_sz - req->src_len;
690 qat_req->src_align = dma_alloc_coherent(dev, ctx->key_sz,
691 &qat_req->in.rsa.enc.m,
693 if (unlikely(!qat_req->src_align))
696 scatterwalk_map_and_copy(qat_req->src_align + shift, req->src,
699 if (sg_is_last(req->dst) && req->dst_len == ctx->key_sz) {
700 qat_req->dst_align = NULL;
701 qat_req->out.rsa.enc.c = dma_map_single(dev, sg_virt(req->dst),
705 if (unlikely(dma_mapping_error(dev, qat_req->out.rsa.enc.c)))
709 qat_req->dst_align = dma_alloc_coherent(dev, ctx->key_sz,
710 &qat_req->out.rsa.enc.c,
712 if (unlikely(!qat_req->dst_align))
716 qat_req->in.rsa.in_tab[3] = 0;
717 qat_req->out.rsa.out_tab[1] = 0;
718 qat_req->phy_in = dma_map_single(dev, &qat_req->in.rsa.enc.m,
719 sizeof(qat_req->in.rsa.enc.m),
721 if (unlikely(dma_mapping_error(dev, qat_req->phy_in)))
724 qat_req->phy_out = dma_map_single(dev, &qat_req->out.rsa.enc.c,
725 sizeof(qat_req->out.rsa.enc.c),
727 if (unlikely(dma_mapping_error(dev, qat_req->phy_out)))
728 goto unmap_in_params;
730 msg->pke_mid.src_data_addr = qat_req->phy_in;
731 msg->pke_mid.dest_data_addr = qat_req->phy_out;
732 msg->pke_mid.opaque = (u64)(__force long)qat_req;
733 msg->input_param_count = 3;
734 msg->output_param_count = 1;
736 ret = adf_send_message(ctx->inst->pke_tx, (u32 *)msg);
737 } while (ret == -EBUSY && ctr++ < 100);
742 if (!dma_mapping_error(dev, qat_req->phy_out))
743 dma_unmap_single(dev, qat_req->phy_out,
744 sizeof(struct qat_rsa_output_params),
747 if (!dma_mapping_error(dev, qat_req->phy_in))
748 dma_unmap_single(dev, qat_req->phy_in,
749 sizeof(struct qat_rsa_input_params),
752 if (qat_req->dst_align)
753 dma_free_coherent(dev, ctx->key_sz, qat_req->dst_align,
754 qat_req->out.rsa.enc.c);
756 if (!dma_mapping_error(dev, qat_req->out.rsa.enc.c))
757 dma_unmap_single(dev, qat_req->out.rsa.enc.c,
758 ctx->key_sz, DMA_FROM_DEVICE);
760 if (qat_req->src_align)
761 dma_free_coherent(dev, ctx->key_sz, qat_req->src_align,
762 qat_req->in.rsa.enc.m);
764 if (!dma_mapping_error(dev, qat_req->in.rsa.enc.m))
765 dma_unmap_single(dev, qat_req->in.rsa.enc.m,
766 ctx->key_sz, DMA_TO_DEVICE);
770 static int qat_rsa_dec(struct akcipher_request *req)
772 struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
773 struct qat_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
774 struct qat_crypto_instance *inst = ctx->inst;
775 struct device *dev = &GET_DEV(inst->accel_dev);
776 struct qat_asym_request *qat_req =
777 PTR_ALIGN(akcipher_request_ctx(req), 64);
778 struct icp_qat_fw_pke_request *msg = &qat_req->req;
781 if (unlikely(!ctx->n || !ctx->d))
784 if (req->dst_len < ctx->key_sz) {
785 req->dst_len = ctx->key_sz;
788 memset(msg, '\0', sizeof(*msg));
789 ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET(msg->pke_hdr,
790 ICP_QAT_FW_COMN_REQ_FLAG_SET);
791 msg->pke_hdr.cd_pars.func_id = ctx->crt_mode ?
792 qat_rsa_dec_fn_id_crt(ctx->key_sz) :
793 qat_rsa_dec_fn_id(ctx->key_sz);
794 if (unlikely(!msg->pke_hdr.cd_pars.func_id))
797 qat_req->cb = qat_rsa_cb;
798 qat_req->ctx.rsa = ctx;
799 qat_req->areq.rsa = req;
800 msg->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_PKE;
801 msg->pke_hdr.comn_req_flags =
802 ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_PTR_TYPE_FLAT,
803 QAT_COMN_CD_FLD_TYPE_64BIT_ADR);
806 qat_req->in.rsa.dec_crt.p = ctx->dma_p;
807 qat_req->in.rsa.dec_crt.q = ctx->dma_q;
808 qat_req->in.rsa.dec_crt.dp = ctx->dma_dp;
809 qat_req->in.rsa.dec_crt.dq = ctx->dma_dq;
810 qat_req->in.rsa.dec_crt.qinv = ctx->dma_qinv;
812 qat_req->in.rsa.dec.d = ctx->dma_d;
813 qat_req->in.rsa.dec.n = ctx->dma_n;
818 * src can be of any size in valid range, but HW expects it to be the
819 * same as modulo n so in case it is different we need to allocate a
820 * new buf and copy src data.
821 * In other case we just need to map the user provided buffer.
822 * Also need to make sure that it is in contiguous buffer.
824 if (sg_is_last(req->src) && req->src_len == ctx->key_sz) {
825 qat_req->src_align = NULL;
826 qat_req->in.rsa.dec.c = dma_map_single(dev, sg_virt(req->src),
827 req->dst_len, DMA_TO_DEVICE);
828 if (unlikely(dma_mapping_error(dev, qat_req->in.rsa.dec.c)))
832 int shift = ctx->key_sz - req->src_len;
834 qat_req->src_align = dma_alloc_coherent(dev, ctx->key_sz,
835 &qat_req->in.rsa.dec.c,
837 if (unlikely(!qat_req->src_align))
840 scatterwalk_map_and_copy(qat_req->src_align + shift, req->src,
843 if (sg_is_last(req->dst) && req->dst_len == ctx->key_sz) {
844 qat_req->dst_align = NULL;
845 qat_req->out.rsa.dec.m = dma_map_single(dev, sg_virt(req->dst),
849 if (unlikely(dma_mapping_error(dev, qat_req->out.rsa.dec.m)))
853 qat_req->dst_align = dma_alloc_coherent(dev, ctx->key_sz,
854 &qat_req->out.rsa.dec.m,
856 if (unlikely(!qat_req->dst_align))
862 qat_req->in.rsa.in_tab[6] = 0;
864 qat_req->in.rsa.in_tab[3] = 0;
865 qat_req->out.rsa.out_tab[1] = 0;
866 qat_req->phy_in = dma_map_single(dev, &qat_req->in.rsa.dec.c,
867 sizeof(qat_req->in.rsa.dec.c),
869 if (unlikely(dma_mapping_error(dev, qat_req->phy_in)))
872 qat_req->phy_out = dma_map_single(dev, &qat_req->out.rsa.dec.m,
873 sizeof(qat_req->out.rsa.dec.m),
875 if (unlikely(dma_mapping_error(dev, qat_req->phy_out)))
876 goto unmap_in_params;
878 msg->pke_mid.src_data_addr = qat_req->phy_in;
879 msg->pke_mid.dest_data_addr = qat_req->phy_out;
880 msg->pke_mid.opaque = (u64)(__force long)qat_req;
882 msg->input_param_count = 6;
884 msg->input_param_count = 3;
886 msg->output_param_count = 1;
888 ret = adf_send_message(ctx->inst->pke_tx, (u32 *)msg);
889 } while (ret == -EBUSY && ctr++ < 100);
894 if (!dma_mapping_error(dev, qat_req->phy_out))
895 dma_unmap_single(dev, qat_req->phy_out,
896 sizeof(struct qat_rsa_output_params),
899 if (!dma_mapping_error(dev, qat_req->phy_in))
900 dma_unmap_single(dev, qat_req->phy_in,
901 sizeof(struct qat_rsa_input_params),
904 if (qat_req->dst_align)
905 dma_free_coherent(dev, ctx->key_sz, qat_req->dst_align,
906 qat_req->out.rsa.dec.m);
908 if (!dma_mapping_error(dev, qat_req->out.rsa.dec.m))
909 dma_unmap_single(dev, qat_req->out.rsa.dec.m,
910 ctx->key_sz, DMA_FROM_DEVICE);
912 if (qat_req->src_align)
913 dma_free_coherent(dev, ctx->key_sz, qat_req->src_align,
914 qat_req->in.rsa.dec.c);
916 if (!dma_mapping_error(dev, qat_req->in.rsa.dec.c))
917 dma_unmap_single(dev, qat_req->in.rsa.dec.c,
918 ctx->key_sz, DMA_TO_DEVICE);
922 static int qat_rsa_set_n(struct qat_rsa_ctx *ctx, const char *value,
925 struct qat_crypto_instance *inst = ctx->inst;
926 struct device *dev = &GET_DEV(inst->accel_dev);
927 const char *ptr = value;
930 while (!*ptr && vlen) {
937 /* invalid key size provided */
938 if (!qat_rsa_enc_fn_id(ctx->key_sz))
942 ctx->n = dma_alloc_coherent(dev, ctx->key_sz, &ctx->dma_n, GFP_KERNEL);
946 memcpy(ctx->n, ptr, ctx->key_sz);
954 static int qat_rsa_set_e(struct qat_rsa_ctx *ctx, const char *value,
957 struct qat_crypto_instance *inst = ctx->inst;
958 struct device *dev = &GET_DEV(inst->accel_dev);
959 const char *ptr = value;
961 while (!*ptr && vlen) {
966 if (!ctx->key_sz || !vlen || vlen > ctx->key_sz) {
971 ctx->e = dma_alloc_coherent(dev, ctx->key_sz, &ctx->dma_e, GFP_KERNEL);
975 memcpy(ctx->e + (ctx->key_sz - vlen), ptr, vlen);
979 static int qat_rsa_set_d(struct qat_rsa_ctx *ctx, const char *value,
982 struct qat_crypto_instance *inst = ctx->inst;
983 struct device *dev = &GET_DEV(inst->accel_dev);
984 const char *ptr = value;
987 while (!*ptr && vlen) {
993 if (!ctx->key_sz || !vlen || vlen > ctx->key_sz)
997 ctx->d = dma_alloc_coherent(dev, ctx->key_sz, &ctx->dma_d, GFP_KERNEL);
1001 memcpy(ctx->d + (ctx->key_sz - vlen), ptr, vlen);
1008 static void qat_rsa_drop_leading_zeros(const char **ptr, unsigned int *len)
1010 while (!**ptr && *len) {
1016 static void qat_rsa_setkey_crt(struct qat_rsa_ctx *ctx, struct rsa_key *rsa_key)
1018 struct qat_crypto_instance *inst = ctx->inst;
1019 struct device *dev = &GET_DEV(inst->accel_dev);
1022 unsigned int half_key_sz = ctx->key_sz / 2;
1026 len = rsa_key->p_sz;
1027 qat_rsa_drop_leading_zeros(&ptr, &len);
1030 ctx->p = dma_alloc_coherent(dev, half_key_sz, &ctx->dma_p, GFP_KERNEL);
1033 memcpy(ctx->p + (half_key_sz - len), ptr, len);
1037 len = rsa_key->q_sz;
1038 qat_rsa_drop_leading_zeros(&ptr, &len);
1041 ctx->q = dma_alloc_coherent(dev, half_key_sz, &ctx->dma_q, GFP_KERNEL);
1044 memcpy(ctx->q + (half_key_sz - len), ptr, len);
1048 len = rsa_key->dp_sz;
1049 qat_rsa_drop_leading_zeros(&ptr, &len);
1052 ctx->dp = dma_alloc_coherent(dev, half_key_sz, &ctx->dma_dp,
1056 memcpy(ctx->dp + (half_key_sz - len), ptr, len);
1060 len = rsa_key->dq_sz;
1061 qat_rsa_drop_leading_zeros(&ptr, &len);
1064 ctx->dq = dma_alloc_coherent(dev, half_key_sz, &ctx->dma_dq,
1068 memcpy(ctx->dq + (half_key_sz - len), ptr, len);
1071 ptr = rsa_key->qinv;
1072 len = rsa_key->qinv_sz;
1073 qat_rsa_drop_leading_zeros(&ptr, &len);
1076 ctx->qinv = dma_alloc_coherent(dev, half_key_sz, &ctx->dma_qinv,
1080 memcpy(ctx->qinv + (half_key_sz - len), ptr, len);
1082 ctx->crt_mode = true;
1086 memset(ctx->dq, '\0', half_key_sz);
1087 dma_free_coherent(dev, half_key_sz, ctx->dq, ctx->dma_dq);
1090 memset(ctx->dp, '\0', half_key_sz);
1091 dma_free_coherent(dev, half_key_sz, ctx->dp, ctx->dma_dp);
1094 memset(ctx->q, '\0', half_key_sz);
1095 dma_free_coherent(dev, half_key_sz, ctx->q, ctx->dma_q);
1098 memset(ctx->p, '\0', half_key_sz);
1099 dma_free_coherent(dev, half_key_sz, ctx->p, ctx->dma_p);
1102 ctx->crt_mode = false;
1105 static void qat_rsa_clear_ctx(struct device *dev, struct qat_rsa_ctx *ctx)
1107 unsigned int half_key_sz = ctx->key_sz / 2;
1109 /* Free the old key if any */
1111 dma_free_coherent(dev, ctx->key_sz, ctx->n, ctx->dma_n);
1113 dma_free_coherent(dev, ctx->key_sz, ctx->e, ctx->dma_e);
1115 memset(ctx->d, '\0', ctx->key_sz);
1116 dma_free_coherent(dev, ctx->key_sz, ctx->d, ctx->dma_d);
1119 memset(ctx->p, '\0', half_key_sz);
1120 dma_free_coherent(dev, half_key_sz, ctx->p, ctx->dma_p);
1123 memset(ctx->q, '\0', half_key_sz);
1124 dma_free_coherent(dev, half_key_sz, ctx->q, ctx->dma_q);
1127 memset(ctx->dp, '\0', half_key_sz);
1128 dma_free_coherent(dev, half_key_sz, ctx->dp, ctx->dma_dp);
1131 memset(ctx->dq, '\0', half_key_sz);
1132 dma_free_coherent(dev, half_key_sz, ctx->dq, ctx->dma_dq);
1135 memset(ctx->qinv, '\0', half_key_sz);
1136 dma_free_coherent(dev, half_key_sz, ctx->qinv, ctx->dma_qinv);
1147 ctx->crt_mode = false;
1151 static int qat_rsa_setkey(struct crypto_akcipher *tfm, const void *key,
1152 unsigned int keylen, bool private)
1154 struct qat_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
1155 struct device *dev = &GET_DEV(ctx->inst->accel_dev);
1156 struct rsa_key rsa_key;
1159 qat_rsa_clear_ctx(dev, ctx);
1162 ret = rsa_parse_priv_key(&rsa_key, key, keylen);
1164 ret = rsa_parse_pub_key(&rsa_key, key, keylen);
1168 ret = qat_rsa_set_n(ctx, rsa_key.n, rsa_key.n_sz);
1171 ret = qat_rsa_set_e(ctx, rsa_key.e, rsa_key.e_sz);
1175 ret = qat_rsa_set_d(ctx, rsa_key.d, rsa_key.d_sz);
1178 qat_rsa_setkey_crt(ctx, &rsa_key);
1181 if (!ctx->n || !ctx->e) {
1182 /* invalid key provided */
1186 if (private && !ctx->d) {
1187 /* invalid private key provided */
1194 qat_rsa_clear_ctx(dev, ctx);
1198 static int qat_rsa_setpubkey(struct crypto_akcipher *tfm, const void *key,
1199 unsigned int keylen)
1201 return qat_rsa_setkey(tfm, key, keylen, false);
1204 static int qat_rsa_setprivkey(struct crypto_akcipher *tfm, const void *key,
1205 unsigned int keylen)
1207 return qat_rsa_setkey(tfm, key, keylen, true);
1210 static unsigned int qat_rsa_max_size(struct crypto_akcipher *tfm)
1212 struct qat_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
1217 static int qat_rsa_init_tfm(struct crypto_akcipher *tfm)
1219 struct qat_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
1220 struct qat_crypto_instance *inst =
1221 qat_crypto_get_instance_node(get_current_node());
1231 static void qat_rsa_exit_tfm(struct crypto_akcipher *tfm)
1233 struct qat_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
1234 struct device *dev = &GET_DEV(ctx->inst->accel_dev);
1237 dma_free_coherent(dev, ctx->key_sz, ctx->n, ctx->dma_n);
1239 dma_free_coherent(dev, ctx->key_sz, ctx->e, ctx->dma_e);
1241 memset(ctx->d, '\0', ctx->key_sz);
1242 dma_free_coherent(dev, ctx->key_sz, ctx->d, ctx->dma_d);
1244 qat_crypto_put_instance(ctx->inst);
1250 static struct akcipher_alg rsa = {
1251 .encrypt = qat_rsa_enc,
1252 .decrypt = qat_rsa_dec,
1253 .set_pub_key = qat_rsa_setpubkey,
1254 .set_priv_key = qat_rsa_setprivkey,
1255 .max_size = qat_rsa_max_size,
1256 .init = qat_rsa_init_tfm,
1257 .exit = qat_rsa_exit_tfm,
1258 .reqsize = sizeof(struct qat_asym_request) + 64,
1261 .cra_driver_name = "qat-rsa",
1262 .cra_priority = 1000,
1263 .cra_module = THIS_MODULE,
1264 .cra_ctxsize = sizeof(struct qat_rsa_ctx),
1268 static struct kpp_alg dh = {
1269 .set_secret = qat_dh_set_secret,
1270 .generate_public_key = qat_dh_compute_value,
1271 .compute_shared_secret = qat_dh_compute_value,
1272 .max_size = qat_dh_max_size,
1273 .init = qat_dh_init_tfm,
1274 .exit = qat_dh_exit_tfm,
1275 .reqsize = sizeof(struct qat_asym_request) + 64,
1278 .cra_driver_name = "qat-dh",
1279 .cra_priority = 1000,
1280 .cra_module = THIS_MODULE,
1281 .cra_ctxsize = sizeof(struct qat_dh_ctx),
1285 int qat_asym_algs_register(void)
1289 mutex_lock(&algs_lock);
1290 if (++active_devs == 1) {
1291 rsa.base.cra_flags = 0;
1292 ret = crypto_register_akcipher(&rsa);
1295 ret = crypto_register_kpp(&dh);
1298 mutex_unlock(&algs_lock);
1302 void qat_asym_algs_unregister(void)
1304 mutex_lock(&algs_lock);
1305 if (--active_devs == 0) {
1306 crypto_unregister_akcipher(&rsa);
1307 crypto_unregister_kpp(&dh);
1309 mutex_unlock(&algs_lock);