1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (C) 2018 Integrated Device Technology, Inc
6 #define pr_fmt(fmt) "IDT_82p33xxx: " fmt
8 #include <linux/firmware.h>
10 #include <linux/module.h>
11 #include <linux/ptp_clock_kernel.h>
12 #include <linux/delay.h>
13 #include <linux/kernel.h>
14 #include <linux/timekeeping.h>
15 #include <linux/bitops.h>
17 #include "ptp_private.h"
18 #include "ptp_idt82p33.h"
20 MODULE_DESCRIPTION("Driver for IDT 82p33xxx clock devices");
21 MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
22 MODULE_VERSION("1.0");
23 MODULE_LICENSE("GPL");
25 /* Module Parameters */
26 static u32 sync_tod_timeout = SYNC_TOD_TIMEOUT_SEC;
27 module_param(sync_tod_timeout, uint, 0);
28 MODULE_PARM_DESC(sync_tod_timeout,
29 "duration in second to keep SYNC_TOD on (set to 0 to keep it always on)");
31 static u32 phase_snap_threshold = SNAP_THRESHOLD_NS;
32 module_param(phase_snap_threshold, uint, 0);
33 MODULE_PARM_DESC(phase_snap_threshold,
34 "threshold (150000ns by default) below which adjtime would ignore");
36 static void idt82p33_byte_array_to_timespec(struct timespec64 *ts,
37 u8 buf[TOD_BYTE_COUNT])
44 for (i = 0; i < 3; i++) {
50 for (i = 0; i < 5; i++) {
59 static void idt82p33_timespec_to_byte_array(struct timespec64 const *ts,
60 u8 buf[TOD_BYTE_COUNT])
69 for (i = 0; i < 4; i++) {
74 for (i = 4; i < TOD_BYTE_COUNT; i++) {
80 static int idt82p33_xfer(struct idt82p33 *idt82p33,
81 unsigned char regaddr,
86 struct i2c_client *client = idt82p33->client;
87 struct i2c_msg msg[2];
90 msg[0].addr = client->addr;
93 msg[0].buf = ®addr;
95 msg[1].addr = client->addr;
96 msg[1].flags = write ? 0 : I2C_M_RD;
100 cnt = i2c_transfer(client->adapter, msg, 2);
102 dev_err(&client->dev, "i2c_transfer returned %d\n", cnt);
104 } else if (cnt != 2) {
105 dev_err(&client->dev,
106 "i2c_transfer sent only %d of %d messages\n", cnt, 2);
112 static int idt82p33_page_offset(struct idt82p33 *idt82p33, unsigned char val)
116 if (idt82p33->page_offset == val)
119 err = idt82p33_xfer(idt82p33, PAGE_ADDR, &val, sizeof(val), 1);
121 dev_err(&idt82p33->client->dev,
122 "failed to set page offset %d\n", val);
124 idt82p33->page_offset = val;
129 static int idt82p33_rdwr(struct idt82p33 *idt82p33, unsigned int regaddr,
130 unsigned char *buf, unsigned int count, bool write)
135 page = _PAGE(regaddr);
136 offset = _OFFSET(regaddr);
138 err = idt82p33_page_offset(idt82p33, page);
142 err = idt82p33_xfer(idt82p33, offset, buf, count, write);
147 static int idt82p33_read(struct idt82p33 *idt82p33, unsigned int regaddr,
148 unsigned char *buf, unsigned int count)
150 return idt82p33_rdwr(idt82p33, regaddr, buf, count, false);
153 static int idt82p33_write(struct idt82p33 *idt82p33, unsigned int regaddr,
154 unsigned char *buf, unsigned int count)
156 return idt82p33_rdwr(idt82p33, regaddr, buf, count, true);
159 static int idt82p33_dpll_set_mode(struct idt82p33_channel *channel,
162 struct idt82p33 *idt82p33 = channel->idt82p33;
166 if (channel->pll_mode == mode)
169 err = idt82p33_read(idt82p33, channel->dpll_mode_cnfg,
170 &dpll_mode, sizeof(dpll_mode));
174 dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
176 dpll_mode |= (mode << PLL_MODE_SHIFT);
178 err = idt82p33_write(idt82p33, channel->dpll_mode_cnfg,
179 &dpll_mode, sizeof(dpll_mode));
183 channel->pll_mode = dpll_mode;
188 static int _idt82p33_gettime(struct idt82p33_channel *channel,
189 struct timespec64 *ts)
191 struct idt82p33 *idt82p33 = channel->idt82p33;
192 u8 buf[TOD_BYTE_COUNT];
196 trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
197 HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
200 err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
201 &trigger, sizeof(trigger));
206 if (idt82p33->calculate_overhead_flag)
207 idt82p33->start_time = ktime_get_raw();
209 err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf));
214 idt82p33_byte_array_to_timespec(ts, buf);
221 * Bits[7:4] Write 0x9, MSB write
222 * Bits[3:0] Read 0x9, LSB read
225 static int _idt82p33_settime(struct idt82p33_channel *channel,
226 struct timespec64 const *ts)
228 struct idt82p33 *idt82p33 = channel->idt82p33;
229 struct timespec64 local_ts = *ts;
230 char buf[TOD_BYTE_COUNT];
231 s64 dynamic_overhead_ns;
232 unsigned char trigger;
236 trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
237 HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
239 err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
240 &trigger, sizeof(trigger));
245 if (idt82p33->calculate_overhead_flag) {
246 dynamic_overhead_ns = ktime_to_ns(ktime_get_raw())
247 - ktime_to_ns(idt82p33->start_time);
249 timespec64_add_ns(&local_ts, dynamic_overhead_ns);
251 idt82p33->calculate_overhead_flag = 0;
254 idt82p33_timespec_to_byte_array(&local_ts, buf);
257 * Store the new time value.
259 for (i = 0; i < TOD_BYTE_COUNT; i++) {
260 err = idt82p33_write(idt82p33, channel->dpll_tod_cnfg + i,
261 &buf[i], sizeof(buf[i]));
269 static int _idt82p33_adjtime(struct idt82p33_channel *channel, s64 delta_ns)
271 struct idt82p33 *idt82p33 = channel->idt82p33;
272 struct timespec64 ts;
276 idt82p33->calculate_overhead_flag = 1;
278 err = _idt82p33_gettime(channel, &ts);
283 now_ns = timespec64_to_ns(&ts);
284 now_ns += delta_ns + idt82p33->tod_write_overhead_ns;
286 ts = ns_to_timespec64(now_ns);
288 err = _idt82p33_settime(channel, &ts);
293 static int _idt82p33_adjfine(struct idt82p33_channel *channel, long scaled_ppm)
295 struct idt82p33 *idt82p33 = channel->idt82p33;
296 unsigned char buf[5] = {0};
301 if (scaled_ppm == channel->current_freq_ppb)
305 * Frequency Control Word unit is: 1.68 * 10^-10 ppm
314 * FCW = -------------
317 if (scaled_ppm < 0) {
319 scaled_ppm = -scaled_ppm;
322 fcw = scaled_ppm * 244140625ULL;
323 fcw = div_u64(fcw, 2688);
328 for (i = 0; i < 5; i++) {
333 err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);
338 err = idt82p33_write(idt82p33, channel->dpll_freq_cnfg,
342 channel->current_freq_ppb = scaled_ppm;
347 static int idt82p33_measure_one_byte_write_overhead(
348 struct idt82p33_channel *channel, s64 *overhead_ns)
350 struct idt82p33 *idt82p33 = channel->idt82p33;
359 trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
360 HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
362 for (i = 0; i < MAX_MEASURMENT_COUNT; i++) {
364 start = ktime_get_raw();
366 err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
367 &trigger, sizeof(trigger));
369 stop = ktime_get_raw();
374 total_ns += ktime_to_ns(stop) - ktime_to_ns(start);
377 *overhead_ns = div_s64(total_ns, MAX_MEASURMENT_COUNT);
382 static int idt82p33_measure_tod_write_9_byte_overhead(
383 struct idt82p33_channel *channel)
385 struct idt82p33 *idt82p33 = channel->idt82p33;
386 u8 buf[TOD_BYTE_COUNT];
393 idt82p33->tod_write_overhead_ns = 0;
395 for (i = 0; i < MAX_MEASURMENT_COUNT; i++) {
397 start = ktime_get_raw();
399 /* Need one less byte for applicable overhead */
400 for (j = 0; j < (TOD_BYTE_COUNT - 1); j++) {
401 err = idt82p33_write(idt82p33,
402 channel->dpll_tod_cnfg + i,
403 &buf[i], sizeof(buf[i]));
408 stop = ktime_get_raw();
410 total_ns += ktime_to_ns(stop) - ktime_to_ns(start);
413 idt82p33->tod_write_overhead_ns = div_s64(total_ns,
414 MAX_MEASURMENT_COUNT);
419 static int idt82p33_measure_settime_gettime_gap_overhead(
420 struct idt82p33_channel *channel, s64 *overhead_ns)
422 struct timespec64 ts1 = {0, 0};
423 struct timespec64 ts2;
428 err = _idt82p33_settime(channel, &ts1);
433 err = _idt82p33_gettime(channel, &ts2);
436 *overhead_ns = timespec64_to_ns(&ts2) - timespec64_to_ns(&ts1);
441 static int idt82p33_measure_tod_write_overhead(struct idt82p33_channel *channel)
443 s64 trailing_overhead_ns, one_byte_write_ns, gap_ns;
444 struct idt82p33 *idt82p33 = channel->idt82p33;
447 idt82p33->tod_write_overhead_ns = 0;
449 err = idt82p33_measure_settime_gettime_gap_overhead(channel, &gap_ns);
454 err = idt82p33_measure_one_byte_write_overhead(channel,
460 err = idt82p33_measure_tod_write_9_byte_overhead(channel);
465 trailing_overhead_ns = gap_ns - (2 * one_byte_write_ns);
467 idt82p33->tod_write_overhead_ns -= trailing_overhead_ns;
472 static int idt82p33_check_and_set_masks(struct idt82p33 *idt82p33,
479 if (page == PLLMASK_ADDR_HI && offset == PLLMASK_ADDR_LO) {
480 if ((val & 0xfc) || !(val & 0x3)) {
481 dev_err(&idt82p33->client->dev,
482 "Invalid PLL mask 0x%hhx\n", val);
485 idt82p33->pll_mask = val;
487 } else if (page == PLL0_OUTMASK_ADDR_HI &&
488 offset == PLL0_OUTMASK_ADDR_LO) {
489 idt82p33->channel[0].output_mask = val;
490 } else if (page == PLL1_OUTMASK_ADDR_HI &&
491 offset == PLL1_OUTMASK_ADDR_LO) {
492 idt82p33->channel[1].output_mask = val;
498 static void idt82p33_display_masks(struct idt82p33 *idt82p33)
502 dev_info(&idt82p33->client->dev,
503 "pllmask = 0x%02x\n", idt82p33->pll_mask);
505 for (i = 0; i < MAX_PHC_PLL; i++) {
508 if (mask & idt82p33->pll_mask)
509 dev_info(&idt82p33->client->dev,
510 "PLL%d output_mask = 0x%04x\n",
511 i, idt82p33->channel[i].output_mask);
515 static int idt82p33_sync_tod(struct idt82p33_channel *channel, bool enable)
517 struct idt82p33 *idt82p33 = channel->idt82p33;
521 if (enable == channel->sync_tod_on) {
522 if (enable && sync_tod_timeout) {
523 mod_delayed_work(system_wq, &channel->sync_tod_work,
524 sync_tod_timeout * HZ);
529 err = idt82p33_read(idt82p33, channel->dpll_sync_cnfg,
530 &sync_cnfg, sizeof(sync_cnfg));
534 sync_cnfg &= ~SYNC_TOD;
537 sync_cnfg |= SYNC_TOD;
539 err = idt82p33_write(idt82p33, channel->dpll_sync_cnfg,
540 &sync_cnfg, sizeof(sync_cnfg));
544 channel->sync_tod_on = enable;
546 if (enable && sync_tod_timeout) {
547 mod_delayed_work(system_wq, &channel->sync_tod_work,
548 sync_tod_timeout * HZ);
554 static void idt82p33_sync_tod_work_handler(struct work_struct *work)
556 struct idt82p33_channel *channel =
557 container_of(work, struct idt82p33_channel, sync_tod_work.work);
558 struct idt82p33 *idt82p33 = channel->idt82p33;
560 mutex_lock(&idt82p33->reg_lock);
562 (void)idt82p33_sync_tod(channel, false);
564 mutex_unlock(&idt82p33->reg_lock);
567 static int idt82p33_pps_enable(struct idt82p33_channel *channel, bool enable)
569 struct idt82p33 *idt82p33 = channel->idt82p33;
573 mask = channel->output_mask;
578 err = idt82p33_read(idt82p33, OUT_MUX_CNFG(outn),
584 val &= ~SQUELCH_ENABLE;
586 val |= SQUELCH_ENABLE;
588 err = idt82p33_write(idt82p33, OUT_MUX_CNFG(outn),
601 static int idt82p33_enable_tod(struct idt82p33_channel *channel)
603 struct idt82p33 *idt82p33 = channel->idt82p33;
604 struct timespec64 ts = {0, 0};
609 err = idt82p33_write(idt82p33, channel->dpll_input_mode_cnfg,
614 err = idt82p33_pps_enable(channel, false);
619 err = idt82p33_measure_tod_write_overhead(channel);
624 err = _idt82p33_settime(channel, &ts);
629 return idt82p33_sync_tod(channel, true);
632 static void idt82p33_ptp_clock_unregister_all(struct idt82p33 *idt82p33)
634 struct idt82p33_channel *channel;
637 for (i = 0; i < MAX_PHC_PLL; i++) {
639 channel = &idt82p33->channel[i];
641 if (channel->ptp_clock) {
642 ptp_clock_unregister(channel->ptp_clock);
643 cancel_delayed_work_sync(&channel->sync_tod_work);
648 static int idt82p33_enable(struct ptp_clock_info *ptp,
649 struct ptp_clock_request *rq, int on)
651 struct idt82p33_channel *channel =
652 container_of(ptp, struct idt82p33_channel, caps);
653 struct idt82p33 *idt82p33 = channel->idt82p33;
658 mutex_lock(&idt82p33->reg_lock);
660 if (rq->type == PTP_CLK_REQ_PEROUT) {
662 err = idt82p33_pps_enable(channel, false);
664 /* Only accept a 1-PPS aligned to the second. */
665 else if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
666 rq->perout.period.nsec) {
669 err = idt82p33_pps_enable(channel, true);
672 mutex_unlock(&idt82p33->reg_lock);
677 static int idt82p33_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
679 struct idt82p33_channel *channel =
680 container_of(ptp, struct idt82p33_channel, caps);
681 struct idt82p33 *idt82p33 = channel->idt82p33;
684 mutex_lock(&idt82p33->reg_lock);
685 err = _idt82p33_adjfine(channel, scaled_ppm);
686 mutex_unlock(&idt82p33->reg_lock);
691 static int idt82p33_adjtime(struct ptp_clock_info *ptp, s64 delta_ns)
693 struct idt82p33_channel *channel =
694 container_of(ptp, struct idt82p33_channel, caps);
695 struct idt82p33 *idt82p33 = channel->idt82p33;
698 mutex_lock(&idt82p33->reg_lock);
700 if (abs(delta_ns) < phase_snap_threshold) {
701 mutex_unlock(&idt82p33->reg_lock);
705 err = _idt82p33_adjtime(channel, delta_ns);
708 mutex_unlock(&idt82p33->reg_lock);
712 err = idt82p33_sync_tod(channel, true);
714 mutex_unlock(&idt82p33->reg_lock);
719 static int idt82p33_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
721 struct idt82p33_channel *channel =
722 container_of(ptp, struct idt82p33_channel, caps);
723 struct idt82p33 *idt82p33 = channel->idt82p33;
726 mutex_lock(&idt82p33->reg_lock);
727 err = _idt82p33_gettime(channel, ts);
728 mutex_unlock(&idt82p33->reg_lock);
733 static int idt82p33_settime(struct ptp_clock_info *ptp,
734 const struct timespec64 *ts)
736 struct idt82p33_channel *channel =
737 container_of(ptp, struct idt82p33_channel, caps);
738 struct idt82p33 *idt82p33 = channel->idt82p33;
741 mutex_lock(&idt82p33->reg_lock);
742 err = _idt82p33_settime(channel, ts);
743 mutex_unlock(&idt82p33->reg_lock);
748 static int idt82p33_channel_init(struct idt82p33_channel *channel, int index)
752 channel->dpll_tod_cnfg = DPLL1_TOD_CNFG;
753 channel->dpll_tod_trigger = DPLL1_TOD_TRIGGER;
754 channel->dpll_tod_sts = DPLL1_TOD_STS;
755 channel->dpll_mode_cnfg = DPLL1_OPERATING_MODE_CNFG;
756 channel->dpll_freq_cnfg = DPLL1_HOLDOVER_FREQ_CNFG;
757 channel->dpll_phase_cnfg = DPLL1_PHASE_OFFSET_CNFG;
758 channel->dpll_sync_cnfg = DPLL1_SYNC_EDGE_CNFG;
759 channel->dpll_input_mode_cnfg = DPLL1_INPUT_MODE_CNFG;
762 channel->dpll_tod_cnfg = DPLL2_TOD_CNFG;
763 channel->dpll_tod_trigger = DPLL2_TOD_TRIGGER;
764 channel->dpll_tod_sts = DPLL2_TOD_STS;
765 channel->dpll_mode_cnfg = DPLL2_OPERATING_MODE_CNFG;
766 channel->dpll_freq_cnfg = DPLL2_HOLDOVER_FREQ_CNFG;
767 channel->dpll_phase_cnfg = DPLL2_PHASE_OFFSET_CNFG;
768 channel->dpll_sync_cnfg = DPLL2_SYNC_EDGE_CNFG;
769 channel->dpll_input_mode_cnfg = DPLL2_INPUT_MODE_CNFG;
775 INIT_DELAYED_WORK(&channel->sync_tod_work,
776 idt82p33_sync_tod_work_handler);
777 channel->sync_tod_on = false;
778 channel->current_freq_ppb = 0;
783 static void idt82p33_caps_init(struct ptp_clock_info *caps)
785 caps->owner = THIS_MODULE;
786 caps->max_adj = 92000;
787 caps->adjfine = idt82p33_adjfine;
788 caps->adjtime = idt82p33_adjtime;
789 caps->gettime64 = idt82p33_gettime;
790 caps->settime64 = idt82p33_settime;
791 caps->enable = idt82p33_enable;
794 static int idt82p33_enable_channel(struct idt82p33 *idt82p33, u32 index)
796 struct idt82p33_channel *channel;
799 if (!(index < MAX_PHC_PLL))
802 channel = &idt82p33->channel[index];
804 err = idt82p33_channel_init(channel, index);
808 channel->idt82p33 = idt82p33;
810 idt82p33_caps_init(&channel->caps);
811 snprintf(channel->caps.name, sizeof(channel->caps.name),
812 "IDT 82P33 PLL%u", index);
813 channel->caps.n_per_out = hweight8(channel->output_mask);
815 err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);
819 err = idt82p33_enable_tod(channel);
823 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
825 if (IS_ERR(channel->ptp_clock)) {
826 err = PTR_ERR(channel->ptp_clock);
827 channel->ptp_clock = NULL;
831 if (!channel->ptp_clock)
834 dev_info(&idt82p33->client->dev, "PLL%d registered as ptp%d\n",
835 index, channel->ptp_clock->index);
840 static int idt82p33_load_firmware(struct idt82p33 *idt82p33)
842 const struct firmware *fw;
843 struct idt82p33_fwrc *rec;
844 u8 loaddr, page, val;
848 dev_dbg(&idt82p33->client->dev,
849 "requesting firmware '%s'\n", FW_FILENAME);
851 err = reject_firmware(&fw, FW_FILENAME, &idt82p33->client->dev);
856 dev_dbg(&idt82p33->client->dev, "firmware size %zu bytes\n", fw->size);
858 rec = (struct idt82p33_fwrc *) fw->data;
860 for (len = fw->size; len > 0; len -= sizeof(*rec)) {
863 dev_err(&idt82p33->client->dev,
864 "bad firmware, reserved field non-zero\n");
868 loaddr = rec->loaddr;
873 err = idt82p33_check_and_set_masks(idt82p33, page,
878 /* maximum 8 pages */
879 if (page >= PAGE_NUM)
882 /* Page size 128, last 4 bytes of page skipped */
883 if (((loaddr > 0x7b) && (loaddr <= 0x7f))
887 err = idt82p33_write(idt82p33, _ADDR(page, loaddr),
895 idt82p33_display_masks(idt82p33);
897 release_firmware(fw);
902 static int idt82p33_probe(struct i2c_client *client,
903 const struct i2c_device_id *id)
905 struct idt82p33 *idt82p33;
911 idt82p33 = devm_kzalloc(&client->dev,
912 sizeof(struct idt82p33), GFP_KERNEL);
916 mutex_init(&idt82p33->reg_lock);
918 idt82p33->client = client;
919 idt82p33->page_offset = 0xff;
920 idt82p33->tod_write_overhead_ns = 0;
921 idt82p33->calculate_overhead_flag = 0;
922 idt82p33->pll_mask = DEFAULT_PLL_MASK;
923 idt82p33->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
924 idt82p33->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
926 mutex_lock(&idt82p33->reg_lock);
928 err = idt82p33_load_firmware(idt82p33);
931 dev_warn(&idt82p33->client->dev,
932 "loading firmware failed with %d\n", err);
934 if (idt82p33->pll_mask) {
935 for (i = 0; i < MAX_PHC_PLL; i++) {
936 if (idt82p33->pll_mask & (1 << i)) {
937 err = idt82p33_enable_channel(idt82p33, i);
943 dev_err(&idt82p33->client->dev,
944 "no PLLs flagged as PHCs, nothing to do\n");
948 mutex_unlock(&idt82p33->reg_lock);
951 idt82p33_ptp_clock_unregister_all(idt82p33);
955 i2c_set_clientdata(client, idt82p33);
960 static int idt82p33_remove(struct i2c_client *client)
962 struct idt82p33 *idt82p33 = i2c_get_clientdata(client);
964 idt82p33_ptp_clock_unregister_all(idt82p33);
965 mutex_destroy(&idt82p33->reg_lock);
971 static const struct of_device_id idt82p33_dt_id[] = {
972 { .compatible = "idt,82p33810" },
973 { .compatible = "idt,82p33813" },
974 { .compatible = "idt,82p33814" },
975 { .compatible = "idt,82p33831" },
976 { .compatible = "idt,82p33910" },
977 { .compatible = "idt,82p33913" },
978 { .compatible = "idt,82p33914" },
979 { .compatible = "idt,82p33931" },
982 MODULE_DEVICE_TABLE(of, idt82p33_dt_id);
985 static const struct i2c_device_id idt82p33_i2c_id[] = {
996 MODULE_DEVICE_TABLE(i2c, idt82p33_i2c_id);
998 static struct i2c_driver idt82p33_driver = {
1000 .of_match_table = of_match_ptr(idt82p33_dt_id),
1003 .probe = idt82p33_probe,
1004 .remove = idt82p33_remove,
1005 .id_table = idt82p33_i2c_id,
1008 module_i2c_driver(idt82p33_driver);