1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
4 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * pSeries specific routines for PCI.
9 #include <linux/init.h>
10 #include <linux/ioport.h>
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/string.h>
16 #include <asm/pci-bridge.h>
18 #include <asm/ppc-pci.h>
23 void pcibios_name_device(struct pci_dev *dev)
25 struct device_node *dn;
28 * Add IBM loc code (slot) as a prefix to the device names for service
30 dn = pci_device_to_OF_node(dev);
32 const char *loc_code = of_get_property(dn, "ibm,loc-code",
35 int loc_len = strlen(loc_code);
36 if (loc_len < sizeof(dev->dev.name)) {
37 memmove(dev->dev.name+loc_len+1, dev->dev.name,
38 sizeof(dev->dev.name)-loc_len-1);
39 memcpy(dev->dev.name, loc_code, loc_len);
40 dev->dev.name[loc_len] = ' ';
41 dev->dev.name[sizeof(dev->dev.name)-1] = '\0';
46 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_name_device);
50 #define MAX_VFS_FOR_MAP_PE 256
51 struct pe_map_bar_entry {
52 __be64 bar; /* Input: Virtual Function BAR */
53 __be16 rid; /* Input: Virtual Function Router ID */
54 __be16 pe_num; /* Output: Virtual Function PE Number */
55 __be32 reserved; /* Reserved Space */
58 int pseries_send_map_pe(struct pci_dev *pdev,
60 struct pe_map_bar_entry *vf_pe_array)
64 unsigned long buid, addr;
65 int ibm_map_pes = rtas_token("ibm,open-sriov-map-pe-number");
67 if (ibm_map_pes == RTAS_UNKNOWN_SERVICE)
70 pdn = pci_get_pdn(pdev);
71 addr = rtas_config_addr(pdn->busno, pdn->devfn, 0);
72 buid = pdn->phb->buid;
73 spin_lock(&rtas_data_buf_lock);
74 memcpy(rtas_data_buf, vf_pe_array,
76 rc = rtas_call(ibm_map_pes, 5, 1, NULL, addr,
77 BUID_HI(buid), BUID_LO(buid),
79 num_vfs * sizeof(struct pe_map_bar_entry));
80 memcpy(vf_pe_array, rtas_data_buf, RTAS_DATA_BUF_SIZE);
81 spin_unlock(&rtas_data_buf_lock);
85 "%s: Failed to associate pes PE#%lx, rc=%x\n",
91 void pseries_set_pe_num(struct pci_dev *pdev, u16 vf_index, __be16 pe_num)
95 pdn = pci_get_pdn(pdev);
96 pdn->pe_num_map[vf_index] = be16_to_cpu(pe_num);
97 dev_dbg(&pdev->dev, "VF %04x:%02x:%02x.%x associated with PE#%x\n",
98 pci_domain_nr(pdev->bus),
100 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
101 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)),
102 pdn->pe_num_map[vf_index]);
105 int pseries_associate_pes(struct pci_dev *pdev, u16 num_vfs)
109 struct pe_map_bar_entry *vf_pe_array;
110 struct resource *res;
113 vf_pe_array = kzalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL);
117 pdn = pci_get_pdn(pdev);
118 /* create firmware structure to associate pes */
119 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
120 pdn->pe_num_map[vf_index] = IODA_INVALID_PE;
121 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
122 res = &pdev->resource[i + PCI_IOV_RESOURCES];
125 size = pcibios_iov_resource_alignment(pdev, i +
127 vf_pe_array[vf_index].bar =
128 cpu_to_be64(res->start + size * vf_index);
129 vf_pe_array[vf_index].rid =
130 cpu_to_be16((pci_iov_virtfn_bus(pdev, vf_index)
131 << 8) | pci_iov_virtfn_devfn(pdev,
133 vf_pe_array[vf_index].pe_num =
134 cpu_to_be16(IODA_INVALID_PE);
138 rc = pseries_send_map_pe(pdev, num_vfs, vf_pe_array);
139 /* Only zero is success */
141 for (vf_index = 0; vf_index < num_vfs; vf_index++)
142 pseries_set_pe_num(pdev, vf_index,
143 vf_pe_array[vf_index].pe_num);
149 int pseries_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
155 struct device_node *dn = pci_device_to_OF_node(pdev);
157 max_vfs = of_get_property(dn, "ibm,number-of-configurable-vfs", NULL);
162 /* First integer stores max config */
163 max_config_vfs = of_read_number(&max_vfs[0], 1);
164 if (max_config_vfs < num_vfs && num_vfs > MAX_VFS_FOR_MAP_PE) {
166 "Num VFs %x > %x Configurable VFs\n",
167 num_vfs, (num_vfs > MAX_VFS_FOR_MAP_PE) ?
168 MAX_VFS_FOR_MAP_PE : max_config_vfs);
172 pdn = pci_get_pdn(pdev);
173 pdn->pe_num_map = kmalloc_array(num_vfs,
174 sizeof(*pdn->pe_num_map),
176 if (!pdn->pe_num_map)
179 rc = pseries_associate_pes(pdev, num_vfs);
181 /* Anything other than zero is failure */
183 dev_err(&pdev->dev, "Failure to enable sriov: %x\n", rc);
184 kfree(pdn->pe_num_map);
186 pci_vf_drivers_autoprobe(pdev, false);
192 int pseries_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
194 /* Allocate PCI data */
195 add_dev_pci_data(pdev);
196 return pseries_pci_sriov_enable(pdev, num_vfs);
199 int pseries_pcibios_sriov_disable(struct pci_dev *pdev)
203 pdn = pci_get_pdn(pdev);
204 /* Releasing pe_num_map */
205 kfree(pdn->pe_num_map);
206 /* Release PCI data */
207 remove_dev_pci_data(pdev);
208 pci_vf_drivers_autoprobe(pdev, true);
213 static void __init pSeries_request_regions(void)
218 request_region(0x20,0x20,"pic1");
219 request_region(0xa0,0x20,"pic2");
220 request_region(0x00,0x20,"dma1");
221 request_region(0x40,0x20,"timer");
222 request_region(0x80,0x10,"dma page reg");
223 request_region(0xc0,0x20,"dma2");
226 void __init pSeries_final_fixup(void)
228 struct pci_controller *hose;
230 pSeries_request_regions();
234 #ifdef CONFIG_PCI_IOV
235 ppc_md.pcibios_sriov_enable = pseries_pcibios_sriov_enable;
236 ppc_md.pcibios_sriov_disable = pseries_pcibios_sriov_disable;
238 list_for_each_entry(hose, &hose_list, list_node) {
239 struct device_node *dn = hose->dn, *nvdn;
242 dn = of_find_all_nodes(dn);
245 nvdn = of_parse_phandle(dn, "ibm,nvlink", 0);
248 if (!of_device_is_compatible(nvdn, "ibm,npu-link"))
250 if (!of_device_is_compatible(nvdn->parent,
253 #ifdef CONFIG_PPC_POWERNV
254 WARN_ON_ONCE(pnv_npu2_init(hose));
262 * Assume the winbond 82c105 is the IDE controller on a
263 * p610/p615/p630. We should probably be more careful in case
264 * someone tries to plug in a similar adapter.
266 static void fixup_winbond_82c105(struct pci_dev* dev)
271 if (!machine_is(pseries))
274 printk("Using INTC for W82c105 IDE controller.\n");
275 pci_read_config_dword(dev, 0x40, ®);
276 /* Enable LEGIRQ to use INTC instead of ISA interrupts */
277 pci_write_config_dword(dev, 0x40, reg | (1<<11));
279 for (i = 0; i < DEVICE_COUNT_RESOURCE; ++i) {
280 /* zap the 2nd function of the winbond chip */
281 if (dev->resource[i].flags & IORESOURCE_IO
282 && dev->bus->number == 0 && dev->devfn == 0x81)
283 dev->resource[i].flags &= ~IORESOURCE_IO;
284 if (dev->resource[i].start == 0 && dev->resource[i].end) {
285 dev->resource[i].flags = 0;
286 dev->resource[i].end = 0;
290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
291 fixup_winbond_82c105);
293 int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
295 struct device_node *dn, *pdn;
297 u32 pcie_link_speed_stats[2];
302 /* Rely on the pcibios_free_controller_deferred() callback. */
303 pci_set_host_bridge_release(bridge, pcibios_free_controller_deferred,
304 (void *) pci_bus_to_host(bus));
306 dn = pcibios_get_phb_of_node(bus);
310 for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) {
311 rc = of_property_read_u32_array(pdn,
312 "ibm,pcie-link-speed-stats",
313 &pcie_link_speed_stats[0], 2);
321 pr_debug("no ibm,pcie-link-speed-stats property\n");
325 switch (pcie_link_speed_stats[0]) {
327 bus->max_bus_speed = PCIE_SPEED_2_5GT;
330 bus->max_bus_speed = PCIE_SPEED_5_0GT;
333 bus->max_bus_speed = PCIE_SPEED_8_0GT;
336 bus->max_bus_speed = PCI_SPEED_UNKNOWN;
340 switch (pcie_link_speed_stats[1]) {
342 bus->cur_bus_speed = PCIE_SPEED_2_5GT;
345 bus->cur_bus_speed = PCIE_SPEED_5_0GT;
348 bus->cur_bus_speed = PCIE_SPEED_8_0GT;
351 bus->cur_bus_speed = PCI_SPEED_UNKNOWN;