2 * Based on arch/arm/mm/proc.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/init.h>
22 #include <linux/linkage.h>
23 #include <asm/assembler.h>
24 #include <asm/asm-offsets.h>
25 #include <asm/hwcap.h>
26 #include <asm/pgtable.h>
27 #include <asm/pgtable-hwdef.h>
28 #include <asm/cpufeature.h>
29 #include <asm/alternative.h>
31 #ifdef CONFIG_ARM64_64K_PAGES
32 #define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K
33 #elif defined(CONFIG_ARM64_16K_PAGES)
34 #define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K
35 #else /* CONFIG_ARM64_4K_PAGES */
36 #define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K
39 #define TCR_SMP_FLAGS TCR_SHARED
41 /* PTWs cacheable, inner/outer WBWA */
42 #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
44 #define MAIR(attr, mt) ((attr) << ((mt) * 8))
49 * Idle the processor (wait for interrupt).
52 dsb sy // WFI may enter a low-power mode
59 * cpu_do_suspend - save CPU registers context
61 * x0: virtual address of context pointer
66 mrs x4, contextidr_el1
74 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
84 stp x10, x11, [x0, #64]
85 stp x12, x13, [x0, #80]
87 ENDPROC(cpu_do_suspend)
90 * cpu_do_resume - restore CPU register context
92 * x0: Address of context pointer
94 .pushsection ".idmap.text", "awx"
99 ldp x9, x10, [x0, #48]
100 ldp x11, x12, [x0, #64]
101 ldp x13, x14, [x0, #80]
104 msr contextidr_el1, x4
107 /* Don't change t0sz here, mask those bits when restoring */
109 bfi x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
115 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
116 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
117 * exception. Mask them until local_dbg_restore() in cpu_suspend()
124 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
131 * Restore oslsr_el1 by writing oslar_el1
134 ubfx x11, x11, #1, #1
136 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
139 ENDPROC(cpu_do_resume)
144 * cpu_do_switch_mm(pgd_phys, tsk)
146 * Set the translation table base pointer to be pgd_phys.
148 * - pgd_phys - physical address of new TTB
150 ENTRY(cpu_do_switch_mm)
152 mmid x1, x1 // get mm->context.id
153 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
154 bfi x0, x1, #48, #16 // set the ASID field in TTBR0
156 bfi x2, x1, #48, #16 // set the ASID
157 msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set)
159 msr ttbr0_el1, x0 // now update TTBR0
161 b post_ttbr_update_workaround // Back to C code...
162 ENDPROC(cpu_do_switch_mm)
164 .pushsection ".idmap.text", "awx"
166 .macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
167 adrp \tmp1, empty_zero_page
176 * void idmap_cpu_replace_ttbr1(phys_addr_t new_pgd)
178 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
179 * called by anything else. It can only be executed from a TTBR0 mapping.
181 ENTRY(idmap_cpu_replace_ttbr1)
185 __idmap_cpu_set_reserved_ttbr1 x1, x3
193 ENDPROC(idmap_cpu_replace_ttbr1)
196 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
197 .pushsection ".idmap.text", "awx"
199 .macro __idmap_kpti_get_pgtable_ent, type
200 dc cvac, cur_\()\type\()p // Ensure any existing dirty
201 dmb sy // lines are written back before
202 ldr \type, [cur_\()\type\()p] // loading the entry
203 tbz \type, #0, skip_\()\type // Skip invalid and
204 tbnz \type, #11, skip_\()\type // non-global entries
207 .macro __idmap_kpti_put_pgtable_ent_ng, type
208 orr \type, \type, #PTE_NG // Same bit for blocks and pages
209 str \type, [cur_\()\type\()p] // Update the entry and ensure
210 dmb sy // that it is visible to all
211 dc civac, cur_\()\type\()p // CPUs.
215 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
217 * Called exactly once from stop_machine context by each CPU found during boot.
221 ENTRY(idmap_kpti_install_ng_mappings)
240 mrs swapper_ttb, ttbr1_el1
241 adr flag_ptr, __idmap_kpti_flag
243 cbnz cpu, __idmap_kpti_secondary
245 /* We're the boot CPU. Wait for the others to catch up */
248 ldaxr w18, [flag_ptr]
249 eor w18, w18, num_cpus
252 /* We need to walk swapper, so turn off the MMU. */
254 bic x18, x18, #SCTLR_ELx_M
258 /* Everybody is enjoying the idmap, so we can rewrite swapper. */
260 mov cur_pgdp, swapper_pa
261 add end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
262 do_pgd: __idmap_kpti_get_pgtable_ent pgd
263 tbnz pgd, #1, walk_puds
265 __idmap_kpti_put_pgtable_ent_ng pgd
267 add cur_pgdp, cur_pgdp, #8
268 cmp cur_pgdp, end_pgdp
271 /* Publish the updated tables and nuke all the TLBs */
277 /* We're done: fire up the MMU again */
279 orr x18, x18, #SCTLR_ELx_M
284 * Invalidate the local I-cache so that any instructions fetched
285 * speculatively from the PoC are discarded, since they may have
286 * been dynamically patched at the PoU.
292 /* Set the flag to zero to indicate that we're all done */
298 .if CONFIG_PGTABLE_LEVELS > 3
299 pte_to_phys cur_pudp, pgd
300 add end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
301 do_pud: __idmap_kpti_get_pgtable_ent pud
302 tbnz pud, #1, walk_pmds
304 __idmap_kpti_put_pgtable_ent_ng pud
306 add cur_pudp, cur_pudp, 8
307 cmp cur_pudp, end_pudp
310 .else /* CONFIG_PGTABLE_LEVELS <= 3 */
319 .if CONFIG_PGTABLE_LEVELS > 2
320 pte_to_phys cur_pmdp, pud
321 add end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
322 do_pmd: __idmap_kpti_get_pgtable_ent pmd
323 tbnz pmd, #1, walk_ptes
325 __idmap_kpti_put_pgtable_ent_ng pmd
327 add cur_pmdp, cur_pmdp, #8
328 cmp cur_pmdp, end_pmdp
331 .else /* CONFIG_PGTABLE_LEVELS <= 2 */
340 pte_to_phys cur_ptep, pmd
341 add end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
342 do_pte: __idmap_kpti_get_pgtable_ent pte
343 __idmap_kpti_put_pgtable_ent_ng pte
345 add cur_ptep, cur_ptep, #8
346 cmp cur_ptep, end_ptep
350 /* Secondary CPUs end up here */
351 __idmap_kpti_secondary:
352 /* Uninstall swapper before surgery begins */
353 __idmap_cpu_set_reserved_ttbr1 x18, x17
355 /* Increment the flag to let the boot CPU we're ready */
356 1: ldxr w18, [flag_ptr]
358 stxr w17, w18, [flag_ptr]
361 /* Wait for the boot CPU to finish messing around with swapper */
367 /* All done, act like nothing happened */
368 msr ttbr1_el1, swapper_ttb
389 ENDPROC(idmap_kpti_install_ng_mappings)
396 * Initialise the processor for turning the MMU on. Return in x0 the
397 * value of the SCTLR_EL1 register.
399 .pushsection ".idmap.text", "awx"
401 tlbi vmalle1 // Invalidate local TLB
405 msr cpacr_el1, x0 // Enable FP/ASIMD
406 mov x0, #1 << 12 // Reset mdscr_el1 and disable
407 msr mdscr_el1, x0 // access to the DCC from EL0
408 isb // Unmask debug exceptions now,
409 enable_dbg // since this is per-cpu
410 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
412 * Memory region attributes for LPAE:
416 * DEVICE_nGnRnE 000 00000000
417 * DEVICE_nGnRE 001 00000100
418 * DEVICE_GRE 010 00001100
419 * NORMAL_NC 011 01000100
420 * NORMAL 100 11111111
421 * NORMAL_WT 101 10111011
423 ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
424 MAIR(0x04, MT_DEVICE_nGnRE) | \
425 MAIR(0x0c, MT_DEVICE_GRE) | \
426 MAIR(0x44, MT_NORMAL_NC) | \
427 MAIR(0xff, MT_NORMAL) | \
428 MAIR(0xbb, MT_NORMAL_WT)
433 mov_q x0, SCTLR_EL1_SET
435 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
436 * both user and kernel.
438 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
439 TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0 | TCR_A1
440 tcr_set_idmap_t0sz x10, x9
443 * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in
446 mrs x9, ID_AA64MMFR0_EL1
448 #ifdef CONFIG_ARM64_HW_AFDBM
450 * Hardware update of the Access and Dirty bits.
452 mrs x9, ID_AA64MMFR1_EL1
457 #ifdef CONFIG_ARM64_ERRATUM_1024718
458 /* Disable hardware DBM on Cortex-A55 all versions */
459 cpu_midr_match MIDR_CORTEX_A55, MIDR_CPU_VAR_REV(0, 0), MIDR_CPU_VAR_REV(0xf, 0xf), x1, x2, x3, x4
462 orr x10, x10, #TCR_HD // hardware Dirty flag update
463 1: orr x10, x10, #TCR_HA // hardware Access flag update
465 #endif /* CONFIG_ARM64_HW_AFDBM */
467 ret // return to head.S