1 // SPDX-License-Identifier: GPL-2.0
3 * PCI detection and setup code
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/init.h>
10 #include <linux/msi.h>
11 #include <linux/of_device.h>
12 #include <linux/of_pci.h>
13 #include <linux/pci_hotplug.h>
14 #include <linux/slab.h>
15 #include <linux/module.h>
16 #include <linux/cpumask.h>
17 #include <linux/aer.h>
18 #include <linux/acpi.h>
19 #include <linux/hypervisor.h>
20 #include <linux/irqdomain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/bitfield.h>
25 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
26 #define CARDBUS_RESERVE_BUSNR 3
28 static struct resource busn_resource = {
32 .flags = IORESOURCE_BUS,
35 /* Ugh. Need to stop exporting this to modules. */
36 LIST_HEAD(pci_root_buses);
37 EXPORT_SYMBOL(pci_root_buses);
39 static LIST_HEAD(pci_domain_busn_res_list);
41 struct pci_domain_busn_res {
42 struct list_head list;
47 static struct resource *get_pci_domain_busn_res(int domain_nr)
49 struct pci_domain_busn_res *r;
51 list_for_each_entry(r, &pci_domain_busn_res_list, list)
52 if (r->domain_nr == domain_nr)
55 r = kzalloc(sizeof(*r), GFP_KERNEL);
59 r->domain_nr = domain_nr;
62 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
64 list_add_tail(&r->list, &pci_domain_busn_res_list);
70 * Some device drivers need know if PCI is initiated.
71 * Basically, we think PCI is not initiated when there
72 * is no device to be found on the pci_bus_type.
74 int no_pci_devices(void)
79 dev = bus_find_next_device(&pci_bus_type, NULL);
80 no_devices = (dev == NULL);
84 EXPORT_SYMBOL(no_pci_devices);
89 static void release_pcibus_dev(struct device *dev)
91 struct pci_bus *pci_bus = to_pci_bus(dev);
93 put_device(pci_bus->bridge);
94 pci_bus_remove_resources(pci_bus);
95 pci_release_bus_of_node(pci_bus);
99 static struct class pcibus_class = {
101 .dev_release = &release_pcibus_dev,
102 .dev_groups = pcibus_groups,
105 static int __init pcibus_class_init(void)
107 return class_register(&pcibus_class);
109 postcore_initcall(pcibus_class_init);
111 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
113 u64 size = mask & maxbase; /* Find the significant bits */
118 * Get the lowest of them to find the decode size, and from that
121 size = size & ~(size-1);
124 * base == maxbase can be valid only if the BAR has already been
125 * programmed with all 1s.
127 if (base == maxbase && ((base | (size - 1)) & mask) != mask)
133 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
138 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
139 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
140 flags |= IORESOURCE_IO;
144 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
145 flags |= IORESOURCE_MEM;
146 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
147 flags |= IORESOURCE_PREFETCH;
149 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
151 case PCI_BASE_ADDRESS_MEM_TYPE_32:
153 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
154 /* 1M mem BAR treated as 32-bit BAR */
156 case PCI_BASE_ADDRESS_MEM_TYPE_64:
157 flags |= IORESOURCE_MEM_64;
160 /* mem unknown type treated as 32-bit BAR */
166 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
169 * pci_read_base - Read a PCI BAR
170 * @dev: the PCI device
171 * @type: type of the BAR
172 * @res: resource buffer to be filled in
173 * @pos: BAR position in the config space
175 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
177 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
178 struct resource *res, unsigned int pos)
180 u32 l = 0, sz = 0, mask;
181 u64 l64, sz64, mask64;
183 struct pci_bus_region region, inverted_region;
185 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
187 /* No printks while decoding is disabled! */
188 if (!dev->mmio_always_on) {
189 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
190 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
191 pci_write_config_word(dev, PCI_COMMAND,
192 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
196 res->name = pci_name(dev);
198 pci_read_config_dword(dev, pos, &l);
199 pci_write_config_dword(dev, pos, l | mask);
200 pci_read_config_dword(dev, pos, &sz);
201 pci_write_config_dword(dev, pos, l);
204 * All bits set in sz means the device isn't working properly.
205 * If the BAR isn't implemented, all bits must be 0. If it's a
206 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
209 if (sz == 0xffffffff)
213 * I don't know how l can have all bits set. Copied from old code.
214 * Maybe it fixes a bug on some ancient platform.
219 if (type == pci_bar_unknown) {
220 res->flags = decode_bar(dev, l);
221 res->flags |= IORESOURCE_SIZEALIGN;
222 if (res->flags & IORESOURCE_IO) {
223 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
224 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
225 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
227 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
228 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
229 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
232 if (l & PCI_ROM_ADDRESS_ENABLE)
233 res->flags |= IORESOURCE_ROM_ENABLE;
234 l64 = l & PCI_ROM_ADDRESS_MASK;
235 sz64 = sz & PCI_ROM_ADDRESS_MASK;
236 mask64 = PCI_ROM_ADDRESS_MASK;
239 if (res->flags & IORESOURCE_MEM_64) {
240 pci_read_config_dword(dev, pos + 4, &l);
241 pci_write_config_dword(dev, pos + 4, ~0);
242 pci_read_config_dword(dev, pos + 4, &sz);
243 pci_write_config_dword(dev, pos + 4, l);
245 l64 |= ((u64)l << 32);
246 sz64 |= ((u64)sz << 32);
247 mask64 |= ((u64)~0 << 32);
250 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
251 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
256 sz64 = pci_size(l64, sz64, mask64);
258 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
263 if (res->flags & IORESOURCE_MEM_64) {
264 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
265 && sz64 > 0x100000000ULL) {
266 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
269 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
270 pos, (unsigned long long)sz64);
274 if ((sizeof(pci_bus_addr_t) < 8) && l) {
275 /* Above 32-bit boundary; try to reallocate */
276 res->flags |= IORESOURCE_UNSET;
279 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
280 pos, (unsigned long long)l64);
286 region.end = l64 + sz64 - 1;
288 pcibios_bus_to_resource(dev->bus, res, ®ion);
289 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
292 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
293 * the corresponding resource address (the physical address used by
294 * the CPU. Converting that resource address back to a bus address
295 * should yield the original BAR value:
297 * resource_to_bus(bus_to_resource(A)) == A
299 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
300 * be claimed by the device.
302 if (inverted_region.start != region.start) {
303 res->flags |= IORESOURCE_UNSET;
305 res->end = region.end - region.start;
306 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
307 pos, (unsigned long long)region.start);
317 pci_info(dev, "reg 0x%x: %pR\n", pos, res);
319 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
322 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
324 unsigned int pos, reg;
326 if (dev->non_compliant_bars)
329 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
333 for (pos = 0; pos < howmany; pos++) {
334 struct resource *res = &dev->resource[pos];
335 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
336 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
340 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
341 dev->rom_base_reg = rom;
342 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
343 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
344 __pci_read_base(dev, pci_bar_mem32, res, rom);
348 static void pci_read_bridge_windows(struct pci_dev *bridge)
353 pci_read_config_word(bridge, PCI_IO_BASE, &io);
355 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
356 pci_read_config_word(bridge, PCI_IO_BASE, &io);
357 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
360 bridge->io_window = 1;
363 * DECchip 21050 pass 2 errata: the bridge may miss an address
364 * disconnect boundary by one PCI data phase. Workaround: do not
365 * use prefetching on this device.
367 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
370 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
372 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
374 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
375 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
380 bridge->pref_window = 1;
382 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
385 * Bridge claims to have a 64-bit prefetchable memory
386 * window; verify that the upper bits are actually
389 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
390 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
392 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
393 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
395 bridge->pref_64_window = 1;
399 static void pci_read_bridge_io(struct pci_bus *child)
401 struct pci_dev *dev = child->self;
402 u8 io_base_lo, io_limit_lo;
403 unsigned long io_mask, io_granularity, base, limit;
404 struct pci_bus_region region;
405 struct resource *res;
407 io_mask = PCI_IO_RANGE_MASK;
408 io_granularity = 0x1000;
409 if (dev->io_window_1k) {
410 /* Support 1K I/O space granularity */
411 io_mask = PCI_IO_1K_RANGE_MASK;
412 io_granularity = 0x400;
415 res = child->resource[0];
416 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
417 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
418 base = (io_base_lo & io_mask) << 8;
419 limit = (io_limit_lo & io_mask) << 8;
421 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
422 u16 io_base_hi, io_limit_hi;
424 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
425 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
426 base |= ((unsigned long) io_base_hi << 16);
427 limit |= ((unsigned long) io_limit_hi << 16);
431 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
433 region.end = limit + io_granularity - 1;
434 pcibios_bus_to_resource(dev->bus, res, ®ion);
435 pci_info(dev, " bridge window %pR\n", res);
439 static void pci_read_bridge_mmio(struct pci_bus *child)
441 struct pci_dev *dev = child->self;
442 u16 mem_base_lo, mem_limit_lo;
443 unsigned long base, limit;
444 struct pci_bus_region region;
445 struct resource *res;
447 res = child->resource[1];
448 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
449 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
450 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
451 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
453 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
455 region.end = limit + 0xfffff;
456 pcibios_bus_to_resource(dev->bus, res, ®ion);
457 pci_info(dev, " bridge window %pR\n", res);
461 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
463 struct pci_dev *dev = child->self;
464 u16 mem_base_lo, mem_limit_lo;
466 pci_bus_addr_t base, limit;
467 struct pci_bus_region region;
468 struct resource *res;
470 res = child->resource[2];
471 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
472 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
473 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
474 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
476 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
477 u32 mem_base_hi, mem_limit_hi;
479 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
480 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
483 * Some bridges set the base > limit by default, and some
484 * (broken) BIOSes do not initialize them. If we find
485 * this, just assume they are not being used.
487 if (mem_base_hi <= mem_limit_hi) {
488 base64 |= (u64) mem_base_hi << 32;
489 limit64 |= (u64) mem_limit_hi << 32;
493 base = (pci_bus_addr_t) base64;
494 limit = (pci_bus_addr_t) limit64;
496 if (base != base64) {
497 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
498 (unsigned long long) base64);
503 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
504 IORESOURCE_MEM | IORESOURCE_PREFETCH;
505 if (res->flags & PCI_PREF_RANGE_TYPE_64)
506 res->flags |= IORESOURCE_MEM_64;
508 region.end = limit + 0xfffff;
509 pcibios_bus_to_resource(dev->bus, res, ®ion);
510 pci_info(dev, " bridge window %pR\n", res);
514 void pci_read_bridge_bases(struct pci_bus *child)
516 struct pci_dev *dev = child->self;
517 struct resource *res;
520 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
523 pci_info(dev, "PCI bridge to %pR%s\n",
525 dev->transparent ? " (subtractive decode)" : "");
527 pci_bus_remove_resources(child);
528 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
529 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
531 pci_read_bridge_io(child);
532 pci_read_bridge_mmio(child);
533 pci_read_bridge_mmio_pref(child);
535 if (dev->transparent) {
536 pci_bus_for_each_resource(child->parent, res, i) {
537 if (res && res->flags) {
538 pci_bus_add_resource(child, res,
539 PCI_SUBTRACTIVE_DECODE);
540 pci_info(dev, " bridge window %pR (subtractive decode)\n",
547 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
551 b = kzalloc(sizeof(*b), GFP_KERNEL);
555 INIT_LIST_HEAD(&b->node);
556 INIT_LIST_HEAD(&b->children);
557 INIT_LIST_HEAD(&b->devices);
558 INIT_LIST_HEAD(&b->slots);
559 INIT_LIST_HEAD(&b->resources);
560 b->max_bus_speed = PCI_SPEED_UNKNOWN;
561 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
562 #ifdef CONFIG_PCI_DOMAINS_GENERIC
564 b->domain_nr = parent->domain_nr;
569 static void pci_release_host_bridge_dev(struct device *dev)
571 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
573 if (bridge->release_fn)
574 bridge->release_fn(bridge);
576 pci_free_resource_list(&bridge->windows);
577 pci_free_resource_list(&bridge->dma_ranges);
581 static void pci_init_host_bridge(struct pci_host_bridge *bridge)
583 INIT_LIST_HEAD(&bridge->windows);
584 INIT_LIST_HEAD(&bridge->dma_ranges);
587 * We assume we can manage these PCIe features. Some systems may
588 * reserve these for use by the platform itself, e.g., an ACPI BIOS
589 * may implement its own AER handling and use _OSC to prevent the
590 * OS from interfering.
592 bridge->native_aer = 1;
593 bridge->native_pcie_hotplug = 1;
594 bridge->native_shpc_hotplug = 1;
595 bridge->native_pme = 1;
596 bridge->native_ltr = 1;
597 bridge->native_dpc = 1;
599 device_initialize(&bridge->dev);
602 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
604 struct pci_host_bridge *bridge;
606 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
610 pci_init_host_bridge(bridge);
611 bridge->dev.release = pci_release_host_bridge_dev;
615 EXPORT_SYMBOL(pci_alloc_host_bridge);
617 static void devm_pci_alloc_host_bridge_release(void *data)
619 pci_free_host_bridge(data);
622 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
626 struct pci_host_bridge *bridge;
628 bridge = pci_alloc_host_bridge(priv);
632 bridge->dev.parent = dev;
634 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release,
639 ret = devm_of_pci_bridge_init(dev, bridge);
645 EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
647 void pci_free_host_bridge(struct pci_host_bridge *bridge)
649 put_device(&bridge->dev);
651 EXPORT_SYMBOL(pci_free_host_bridge);
653 /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */
654 static const unsigned char pcix_bus_speed[] = {
655 PCI_SPEED_UNKNOWN, /* 0 */
656 PCI_SPEED_66MHz_PCIX, /* 1 */
657 PCI_SPEED_100MHz_PCIX, /* 2 */
658 PCI_SPEED_133MHz_PCIX, /* 3 */
659 PCI_SPEED_UNKNOWN, /* 4 */
660 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
661 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
662 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
663 PCI_SPEED_UNKNOWN, /* 8 */
664 PCI_SPEED_66MHz_PCIX_266, /* 9 */
665 PCI_SPEED_100MHz_PCIX_266, /* A */
666 PCI_SPEED_133MHz_PCIX_266, /* B */
667 PCI_SPEED_UNKNOWN, /* C */
668 PCI_SPEED_66MHz_PCIX_533, /* D */
669 PCI_SPEED_100MHz_PCIX_533, /* E */
670 PCI_SPEED_133MHz_PCIX_533 /* F */
673 /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */
674 const unsigned char pcie_link_speed[] = {
675 PCI_SPEED_UNKNOWN, /* 0 */
676 PCIE_SPEED_2_5GT, /* 1 */
677 PCIE_SPEED_5_0GT, /* 2 */
678 PCIE_SPEED_8_0GT, /* 3 */
679 PCIE_SPEED_16_0GT, /* 4 */
680 PCIE_SPEED_32_0GT, /* 5 */
681 PCI_SPEED_UNKNOWN, /* 6 */
682 PCI_SPEED_UNKNOWN, /* 7 */
683 PCI_SPEED_UNKNOWN, /* 8 */
684 PCI_SPEED_UNKNOWN, /* 9 */
685 PCI_SPEED_UNKNOWN, /* A */
686 PCI_SPEED_UNKNOWN, /* B */
687 PCI_SPEED_UNKNOWN, /* C */
688 PCI_SPEED_UNKNOWN, /* D */
689 PCI_SPEED_UNKNOWN, /* E */
690 PCI_SPEED_UNKNOWN /* F */
692 EXPORT_SYMBOL_GPL(pcie_link_speed);
694 const char *pci_speed_string(enum pci_bus_speed speed)
696 /* Indexed by the pci_bus_speed enum */
697 static const char *speed_strings[] = {
698 "33 MHz PCI", /* 0x00 */
699 "66 MHz PCI", /* 0x01 */
700 "66 MHz PCI-X", /* 0x02 */
701 "100 MHz PCI-X", /* 0x03 */
702 "133 MHz PCI-X", /* 0x04 */
707 "66 MHz PCI-X 266", /* 0x09 */
708 "100 MHz PCI-X 266", /* 0x0a */
709 "133 MHz PCI-X 266", /* 0x0b */
710 "Unknown AGP", /* 0x0c */
715 "66 MHz PCI-X 533", /* 0x11 */
716 "100 MHz PCI-X 533", /* 0x12 */
717 "133 MHz PCI-X 533", /* 0x13 */
718 "2.5 GT/s PCIe", /* 0x14 */
719 "5.0 GT/s PCIe", /* 0x15 */
720 "8.0 GT/s PCIe", /* 0x16 */
721 "16.0 GT/s PCIe", /* 0x17 */
722 "32.0 GT/s PCIe", /* 0x18 */
725 if (speed < ARRAY_SIZE(speed_strings))
726 return speed_strings[speed];
729 EXPORT_SYMBOL_GPL(pci_speed_string);
731 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
733 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
735 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
737 static unsigned char agp_speeds[] = {
745 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
751 else if (agpstat & 2)
753 else if (agpstat & 1)
765 return agp_speeds[index];
768 static void pci_set_bus_speed(struct pci_bus *bus)
770 struct pci_dev *bridge = bus->self;
773 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
775 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
779 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
780 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
782 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
783 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
786 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
789 enum pci_bus_speed max;
791 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
794 if (status & PCI_X_SSTATUS_533MHZ) {
795 max = PCI_SPEED_133MHz_PCIX_533;
796 } else if (status & PCI_X_SSTATUS_266MHZ) {
797 max = PCI_SPEED_133MHz_PCIX_266;
798 } else if (status & PCI_X_SSTATUS_133MHZ) {
799 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
800 max = PCI_SPEED_133MHz_PCIX_ECC;
802 max = PCI_SPEED_133MHz_PCIX;
804 max = PCI_SPEED_66MHz_PCIX;
807 bus->max_bus_speed = max;
808 bus->cur_bus_speed = pcix_bus_speed[
809 (status & PCI_X_SSTATUS_FREQ) >> 6];
814 if (pci_is_pcie(bridge)) {
818 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
819 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
820 bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC);
822 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
823 pcie_update_link_speed(bus, linksta);
827 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
829 struct irq_domain *d;
832 * Any firmware interface that can resolve the msi_domain
833 * should be called from here.
835 d = pci_host_bridge_of_msi_domain(bus);
837 d = pci_host_bridge_acpi_msi_domain(bus);
839 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
841 * If no IRQ domain was found via the OF tree, try looking it up
842 * directly through the fwnode_handle.
845 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
848 d = irq_find_matching_fwnode(fwnode,
856 static void pci_set_bus_msi_domain(struct pci_bus *bus)
858 struct irq_domain *d;
862 * The bus can be a root bus, a subordinate bus, or a virtual bus
863 * created by an SR-IOV device. Walk up to the first bridge device
864 * found or derive the domain from the host bridge.
866 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
868 d = dev_get_msi_domain(&b->self->dev);
872 d = pci_host_bridge_msi_domain(b);
874 dev_set_msi_domain(&bus->dev, d);
877 static int pci_register_host_bridge(struct pci_host_bridge *bridge)
879 struct device *parent = bridge->dev.parent;
880 struct resource_entry *window, *n;
881 struct pci_bus *bus, *b;
882 resource_size_t offset;
883 LIST_HEAD(resources);
884 struct resource *res;
889 bus = pci_alloc_bus(NULL);
895 /* Temporarily move resources off the list */
896 list_splice_init(&bridge->windows, &resources);
897 bus->sysdata = bridge->sysdata;
898 bus->msi = bridge->msi;
899 bus->ops = bridge->ops;
900 bus->number = bus->busn_res.start = bridge->busnr;
901 #ifdef CONFIG_PCI_DOMAINS_GENERIC
902 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
905 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
907 /* Ignore it if we already got here via a different bridge */
908 dev_dbg(&b->dev, "bus already known\n");
913 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
916 err = pcibios_root_bridge_prepare(bridge);
920 err = device_add(&bridge->dev);
922 put_device(&bridge->dev);
925 bus->bridge = get_device(&bridge->dev);
926 device_enable_async_suspend(bus->bridge);
927 pci_set_bus_of_node(bus);
928 pci_set_bus_msi_domain(bus);
931 set_dev_node(bus->bridge, pcibus_to_node(bus));
933 bus->dev.class = &pcibus_class;
934 bus->dev.parent = bus->bridge;
936 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
937 name = dev_name(&bus->dev);
939 err = device_register(&bus->dev);
943 pcibios_add_bus(bus);
945 if (bus->ops->add_bus) {
946 err = bus->ops->add_bus(bus);
947 if (WARN_ON(err < 0))
948 dev_err(&bus->dev, "failed to add bus: %d\n", err);
951 /* Create legacy_io and legacy_mem files for this bus */
952 pci_create_legacy_files(bus);
955 dev_info(parent, "PCI host bridge to bus %s\n", name);
957 pr_info("PCI host bridge to bus %s\n", name);
959 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE)
960 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n");
962 /* Add initial resources to the bus */
963 resource_list_for_each_entry_safe(window, n, &resources) {
964 list_move_tail(&window->node, &bridge->windows);
965 offset = window->offset;
968 if (res->flags & IORESOURCE_BUS)
969 pci_bus_insert_busn_res(bus, bus->number, res->end);
971 pci_bus_add_resource(bus, res, 0);
974 if (resource_type(res) == IORESOURCE_IO)
975 fmt = " (bus address [%#06llx-%#06llx])";
977 fmt = " (bus address [%#010llx-%#010llx])";
979 snprintf(addr, sizeof(addr), fmt,
980 (unsigned long long)(res->start - offset),
981 (unsigned long long)(res->end - offset));
985 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
988 down_write(&pci_bus_sem);
989 list_add_tail(&bus->node, &pci_root_buses);
990 up_write(&pci_bus_sem);
995 put_device(&bridge->dev);
996 device_del(&bridge->dev);
1003 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
1009 * If extended config space isn't accessible on a bridge's primary
1010 * bus, we certainly can't access it on the secondary bus.
1012 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1016 * PCIe Root Ports and switch ports are PCIe on both sides, so if
1017 * extended config space is accessible on the primary, it's also
1018 * accessible on the secondary.
1020 if (pci_is_pcie(bridge) &&
1021 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
1022 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
1023 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
1027 * For the other bridge types:
1028 * - PCI-to-PCI bridges
1029 * - PCIe-to-PCI/PCI-X forward bridges
1030 * - PCI/PCI-X-to-PCIe reverse bridges
1031 * extended config space on the secondary side is only accessible
1032 * if the bridge supports PCI-X Mode 2.
1034 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
1038 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
1039 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
1042 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
1043 struct pci_dev *bridge, int busnr)
1045 struct pci_bus *child;
1046 struct pci_host_bridge *host;
1050 /* Allocate a new bus and inherit stuff from the parent */
1051 child = pci_alloc_bus(parent);
1055 child->parent = parent;
1056 child->msi = parent->msi;
1057 child->sysdata = parent->sysdata;
1058 child->bus_flags = parent->bus_flags;
1060 host = pci_find_host_bridge(parent);
1061 if (host->child_ops)
1062 child->ops = host->child_ops;
1064 child->ops = parent->ops;
1067 * Initialize some portions of the bus device, but don't register
1068 * it now as the parent is not properly set up yet.
1070 child->dev.class = &pcibus_class;
1071 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
1073 /* Set up the primary, secondary and subordinate bus numbers */
1074 child->number = child->busn_res.start = busnr;
1075 child->primary = parent->busn_res.start;
1076 child->busn_res.end = 0xff;
1079 child->dev.parent = parent->bridge;
1083 child->self = bridge;
1084 child->bridge = get_device(&bridge->dev);
1085 child->dev.parent = child->bridge;
1086 pci_set_bus_of_node(child);
1087 pci_set_bus_speed(child);
1090 * Check whether extended config space is accessible on the child
1091 * bus. Note that we currently assume it is always accessible on
1094 if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
1095 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
1096 pci_info(child, "extended config space not accessible\n");
1099 /* Set up default resource pointers and names */
1100 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
1101 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
1102 child->resource[i]->name = child->name;
1104 bridge->subordinate = child;
1107 pci_set_bus_msi_domain(child);
1108 ret = device_register(&child->dev);
1111 pcibios_add_bus(child);
1113 if (child->ops->add_bus) {
1114 ret = child->ops->add_bus(child);
1115 if (WARN_ON(ret < 0))
1116 dev_err(&child->dev, "failed to add bus: %d\n", ret);
1119 /* Create legacy_io and legacy_mem files for this bus */
1120 pci_create_legacy_files(child);
1125 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1128 struct pci_bus *child;
1130 child = pci_alloc_child_bus(parent, dev, busnr);
1132 down_write(&pci_bus_sem);
1133 list_add_tail(&child->node, &parent->children);
1134 up_write(&pci_bus_sem);
1138 EXPORT_SYMBOL(pci_add_new_bus);
1140 static void pci_enable_crs(struct pci_dev *pdev)
1144 /* Enable CRS Software Visibility if supported */
1145 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
1146 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
1147 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
1148 PCI_EXP_RTCTL_CRSSVE);
1151 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
1152 unsigned int available_buses);
1154 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1155 * numbers from EA capability.
1157 * @sec: updated with secondary bus number from EA
1158 * @sub: updated with subordinate bus number from EA
1160 * If @dev is a bridge with EA capability that specifies valid secondary
1161 * and subordinate bus numbers, return true with the bus numbers in @sec
1162 * and @sub. Otherwise return false.
1164 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
1170 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
1173 /* find PCI EA capability in list */
1174 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
1178 offset = ea + PCI_EA_FIRST_ENT;
1179 pci_read_config_dword(dev, offset, &dw);
1180 ea_sec = dw & PCI_EA_SEC_BUS_MASK;
1181 ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT;
1182 if (ea_sec == 0 || ea_sub < ea_sec)
1191 * pci_scan_bridge_extend() - Scan buses behind a bridge
1192 * @bus: Parent bus the bridge is on
1193 * @dev: Bridge itself
1194 * @max: Starting subordinate number of buses behind this bridge
1195 * @available_buses: Total number of buses available for this bridge and
1196 * the devices below. After the minimal bus space has
1197 * been allocated the remaining buses will be
1198 * distributed equally between hotplug-capable bridges.
1199 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1200 * that need to be reconfigured.
1202 * If it's a bridge, configure it and scan the bus behind it.
1203 * For CardBus bridges, we don't scan behind as the devices will
1204 * be handled by the bridge driver itself.
1206 * We need to process bridges in two passes -- first we scan those
1207 * already configured by the BIOS and after we are done with all of
1208 * them, we proceed to assigning numbers to the remaining buses in
1209 * order to avoid overlaps between old and new bus numbers.
1211 * Return: New subordinate number covering all buses behind this bridge.
1213 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1214 int max, unsigned int available_buses,
1217 struct pci_bus *child;
1218 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1219 u32 buses, i, j = 0;
1221 u8 primary, secondary, subordinate;
1224 u8 fixed_sec, fixed_sub;
1228 * Make sure the bridge is powered on to be able to access config
1229 * space of devices below it.
1231 pm_runtime_get_sync(&dev->dev);
1233 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1234 primary = buses & 0xFF;
1235 secondary = (buses >> 8) & 0xFF;
1236 subordinate = (buses >> 16) & 0xFF;
1238 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1239 secondary, subordinate, pass);
1241 if (!primary && (primary != bus->number) && secondary && subordinate) {
1242 pci_warn(dev, "Primary bus is hard wired to 0\n");
1243 primary = bus->number;
1246 /* Check if setup is sensible at all */
1248 (primary != bus->number || secondary <= bus->number ||
1249 secondary > subordinate)) {
1250 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1251 secondary, subordinate);
1256 * Disable Master-Abort Mode during probing to avoid reporting of
1257 * bus errors in some architectures.
1259 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1260 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1261 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1263 pci_enable_crs(dev);
1265 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1266 !is_cardbus && !broken) {
1270 * Bus already configured by firmware, process it in the
1271 * first pass and just note the configuration.
1277 * The bus might already exist for two reasons: Either we
1278 * are rescanning the bus or the bus is reachable through
1279 * more than one bridge. The second case can happen with
1280 * the i450NX chipset.
1282 child = pci_find_bus(pci_domain_nr(bus), secondary);
1284 child = pci_add_new_bus(bus, dev, secondary);
1287 child->primary = primary;
1288 pci_bus_insert_busn_res(child, secondary, subordinate);
1289 child->bridge_ctl = bctl;
1292 cmax = pci_scan_child_bus(child);
1293 if (cmax > subordinate)
1294 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1297 /* Subordinate should equal child->busn_res.end */
1298 if (subordinate > max)
1303 * We need to assign a number to this bus which we always
1304 * do in the second pass.
1307 if (pcibios_assign_all_busses() || broken || is_cardbus)
1310 * Temporarily disable forwarding of the
1311 * configuration cycles on all bridges in
1312 * this bus segment to avoid possible
1313 * conflicts in the second pass between two
1314 * bridges programmed with overlapping bus
1317 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1323 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1325 /* Read bus numbers from EA Capability (if present) */
1326 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
1328 next_busnr = fixed_sec;
1330 next_busnr = max + 1;
1333 * Prevent assigning a bus number that already exists.
1334 * This can happen when a bridge is hot-plugged, so in this
1335 * case we only re-scan this bus.
1337 child = pci_find_bus(pci_domain_nr(bus), next_busnr);
1339 child = pci_add_new_bus(bus, dev, next_busnr);
1342 pci_bus_insert_busn_res(child, next_busnr,
1346 if (available_buses)
1349 buses = (buses & 0xff000000)
1350 | ((unsigned int)(child->primary) << 0)
1351 | ((unsigned int)(child->busn_res.start) << 8)
1352 | ((unsigned int)(child->busn_res.end) << 16);
1355 * yenta.c forces a secondary latency timer of 176.
1356 * Copy that behaviour here.
1359 buses &= ~0xff000000;
1360 buses |= CARDBUS_LATENCY_TIMER << 24;
1363 /* We need to blast all three values with a single write */
1364 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1367 child->bridge_ctl = bctl;
1368 max = pci_scan_child_bus_extend(child, available_buses);
1372 * For CardBus bridges, we leave 4 bus numbers as
1373 * cards with a PCI-to-PCI bridge can be inserted
1376 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1377 struct pci_bus *parent = bus;
1378 if (pci_find_bus(pci_domain_nr(bus),
1381 while (parent->parent) {
1382 if ((!pcibios_assign_all_busses()) &&
1383 (parent->busn_res.end > max) &&
1384 (parent->busn_res.end <= max+i)) {
1387 parent = parent->parent;
1392 * Often, there are two CardBus
1393 * bridges -- try to leave one
1394 * valid bus number for each one.
1404 * Set subordinate bus number to its real value.
1405 * If fixed subordinate bus number exists from EA
1406 * capability then use it.
1410 pci_bus_update_busn_res_end(child, max);
1411 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1414 sprintf(child->name,
1415 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1416 pci_domain_nr(bus), child->number);
1418 /* Check that all devices are accessible */
1419 while (bus->parent) {
1420 if ((child->busn_res.end > bus->busn_res.end) ||
1421 (child->number > bus->busn_res.end) ||
1422 (child->number < bus->number) ||
1423 (child->busn_res.end < bus->number)) {
1424 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1432 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1434 pm_runtime_put(&dev->dev);
1440 * pci_scan_bridge() - Scan buses behind a bridge
1441 * @bus: Parent bus the bridge is on
1442 * @dev: Bridge itself
1443 * @max: Starting subordinate number of buses behind this bridge
1444 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1445 * that need to be reconfigured.
1447 * If it's a bridge, configure it and scan the bus behind it.
1448 * For CardBus bridges, we don't scan behind as the devices will
1449 * be handled by the bridge driver itself.
1451 * We need to process bridges in two passes -- first we scan those
1452 * already configured by the BIOS and after we are done with all of
1453 * them, we proceed to assigning numbers to the remaining buses in
1454 * order to avoid overlaps between old and new bus numbers.
1456 * Return: New subordinate number covering all buses behind this bridge.
1458 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1460 return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1462 EXPORT_SYMBOL(pci_scan_bridge);
1465 * Read interrupt line and base address registers.
1466 * The architecture-dependent code can tweak these, of course.
1468 static void pci_read_irq(struct pci_dev *dev)
1472 /* VFs are not allowed to use INTx, so skip the config reads */
1473 if (dev->is_virtfn) {
1479 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1482 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1486 void set_pcie_port_type(struct pci_dev *pdev)
1491 struct pci_dev *parent;
1493 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1497 pdev->pcie_cap = pos;
1498 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1499 pdev->pcie_flags_reg = reg16;
1500 pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap);
1501 pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap);
1503 parent = pci_upstream_bridge(pdev);
1508 * Some systems do not identify their upstream/downstream ports
1509 * correctly so detect impossible configurations here and correct
1510 * the port type accordingly.
1512 type = pci_pcie_type(pdev);
1513 if (type == PCI_EXP_TYPE_DOWNSTREAM) {
1515 * If pdev claims to be downstream port but the parent
1516 * device is also downstream port assume pdev is actually
1519 if (pcie_downstream_port(parent)) {
1520 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n");
1521 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1522 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM;
1524 } else if (type == PCI_EXP_TYPE_UPSTREAM) {
1526 * If pdev claims to be upstream port but the parent
1527 * device is also upstream port assume pdev is actually
1530 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {
1531 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n");
1532 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1533 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM;
1538 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1542 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1543 if (reg32 & PCI_EXP_SLTCAP_HPC)
1544 pdev->is_hotplug_bridge = 1;
1547 static void set_pcie_thunderbolt(struct pci_dev *dev)
1552 while ((vsec = pci_find_next_ext_capability(dev, vsec,
1553 PCI_EXT_CAP_ID_VNDR))) {
1554 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
1556 /* Is the device part of a Thunderbolt controller? */
1557 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
1558 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) {
1559 dev->is_thunderbolt = 1;
1565 static void set_pcie_untrusted(struct pci_dev *dev)
1567 struct pci_dev *parent;
1570 * If the upstream bridge is untrusted we treat this device
1571 * untrusted as well.
1573 parent = pci_upstream_bridge(dev);
1574 if (parent && (parent->untrusted || parent->external_facing))
1575 dev->untrusted = true;
1579 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1582 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1583 * when forwarding a type1 configuration request the bridge must check that
1584 * the extended register address field is zero. The bridge is not permitted
1585 * to forward the transactions and must handle it as an Unsupported Request.
1586 * Some bridges do not follow this rule and simply drop the extended register
1587 * bits, resulting in the standard config space being aliased, every 256
1588 * bytes across the entire configuration space. Test for this condition by
1589 * comparing the first dword of each potential alias to the vendor/device ID.
1591 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1592 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1594 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1596 #ifdef CONFIG_PCI_QUIRKS
1600 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1602 for (pos = PCI_CFG_SPACE_SIZE;
1603 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1604 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1616 * pci_cfg_space_size - Get the configuration space size of the PCI device
1619 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1620 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1621 * access it. Maybe we don't have a way to generate extended config space
1622 * accesses, or the device is behind a reverse Express bridge. So we try
1623 * reading the dword at 0x100 which must either be 0 or a valid extended
1624 * capability header.
1626 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1629 int pos = PCI_CFG_SPACE_SIZE;
1631 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1632 return PCI_CFG_SPACE_SIZE;
1633 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1634 return PCI_CFG_SPACE_SIZE;
1636 return PCI_CFG_SPACE_EXP_SIZE;
1639 int pci_cfg_space_size(struct pci_dev *dev)
1645 #ifdef CONFIG_PCI_IOV
1647 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
1648 * implement a PCIe capability and therefore must implement extended
1649 * config space. We can skip the NO_EXTCFG test below and the
1650 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
1651 * the fact that the SR-IOV capability on the PF resides in extended
1652 * config space and must be accessible and non-aliased to have enabled
1653 * support for this VF. This is a micro performance optimization for
1654 * systems supporting many VFs.
1657 return PCI_CFG_SPACE_EXP_SIZE;
1660 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1661 return PCI_CFG_SPACE_SIZE;
1663 class = dev->class >> 8;
1664 if (class == PCI_CLASS_BRIDGE_HOST)
1665 return pci_cfg_space_size_ext(dev);
1667 if (pci_is_pcie(dev))
1668 return pci_cfg_space_size_ext(dev);
1670 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1672 return PCI_CFG_SPACE_SIZE;
1674 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1675 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1676 return pci_cfg_space_size_ext(dev);
1678 return PCI_CFG_SPACE_SIZE;
1681 static u32 pci_class(struct pci_dev *dev)
1685 #ifdef CONFIG_PCI_IOV
1687 return dev->physfn->sriov->class;
1689 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1693 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1695 #ifdef CONFIG_PCI_IOV
1696 if (dev->is_virtfn) {
1697 *vendor = dev->physfn->sriov->subsystem_vendor;
1698 *device = dev->physfn->sriov->subsystem_device;
1702 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1703 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1706 static u8 pci_hdr_type(struct pci_dev *dev)
1710 #ifdef CONFIG_PCI_IOV
1712 return dev->physfn->sriov->hdr_type;
1714 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1718 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1720 static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1723 * Disable the MSI hardware to avoid screaming interrupts
1724 * during boot. This is the power on reset default so
1725 * usually this should be a noop.
1727 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1729 pci_msi_set_enable(dev, 0);
1731 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1733 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1737 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1740 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1741 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1743 static int pci_intx_mask_broken(struct pci_dev *dev)
1745 u16 orig, toggle, new;
1747 pci_read_config_word(dev, PCI_COMMAND, &orig);
1748 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1749 pci_write_config_word(dev, PCI_COMMAND, toggle);
1750 pci_read_config_word(dev, PCI_COMMAND, &new);
1752 pci_write_config_word(dev, PCI_COMMAND, orig);
1755 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1756 * r2.3, so strictly speaking, a device is not *broken* if it's not
1757 * writable. But we'll live with the misnomer for now.
1764 static void early_dump_pci_device(struct pci_dev *pdev)
1769 pci_info(pdev, "config space:\n");
1771 for (i = 0; i < 256; i += 4)
1772 pci_read_config_dword(pdev, i, &value[i / 4]);
1774 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1779 * pci_setup_device - Fill in class and map information of a device
1780 * @dev: the device structure to fill
1782 * Initialize the device structure with information about the device's
1783 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1784 * Called at initialisation of the PCI subsystem and by CardBus services.
1785 * Returns 0 on success and negative if unknown type of device (not normal,
1786 * bridge or CardBus).
1788 int pci_setup_device(struct pci_dev *dev)
1794 struct pci_bus_region region;
1795 struct resource *res;
1797 hdr_type = pci_hdr_type(dev);
1799 dev->sysdata = dev->bus->sysdata;
1800 dev->dev.parent = dev->bus->bridge;
1801 dev->dev.bus = &pci_bus_type;
1802 dev->hdr_type = hdr_type & 0x7f;
1803 dev->multifunction = !!(hdr_type & 0x80);
1804 dev->error_state = pci_channel_io_normal;
1805 set_pcie_port_type(dev);
1807 pci_dev_assign_slot(dev);
1810 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1811 * set this higher, assuming the system even supports it.
1813 dev->dma_mask = 0xffffffff;
1815 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1816 dev->bus->number, PCI_SLOT(dev->devfn),
1817 PCI_FUNC(dev->devfn));
1819 class = pci_class(dev);
1821 dev->revision = class & 0xff;
1822 dev->class = class >> 8; /* upper 3 bytes */
1825 early_dump_pci_device(dev);
1827 /* Need to have dev->class ready */
1828 dev->cfg_size = pci_cfg_space_size(dev);
1830 /* Need to have dev->cfg_size ready */
1831 set_pcie_thunderbolt(dev);
1833 set_pcie_untrusted(dev);
1835 /* "Unknown power state" */
1836 dev->current_state = PCI_UNKNOWN;
1838 /* Early fixups, before probing the BARs */
1839 pci_fixup_device(pci_fixup_early, dev);
1841 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
1842 dev->vendor, dev->device, dev->hdr_type, dev->class);
1844 /* Device class may be changed after fixup */
1845 class = dev->class >> 8;
1847 if (dev->non_compliant_bars && !dev->mmio_always_on) {
1848 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1849 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1850 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1851 cmd &= ~PCI_COMMAND_IO;
1852 cmd &= ~PCI_COMMAND_MEMORY;
1853 pci_write_config_word(dev, PCI_COMMAND, cmd);
1857 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1859 switch (dev->hdr_type) { /* header type */
1860 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1861 if (class == PCI_CLASS_BRIDGE_PCI)
1864 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1866 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
1869 * Do the ugly legacy mode stuff here rather than broken chip
1870 * quirk code. Legacy mode ATA controllers have fixed
1871 * addresses. These are not always echoed in BAR0-3, and
1872 * BAR0-3 in a few cases contain junk!
1874 if (class == PCI_CLASS_STORAGE_IDE) {
1876 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1877 if ((progif & 1) == 0) {
1878 region.start = 0x1F0;
1880 res = &dev->resource[0];
1881 res->flags = LEGACY_IO_RESOURCE;
1882 pcibios_bus_to_resource(dev->bus, res, ®ion);
1883 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
1885 region.start = 0x3F6;
1887 res = &dev->resource[1];
1888 res->flags = LEGACY_IO_RESOURCE;
1889 pcibios_bus_to_resource(dev->bus, res, ®ion);
1890 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
1893 if ((progif & 4) == 0) {
1894 region.start = 0x170;
1896 res = &dev->resource[2];
1897 res->flags = LEGACY_IO_RESOURCE;
1898 pcibios_bus_to_resource(dev->bus, res, ®ion);
1899 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
1901 region.start = 0x376;
1903 res = &dev->resource[3];
1904 res->flags = LEGACY_IO_RESOURCE;
1905 pcibios_bus_to_resource(dev->bus, res, ®ion);
1906 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1912 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1914 * The PCI-to-PCI bridge spec requires that subtractive
1915 * decoding (i.e. transparent) bridge must have programming
1916 * interface code of 0x01.
1919 dev->transparent = ((dev->class & 0xff) == 1);
1920 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1921 pci_read_bridge_windows(dev);
1922 set_pcie_hotplug_bridge(dev);
1923 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1925 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1926 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1930 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1931 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1934 pci_read_bases(dev, 1, 0);
1935 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1936 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1939 default: /* unknown header */
1940 pci_err(dev, "unknown header type %02x, ignoring device\n",
1945 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1946 dev->class, dev->hdr_type);
1947 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1950 /* We found a fine healthy device, go go go... */
1954 static void pci_configure_mps(struct pci_dev *dev)
1956 struct pci_dev *bridge = pci_upstream_bridge(dev);
1957 int mps, mpss, p_mps, rc;
1959 if (!pci_is_pcie(dev))
1962 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
1967 * For Root Complex Integrated Endpoints, program the maximum
1968 * supported value unless limited by the PCIE_BUS_PEER2PEER case.
1970 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
1971 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1974 mps = 128 << dev->pcie_mpss;
1975 rc = pcie_set_mps(dev, mps);
1977 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1983 if (!bridge || !pci_is_pcie(bridge))
1986 mps = pcie_get_mps(dev);
1987 p_mps = pcie_get_mps(bridge);
1992 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1993 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1994 mps, pci_name(bridge), p_mps);
1999 * Fancier MPS configuration is done later by
2000 * pcie_bus_configure_settings()
2002 if (pcie_bus_config != PCIE_BUS_DEFAULT)
2005 mpss = 128 << dev->pcie_mpss;
2006 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
2007 pcie_set_mps(bridge, mpss);
2008 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
2009 mpss, p_mps, 128 << bridge->pcie_mpss);
2010 p_mps = pcie_get_mps(bridge);
2013 rc = pcie_set_mps(dev, p_mps);
2015 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2020 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
2024 int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
2026 struct pci_host_bridge *host;
2031 if (!pci_is_pcie(dev))
2034 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
2038 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
2041 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
2045 host = pci_find_host_bridge(dev->bus);
2050 * If some device in the hierarchy doesn't handle Extended Tags
2051 * correctly, make sure they're disabled.
2053 if (host->no_ext_tags) {
2054 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
2055 pci_info(dev, "disabling Extended Tags\n");
2056 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2057 PCI_EXP_DEVCTL_EXT_TAG);
2062 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
2063 pci_info(dev, "enabling Extended Tags\n");
2064 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
2065 PCI_EXP_DEVCTL_EXT_TAG);
2071 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
2072 * @dev: PCI device to query
2074 * Returns true if the device has enabled relaxed ordering attribute.
2076 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
2080 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
2082 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
2084 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
2086 static void pci_configure_relaxed_ordering(struct pci_dev *dev)
2088 struct pci_dev *root;
2090 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
2094 if (!pcie_relaxed_ordering_enabled(dev))
2098 * For now, we only deal with Relaxed Ordering issues with Root
2099 * Ports. Peer-to-Peer DMA is another can of worms.
2101 root = pcie_find_root_port(dev);
2105 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
2106 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2107 PCI_EXP_DEVCTL_RELAX_EN);
2108 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
2112 static void pci_configure_ltr(struct pci_dev *dev)
2114 #ifdef CONFIG_PCIEASPM
2115 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
2116 struct pci_dev *bridge;
2119 if (!pci_is_pcie(dev))
2122 /* Read L1 PM substate capabilities */
2123 dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
2125 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2126 if (!(cap & PCI_EXP_DEVCAP2_LTR))
2129 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
2130 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
2131 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2136 bridge = pci_upstream_bridge(dev);
2137 if (bridge && bridge->ltr_path)
2143 if (!host->native_ltr)
2147 * Software must not enable LTR in an Endpoint unless the Root
2148 * Complex and all intermediate Switches indicate support for LTR.
2149 * PCIe r4.0, sec 6.18.
2151 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
2152 ((bridge = pci_upstream_bridge(dev)) &&
2153 bridge->ltr_path)) {
2154 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2155 PCI_EXP_DEVCTL2_LTR_EN);
2161 static void pci_configure_eetlp_prefix(struct pci_dev *dev)
2163 #ifdef CONFIG_PCI_PASID
2164 struct pci_dev *bridge;
2168 if (!pci_is_pcie(dev))
2171 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2172 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
2175 pcie_type = pci_pcie_type(dev);
2176 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2177 pcie_type == PCI_EXP_TYPE_RC_END)
2178 dev->eetlp_prefix_path = 1;
2180 bridge = pci_upstream_bridge(dev);
2181 if (bridge && bridge->eetlp_prefix_path)
2182 dev->eetlp_prefix_path = 1;
2187 static void pci_configure_serr(struct pci_dev *dev)
2191 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
2194 * A bridge will not forward ERR_ messages coming from an
2195 * endpoint unless SERR# forwarding is enabled.
2197 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
2198 if (!(control & PCI_BRIDGE_CTL_SERR)) {
2199 control |= PCI_BRIDGE_CTL_SERR;
2200 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
2205 static void pci_configure_device(struct pci_dev *dev)
2207 pci_configure_mps(dev);
2208 pci_configure_extended_tags(dev, NULL);
2209 pci_configure_relaxed_ordering(dev);
2210 pci_configure_ltr(dev);
2211 pci_configure_eetlp_prefix(dev);
2212 pci_configure_serr(dev);
2214 pci_acpi_program_hp_params(dev);
2217 static void pci_release_capabilities(struct pci_dev *dev)
2221 pci_vpd_release(dev);
2222 pci_iov_release(dev);
2223 pci_free_cap_save_buffers(dev);
2227 * pci_release_dev - Free a PCI device structure when all users of it are
2229 * @dev: device that's been disconnected
2231 * Will be called only by the device core when all users of this PCI device are
2234 static void pci_release_dev(struct device *dev)
2236 struct pci_dev *pci_dev;
2238 pci_dev = to_pci_dev(dev);
2239 pci_release_capabilities(pci_dev);
2240 pci_release_of_node(pci_dev);
2241 pcibios_release_device(pci_dev);
2242 pci_bus_put(pci_dev->bus);
2243 kfree(pci_dev->driver_override);
2244 bitmap_free(pci_dev->dma_alias_mask);
2248 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
2250 struct pci_dev *dev;
2252 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2256 INIT_LIST_HEAD(&dev->bus_list);
2257 dev->dev.type = &pci_dev_type;
2258 dev->bus = pci_bus_get(bus);
2262 EXPORT_SYMBOL(pci_alloc_dev);
2264 static bool pci_bus_crs_vendor_id(u32 l)
2266 return (l & 0xffff) == 0x0001;
2269 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2274 if (!pci_bus_crs_vendor_id(*l))
2275 return true; /* not a CRS completion */
2278 return false; /* CRS, but caller doesn't want to wait */
2281 * We got the reserved Vendor ID that indicates a completion with
2282 * Configuration Request Retry Status (CRS). Retry until we get a
2283 * valid Vendor ID or we time out.
2285 while (pci_bus_crs_vendor_id(*l)) {
2286 if (delay > timeout) {
2287 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2288 pci_domain_nr(bus), bus->number,
2289 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2294 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2295 pci_domain_nr(bus), bus->number,
2296 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2301 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2306 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2307 pci_domain_nr(bus), bus->number,
2308 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2313 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2316 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2319 /* Some broken boards return 0 or ~0 if a slot is empty: */
2320 if (*l == 0xffffffff || *l == 0x00000000 ||
2321 *l == 0x0000ffff || *l == 0xffff0000)
2324 if (pci_bus_crs_vendor_id(*l))
2325 return pci_bus_wait_crs(bus, devfn, l, timeout);
2330 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2333 #ifdef CONFIG_PCI_QUIRKS
2334 struct pci_dev *bridge = bus->self;
2337 * Certain IDT switches have an issue where they improperly trigger
2338 * ACS Source Validation errors on completions for config reads.
2340 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
2341 bridge->device == 0x80b5)
2342 return pci_idt_bus_quirk(bus, devfn, l, timeout);
2345 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
2347 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2350 * Read the config data for a PCI device, sanity-check it,
2351 * and fill in the dev structure.
2353 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2355 struct pci_dev *dev;
2358 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2361 dev = pci_alloc_dev(bus);
2366 dev->vendor = l & 0xffff;
2367 dev->device = (l >> 16) & 0xffff;
2369 pci_set_of_node(dev);
2371 if (pci_setup_device(dev)) {
2372 pci_release_of_node(dev);
2373 pci_bus_put(dev->bus);
2381 void pcie_report_downtraining(struct pci_dev *dev)
2383 if (!pci_is_pcie(dev))
2386 /* Look from the device up to avoid downstream ports with no devices */
2387 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&
2388 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&
2389 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))
2392 /* Multi-function PCIe devices share the same link/status */
2393 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)
2396 /* Print link status only if the device is constrained by the fabric */
2397 __pcie_print_link_status(dev, false);
2400 static void pci_init_capabilities(struct pci_dev *dev)
2402 pci_ea_init(dev); /* Enhanced Allocation */
2404 /* Setup MSI caps & disable MSI/MSI-X interrupts */
2405 pci_msi_setup_pci_dev(dev);
2407 /* Buffers for saving PCIe and PCI-X capabilities */
2408 pci_allocate_cap_save_buffers(dev);
2410 pci_pm_init(dev); /* Power Management */
2411 pci_vpd_init(dev); /* Vital Product Data */
2412 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */
2413 pci_iov_init(dev); /* Single Root I/O Virtualization */
2414 pci_ats_init(dev); /* Address Translation Services */
2415 pci_pri_init(dev); /* Page Request Interface */
2416 pci_pasid_init(dev); /* Process Address Space ID */
2417 pci_acs_init(dev); /* Access Control Services */
2418 pci_ptm_init(dev); /* Precision Time Measurement */
2419 pci_aer_init(dev); /* Advanced Error Reporting */
2420 pci_dpc_init(dev); /* Downstream Port Containment */
2421 pci_rcec_init(dev); /* Root Complex Event Collector */
2423 pcie_report_downtraining(dev);
2425 if (pci_probe_reset_function(dev) == 0)
2430 * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2431 * devices. Firmware interfaces that can select the MSI domain on a
2432 * per-device basis should be called from here.
2434 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2436 struct irq_domain *d;
2439 * If a domain has been set through the pcibios_add_device()
2440 * callback, then this is the one (platform code knows best).
2442 d = dev_get_msi_domain(&dev->dev);
2447 * Let's see if we have a firmware interface able to provide
2450 d = pci_msi_get_device_domain(dev);
2457 static void pci_set_msi_domain(struct pci_dev *dev)
2459 struct irq_domain *d;
2462 * If the platform or firmware interfaces cannot supply a
2463 * device-specific MSI domain, then inherit the default domain
2464 * from the host bridge itself.
2466 d = pci_dev_msi_domain(dev);
2468 d = dev_get_msi_domain(&dev->bus->dev);
2470 dev_set_msi_domain(&dev->dev, d);
2473 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2477 pci_configure_device(dev);
2479 device_initialize(&dev->dev);
2480 dev->dev.release = pci_release_dev;
2482 set_dev_node(&dev->dev, pcibus_to_node(bus));
2483 dev->dev.dma_mask = &dev->dma_mask;
2484 dev->dev.dma_parms = &dev->dma_parms;
2485 dev->dev.coherent_dma_mask = 0xffffffffull;
2487 dma_set_max_seg_size(&dev->dev, 65536);
2488 dma_set_seg_boundary(&dev->dev, 0xffffffff);
2490 /* Fix up broken headers */
2491 pci_fixup_device(pci_fixup_header, dev);
2493 pci_reassigndev_resource_alignment(dev);
2495 dev->state_saved = false;
2497 pci_init_capabilities(dev);
2500 * Add the device to our list of discovered devices
2501 * and the bus list for fixup functions, etc.
2503 down_write(&pci_bus_sem);
2504 list_add_tail(&dev->bus_list, &bus->devices);
2505 up_write(&pci_bus_sem);
2507 ret = pcibios_add_device(dev);
2510 /* Set up MSI IRQ domain */
2511 pci_set_msi_domain(dev);
2513 /* Notifier could use PCI capabilities */
2514 dev->match_driver = false;
2515 ret = device_add(&dev->dev);
2519 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2521 struct pci_dev *dev;
2523 dev = pci_get_slot(bus, devfn);
2529 dev = pci_scan_device(bus, devfn);
2533 pci_device_add(dev, bus);
2537 EXPORT_SYMBOL(pci_scan_single_device);
2539 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
2545 if (pci_ari_enabled(bus)) {
2548 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2552 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2553 next_fn = PCI_ARI_CAP_NFN(cap);
2555 return 0; /* protect against malformed list */
2560 /* dev may be NULL for non-contiguous multifunction devices */
2561 if (!dev || dev->multifunction)
2562 return (fn + 1) % 8;
2567 static int only_one_child(struct pci_bus *bus)
2569 struct pci_dev *bridge = bus->self;
2572 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2573 * we scan for all possible devices, not just Device 0.
2575 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2579 * A PCIe Downstream Port normally leads to a Link with only Device
2580 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2581 * only for Device 0 in that situation.
2583 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))
2590 * pci_scan_slot - Scan a PCI slot on a bus for devices
2591 * @bus: PCI bus to scan
2592 * @devfn: slot number to scan (must have zero function)
2594 * Scan a PCI slot on the specified PCI bus for devices, adding
2595 * discovered devices to the @bus->devices list. New devices
2596 * will not have is_added set.
2598 * Returns the number of new devices found.
2600 int pci_scan_slot(struct pci_bus *bus, int devfn)
2602 unsigned fn, nr = 0;
2603 struct pci_dev *dev;
2605 if (only_one_child(bus) && (devfn > 0))
2606 return 0; /* Already scanned the entire slot */
2608 dev = pci_scan_single_device(bus, devfn);
2611 if (!pci_dev_is_added(dev))
2614 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
2615 dev = pci_scan_single_device(bus, devfn + fn);
2617 if (!pci_dev_is_added(dev))
2619 dev->multifunction = 1;
2623 /* Only one slot has PCIe device */
2624 if (bus->self && nr)
2625 pcie_aspm_init_link_state(bus->self);
2629 EXPORT_SYMBOL(pci_scan_slot);
2631 static int pcie_find_smpss(struct pci_dev *dev, void *data)
2635 if (!pci_is_pcie(dev))
2639 * We don't have a way to change MPS settings on devices that have
2640 * drivers attached. A hot-added device might support only the minimum
2641 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2642 * where devices may be hot-added, we limit the fabric MPS to 128 so
2643 * hot-added devices will work correctly.
2645 * However, if we hot-add a device to a slot directly below a Root
2646 * Port, it's impossible for there to be other existing devices below
2647 * the port. We don't limit the MPS in this case because we can
2648 * reconfigure MPS on both the Root Port and the hot-added device,
2649 * and there are no other devices involved.
2651 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2653 if (dev->is_hotplug_bridge &&
2654 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2657 if (*smpss > dev->pcie_mpss)
2658 *smpss = dev->pcie_mpss;
2663 static void pcie_write_mps(struct pci_dev *dev, int mps)
2667 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2668 mps = 128 << dev->pcie_mpss;
2670 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2674 * For "Performance", the assumption is made that
2675 * downstream communication will never be larger than
2676 * the MRRS. So, the MPS only needs to be configured
2677 * for the upstream communication. This being the case,
2678 * walk from the top down and set the MPS of the child
2679 * to that of the parent bus.
2681 * Configure the device MPS with the smaller of the
2682 * device MPSS or the bridge MPS (which is assumed to be
2683 * properly configured at this point to the largest
2684 * allowable MPS based on its parent bus).
2686 mps = min(mps, pcie_get_mps(dev->bus->self));
2689 rc = pcie_set_mps(dev, mps);
2691 pci_err(dev, "Failed attempting to set the MPS\n");
2694 static void pcie_write_mrrs(struct pci_dev *dev)
2699 * In the "safe" case, do not configure the MRRS. There appear to be
2700 * issues with setting MRRS to 0 on a number of devices.
2702 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2706 * For max performance, the MRRS must be set to the largest supported
2707 * value. However, it cannot be configured larger than the MPS the
2708 * device or the bus can support. This should already be properly
2709 * configured by a prior call to pcie_write_mps().
2711 mrrs = pcie_get_mps(dev);
2714 * MRRS is a R/W register. Invalid values can be written, but a
2715 * subsequent read will verify if the value is acceptable or not.
2716 * If the MRRS value provided is not acceptable (e.g., too large),
2717 * shrink the value until it is acceptable to the HW.
2719 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2720 rc = pcie_set_readrq(dev, mrrs);
2724 pci_warn(dev, "Failed attempting to set the MRRS\n");
2729 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2732 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2736 if (!pci_is_pcie(dev))
2739 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2740 pcie_bus_config == PCIE_BUS_DEFAULT)
2743 mps = 128 << *(u8 *)data;
2744 orig_mps = pcie_get_mps(dev);
2746 pcie_write_mps(dev, mps);
2747 pcie_write_mrrs(dev);
2749 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2750 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2751 orig_mps, pcie_get_readrq(dev));
2757 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2758 * parents then children fashion. If this changes, then this code will not
2761 void pcie_bus_configure_settings(struct pci_bus *bus)
2768 if (!pci_is_pcie(bus->self))
2772 * FIXME - Peer to peer DMA is possible, though the endpoint would need
2773 * to be aware of the MPS of the destination. To work around this,
2774 * simply force the MPS of the entire system to the smallest possible.
2776 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2779 if (pcie_bus_config == PCIE_BUS_SAFE) {
2780 smpss = bus->self->pcie_mpss;
2782 pcie_find_smpss(bus->self, &smpss);
2783 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2786 pcie_bus_configure_set(bus->self, &smpss);
2787 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2789 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2792 * Called after each bus is probed, but before its children are examined. This
2793 * is marked as __weak because multiple architectures define it.
2795 void __weak pcibios_fixup_bus(struct pci_bus *bus)
2797 /* nothing to do, expected to be removed in the future */
2801 * pci_scan_child_bus_extend() - Scan devices below a bus
2802 * @bus: Bus to scan for devices
2803 * @available_buses: Total number of buses available (%0 does not try to
2804 * extend beyond the minimal)
2806 * Scans devices below @bus including subordinate buses. Returns new
2807 * subordinate number including all the found devices. Passing
2808 * @available_buses causes the remaining bus space to be distributed
2809 * equally between hotplug-capable bridges to allow future extension of the
2812 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2813 unsigned int available_buses)
2815 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2816 unsigned int start = bus->busn_res.start;
2817 unsigned int devfn, fn, cmax, max = start;
2818 struct pci_dev *dev;
2821 dev_dbg(&bus->dev, "scanning bus\n");
2823 /* Go find them, Rover! */
2824 for (devfn = 0; devfn < 256; devfn += 8) {
2825 nr_devs = pci_scan_slot(bus, devfn);
2828 * The Jailhouse hypervisor may pass individual functions of a
2829 * multi-function device to a guest without passing function 0.
2830 * Look for them as well.
2832 if (jailhouse_paravirt() && nr_devs == 0) {
2833 for (fn = 1; fn < 8; fn++) {
2834 dev = pci_scan_single_device(bus, devfn + fn);
2836 dev->multifunction = 1;
2841 /* Reserve buses for SR-IOV capability */
2842 used_buses = pci_iov_bus_range(bus);
2846 * After performing arch-dependent fixup of the bus, look behind
2847 * all PCI-to-PCI bridges on this bus.
2849 if (!bus->is_added) {
2850 dev_dbg(&bus->dev, "fixups for bus\n");
2851 pcibios_fixup_bus(bus);
2856 * Calculate how many hotplug bridges and normal bridges there
2857 * are on this bus. We will distribute the additional available
2858 * buses between hotplug bridges.
2860 for_each_pci_bridge(dev, bus) {
2861 if (dev->is_hotplug_bridge)
2868 * Scan bridges that are already configured. We don't touch them
2869 * unless they are misconfigured (which will be done in the second
2872 for_each_pci_bridge(dev, bus) {
2874 max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
2877 * Reserve one bus for each bridge now to avoid extending
2878 * hotplug bridges too much during the second scan below.
2882 used_buses += cmax - max - 1;
2885 /* Scan bridges that need to be reconfigured */
2886 for_each_pci_bridge(dev, bus) {
2887 unsigned int buses = 0;
2889 if (!hotplug_bridges && normal_bridges == 1) {
2892 * There is only one bridge on the bus (upstream
2893 * port) so it gets all available buses which it
2894 * can then distribute to the possible hotplug
2897 buses = available_buses;
2898 } else if (dev->is_hotplug_bridge) {
2901 * Distribute the extra buses between hotplug
2904 buses = available_buses / hotplug_bridges;
2905 buses = min(buses, available_buses - used_buses + 1);
2909 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
2910 /* One bus is already accounted so don't add it again */
2912 used_buses += max - cmax - 1;
2916 * Make sure a hotplug bridge has at least the minimum requested
2917 * number of buses but allow it to grow up to the maximum available
2918 * bus number of there is room.
2920 if (bus->self && bus->self->is_hotplug_bridge) {
2921 used_buses = max_t(unsigned int, available_buses,
2922 pci_hotplug_bus_size - 1);
2923 if (max - start < used_buses) {
2924 max = start + used_buses;
2926 /* Do not allocate more buses than we have room left */
2927 if (max > bus->busn_res.end)
2928 max = bus->busn_res.end;
2930 dev_dbg(&bus->dev, "%pR extended by %#02x\n",
2931 &bus->busn_res, max - start);
2936 * We've scanned the bus and so we know all about what's on
2937 * the other side of any bridges that may be on this bus plus
2940 * Return how far we've got finding sub-buses.
2942 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2947 * pci_scan_child_bus() - Scan devices below a bus
2948 * @bus: Bus to scan for devices
2950 * Scans devices below @bus including subordinate buses. Returns new
2951 * subordinate number including all the found devices.
2953 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2955 return pci_scan_child_bus_extend(bus, 0);
2957 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2960 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
2961 * @bridge: Host bridge to set up
2963 * Default empty implementation. Replace with an architecture-specific setup
2964 * routine, if necessary.
2966 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2971 void __weak pcibios_add_bus(struct pci_bus *bus)
2975 void __weak pcibios_remove_bus(struct pci_bus *bus)
2979 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2980 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2983 struct pci_host_bridge *bridge;
2985 bridge = pci_alloc_host_bridge(0);
2989 bridge->dev.parent = parent;
2991 list_splice_init(resources, &bridge->windows);
2992 bridge->sysdata = sysdata;
2993 bridge->busnr = bus;
2996 error = pci_register_host_bridge(bridge);
3003 put_device(&bridge->dev);
3006 EXPORT_SYMBOL_GPL(pci_create_root_bus);
3008 int pci_host_probe(struct pci_host_bridge *bridge)
3010 struct pci_bus *bus, *child;
3013 ret = pci_scan_root_bus_bridge(bridge);
3015 dev_err(bridge->dev.parent, "Scanning root bridge failed");
3022 * We insert PCI resources into the iomem_resource and
3023 * ioport_resource trees in either pci_bus_claim_resources()
3024 * or pci_bus_assign_resources().
3026 if (pci_has_flag(PCI_PROBE_ONLY)) {
3027 pci_bus_claim_resources(bus);
3029 pci_bus_size_bridges(bus);
3030 pci_bus_assign_resources(bus);
3032 list_for_each_entry(child, &bus->children, node)
3033 pcie_bus_configure_settings(child);
3036 pci_bus_add_devices(bus);
3039 EXPORT_SYMBOL_GPL(pci_host_probe);
3041 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
3043 struct resource *res = &b->busn_res;
3044 struct resource *parent_res, *conflict;
3048 res->flags = IORESOURCE_BUS;
3050 if (!pci_is_root_bus(b))
3051 parent_res = &b->parent->busn_res;
3053 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
3054 res->flags |= IORESOURCE_PCI_FIXED;
3057 conflict = request_resource_conflict(parent_res, res);
3061 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
3062 res, pci_is_root_bus(b) ? "domain " : "",
3063 parent_res, conflict->name, conflict);
3065 return conflict == NULL;
3068 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
3070 struct resource *res = &b->busn_res;
3071 struct resource old_res = *res;
3072 resource_size_t size;
3075 if (res->start > bus_max)
3078 size = bus_max - res->start + 1;
3079 ret = adjust_resource(res, res->start, size);
3080 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",
3081 &old_res, ret ? "can not be" : "is", bus_max);
3083 if (!ret && !res->parent)
3084 pci_bus_insert_busn_res(b, res->start, res->end);
3089 void pci_bus_release_busn_res(struct pci_bus *b)
3091 struct resource *res = &b->busn_res;
3094 if (!res->flags || !res->parent)
3097 ret = release_resource(res);
3098 dev_info(&b->dev, "busn_res: %pR %s released\n",
3099 res, ret ? "can not be" : "is");
3102 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
3104 struct resource_entry *window;
3112 resource_list_for_each_entry(window, &bridge->windows)
3113 if (window->res->flags & IORESOURCE_BUS) {
3114 bridge->busnr = window->res->start;
3119 ret = pci_register_host_bridge(bridge);
3124 bus = bridge->busnr;
3128 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3130 pci_bus_insert_busn_res(b, bus, 255);
3133 max = pci_scan_child_bus(b);
3136 pci_bus_update_busn_res_end(b, max);
3140 EXPORT_SYMBOL(pci_scan_root_bus_bridge);
3142 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
3143 struct pci_ops *ops, void *sysdata, struct list_head *resources)
3145 struct resource_entry *window;
3150 resource_list_for_each_entry(window, resources)
3151 if (window->res->flags & IORESOURCE_BUS) {
3156 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
3162 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3164 pci_bus_insert_busn_res(b, bus, 255);
3167 max = pci_scan_child_bus(b);
3170 pci_bus_update_busn_res_end(b, max);
3174 EXPORT_SYMBOL(pci_scan_root_bus);
3176 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
3179 LIST_HEAD(resources);
3182 pci_add_resource(&resources, &ioport_resource);
3183 pci_add_resource(&resources, &iomem_resource);
3184 pci_add_resource(&resources, &busn_resource);
3185 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
3187 pci_scan_child_bus(b);
3189 pci_free_resource_list(&resources);
3193 EXPORT_SYMBOL(pci_scan_bus);
3196 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3197 * @bridge: PCI bridge for the bus to scan
3199 * Scan a PCI bus and child buses for new devices, add them,
3200 * and enable them, resizing bridge mmio/io resource if necessary
3201 * and possible. The caller must ensure the child devices are already
3202 * removed for resizing to occur.
3204 * Returns the max number of subordinate bus discovered.
3206 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
3209 struct pci_bus *bus = bridge->subordinate;
3211 max = pci_scan_child_bus(bus);
3213 pci_assign_unassigned_bridge_resources(bridge);
3215 pci_bus_add_devices(bus);
3221 * pci_rescan_bus - Scan a PCI bus for devices
3222 * @bus: PCI bus to scan
3224 * Scan a PCI bus and child buses for new devices, add them,
3227 * Returns the max number of subordinate bus discovered.
3229 unsigned int pci_rescan_bus(struct pci_bus *bus)
3233 max = pci_scan_child_bus(bus);
3234 pci_assign_unassigned_bus_resources(bus);
3235 pci_bus_add_devices(bus);
3239 EXPORT_SYMBOL_GPL(pci_rescan_bus);
3242 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3243 * routines should always be executed under this mutex.
3245 static DEFINE_MUTEX(pci_rescan_remove_lock);
3247 void pci_lock_rescan_remove(void)
3249 mutex_lock(&pci_rescan_remove_lock);
3251 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3253 void pci_unlock_rescan_remove(void)
3255 mutex_unlock(&pci_rescan_remove_lock);
3257 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3259 static int __init pci_sort_bf_cmp(const struct device *d_a,
3260 const struct device *d_b)
3262 const struct pci_dev *a = to_pci_dev(d_a);
3263 const struct pci_dev *b = to_pci_dev(d_b);
3265 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3266 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
3268 if (a->bus->number < b->bus->number) return -1;
3269 else if (a->bus->number > b->bus->number) return 1;
3271 if (a->devfn < b->devfn) return -1;
3272 else if (a->devfn > b->devfn) return 1;
3277 void __init pci_sort_breadthfirst(void)
3279 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
3282 int pci_hp_add_bridge(struct pci_dev *dev)
3284 struct pci_bus *parent = dev->bus;
3285 int busnr, start = parent->busn_res.start;
3286 unsigned int available_buses = 0;
3287 int end = parent->busn_res.end;
3289 for (busnr = start; busnr <= end; busnr++) {
3290 if (!pci_find_bus(pci_domain_nr(parent), busnr))
3293 if (busnr-- > end) {
3294 pci_err(dev, "No bus number available for hot-added bridge\n");
3298 /* Scan bridges that are already configured */
3299 busnr = pci_scan_bridge(parent, dev, busnr, 0);
3302 * Distribute the available bus numbers between hotplug-capable
3303 * bridges to make extending the chain later possible.
3305 available_buses = end - busnr;
3307 /* Scan bridges that need to be reconfigured */
3308 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3310 if (!dev->subordinate)
3315 EXPORT_SYMBOL_GPL(pci_hp_add_bridge);
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