1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file contains the routines for initializing the MMU
4 * on the 4xx series of chips.
7 * Derived from arch/ppc/mm/init.c:
8 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
10 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
11 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
12 * Copyright (C) 1996 Paul Mackerras
14 * Derived from "arch/i386/mm/init.c"
15 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
18 #include <linux/signal.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
21 #include <linux/errno.h>
22 #include <linux/string.h>
23 #include <linux/types.h>
24 #include <linux/ptrace.h>
25 #include <linux/mman.h>
27 #include <linux/swap.h>
28 #include <linux/stddef.h>
29 #include <linux/vmalloc.h>
30 #include <linux/init.h>
31 #include <linux/delay.h>
32 #include <linux/highmem.h>
33 #include <linux/memblock.h>
36 #include <asm/mmu_context.h>
38 #include <linux/uaccess.h>
40 #include <asm/bootx.h>
41 #include <asm/machdep.h>
42 #include <asm/setup.h>
44 #include <mm/mmu_decl.h>
47 * MMU_init_hw does the chip-specific initialization of the MMU hardware.
49 void __init MMU_init_hw(void)
52 * The Zone Protection Register (ZPR) defines how protection will
53 * be applied to every page which is a member of a given zone. At
54 * present, we utilize only two of the 4xx's zones.
55 * The zone index bits (of ZSEL) in the PTE are used for software
56 * indicators, except the LSB. For user access, zone 1 is used,
57 * for kernel access, zone 0 is used. We set all but zone 1
58 * to zero, allowing only kernel access as indicated in the PTE.
59 * For zone 1, we set a 01 binary (a value of 10 will not work)
60 * to allow user access as indicated in the PTE. This also allows
61 * kernel access as indicated in the PTE.
64 mtspr(SPRN_ZPR, 0x10000000);
66 flush_instruction_cache();
69 * Set up the real-mode cache parameters for the exception vector
70 * handlers (which are run in real-mode).
73 mtspr(SPRN_DCWR, 0x00000000); /* All caching is write-back */
76 * Cache instruction and data space where the exception
77 * vectors and the kernel live in real-mode.
80 mtspr(SPRN_DCCR, 0xFFFF0000); /* 2GByte of data space at 0x0. */
81 mtspr(SPRN_ICCR, 0xFFFF0000); /* 2GByte of instr. space at 0x0. */
84 #define LARGE_PAGE_SIZE_16M (1<<24)
85 #define LARGE_PAGE_SIZE_4M (1<<22)
87 unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
89 unsigned long v, s, mapped;
96 if (IS_ENABLED(CONFIG_KFENCE))
99 if (debug_pagealloc_enabled())
102 if (strict_kernel_rwx_enabled())
105 while (s >= LARGE_PAGE_SIZE_16M) {
107 unsigned long val = p | _PMD_SIZE_16M | _PAGE_EXEC | _PAGE_RW;
110 *pmdp++ = __pmd(val);
111 *pmdp++ = __pmd(val);
112 *pmdp++ = __pmd(val);
113 *pmdp++ = __pmd(val);
115 v += LARGE_PAGE_SIZE_16M;
116 p += LARGE_PAGE_SIZE_16M;
117 s -= LARGE_PAGE_SIZE_16M;
120 while (s >= LARGE_PAGE_SIZE_4M) {
122 unsigned long val = p | _PMD_SIZE_4M | _PAGE_EXEC | _PAGE_RW;
127 v += LARGE_PAGE_SIZE_4M;
128 p += LARGE_PAGE_SIZE_4M;
129 s -= LARGE_PAGE_SIZE_4M;
132 mapped = total_lowmem - s;
134 /* If the size of RAM is not an exact power of two, we may not
135 * have covered RAM in its entirety with 16 and 4 MiB
136 * pages. Consequently, restrict the top end of RAM currently
137 * allocable so that calls to the MEMBLOCK to allocate PTEs for "tail"
138 * coverage with normal-sized pages (or other reasons) do not
139 * attempt to allocate outside the allowed range.
141 memblock_set_current_limit(mapped);
146 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
147 phys_addr_t first_memblock_size)
149 /* We don't currently support the first MEMBLOCK not mapping 0
150 * physical on those processors
152 BUG_ON(first_memblock_base != 0);
154 /* 40x can only access 16MB at the moment (see head_40x.S) */
155 memblock_set_current_limit(min_t(u64, first_memblock_size, 0x00800000));