3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Derived from "arch/m68k/kernel/ptrace.c"
6 * Copyright (C) 1994 by Hamish Macdonald
7 * Taken from linux/kernel/ptrace.c and modified for M680x0.
8 * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
10 * Modified by Cort Dougan (cort@hq.fsmlabs.com)
11 * and Paul Mackerras (paulus@samba.org).
13 * This file is subject to the terms and conditions of the GNU General
14 * Public License. See the file README.legal in the main directory of
15 * this archive for more details.
18 #include <linux/kernel.h>
19 #include <linux/sched.h>
21 #include <linux/smp.h>
22 #include <linux/errno.h>
23 #include <linux/ptrace.h>
24 #include <linux/regset.h>
25 #include <linux/tracehook.h>
26 #include <linux/elf.h>
27 #include <linux/user.h>
28 #include <linux/security.h>
29 #include <linux/signal.h>
30 #include <linux/seccomp.h>
31 #include <linux/audit.h>
32 #include <trace/syscall.h>
33 #include <linux/hw_breakpoint.h>
34 #include <linux/perf_event.h>
35 #include <linux/context_tracking.h>
37 #include <linux/uaccess.h>
39 #include <asm/pgtable.h>
40 #include <asm/switch_to.h>
42 #include <asm/asm-prototypes.h>
44 #define CREATE_TRACE_POINTS
45 #include <trace/events/syscalls.h>
48 * The parameter save area on the stack is used to store arguments being passed
49 * to callee function and is located at fixed offset from stack pointer.
52 #define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */
53 #else /* CONFIG_PPC32 */
54 #define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */
57 struct pt_regs_offset {
62 #define STR(s) #s /* convert to string */
63 #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
64 #define GPR_OFFSET_NAME(num) \
65 {.name = STR(r##num), .offset = offsetof(struct pt_regs, gpr[num])}, \
66 {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])}
67 #define REG_OFFSET_END {.name = NULL, .offset = 0}
69 #define TVSO(f) (offsetof(struct thread_vr_state, f))
70 #define TFSO(f) (offsetof(struct thread_fp_state, f))
71 #define TSO(f) (offsetof(struct thread_struct, f))
73 static const struct pt_regs_offset regoffset_table[] = {
106 REG_OFFSET_NAME(nip),
107 REG_OFFSET_NAME(msr),
108 REG_OFFSET_NAME(ctr),
109 REG_OFFSET_NAME(link),
110 REG_OFFSET_NAME(xer),
111 REG_OFFSET_NAME(ccr),
113 REG_OFFSET_NAME(softe),
117 REG_OFFSET_NAME(trap),
118 REG_OFFSET_NAME(dar),
119 REG_OFFSET_NAME(dsisr),
123 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
124 static void flush_tmregs_to_thread(struct task_struct *tsk)
127 * If task is not current, it will have been flushed already to
128 * it's thread_struct during __switch_to().
130 * A reclaim flushes ALL the state or if not in TM save TM SPRs
131 * in the appropriate thread structures from live.
134 if ((!cpu_has_feature(CPU_FTR_TM)) || (tsk != current))
137 if (MSR_TM_SUSPENDED(mfmsr())) {
138 tm_reclaim_current(TM_CAUSE_SIGNAL);
141 tm_save_sprs(&(tsk->thread));
145 static inline void flush_tmregs_to_thread(struct task_struct *tsk) { }
149 * regs_query_register_offset() - query register offset from its name
150 * @name: the name of a register
152 * regs_query_register_offset() returns the offset of a register in struct
153 * pt_regs from its name. If the name is invalid, this returns -EINVAL;
155 int regs_query_register_offset(const char *name)
157 const struct pt_regs_offset *roff;
158 for (roff = regoffset_table; roff->name != NULL; roff++)
159 if (!strcmp(roff->name, name))
165 * regs_query_register_name() - query register name from its offset
166 * @offset: the offset of a register in struct pt_regs.
168 * regs_query_register_name() returns the name of a register from its
169 * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
171 const char *regs_query_register_name(unsigned int offset)
173 const struct pt_regs_offset *roff;
174 for (roff = regoffset_table; roff->name != NULL; roff++)
175 if (roff->offset == offset)
181 * does not yet catch signals sent when the child dies.
182 * in exit.c or in signal.c.
186 * Set of msr bits that gdb can change on behalf of a process.
188 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
189 #define MSR_DEBUGCHANGE 0
191 #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE)
195 * Max register writeable via put_reg
198 #define PT_MAX_PUT_REG PT_MQ
200 #define PT_MAX_PUT_REG PT_CCR
203 static unsigned long get_user_msr(struct task_struct *task)
205 return task->thread.regs->msr | task->thread.fpexc_mode;
208 static int set_user_msr(struct task_struct *task, unsigned long msr)
210 task->thread.regs->msr &= ~MSR_DEBUGCHANGE;
211 task->thread.regs->msr |= msr & MSR_DEBUGCHANGE;
215 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
216 static unsigned long get_user_ckpt_msr(struct task_struct *task)
218 return task->thread.ckpt_regs.msr | task->thread.fpexc_mode;
221 static int set_user_ckpt_msr(struct task_struct *task, unsigned long msr)
223 task->thread.ckpt_regs.msr &= ~MSR_DEBUGCHANGE;
224 task->thread.ckpt_regs.msr |= msr & MSR_DEBUGCHANGE;
228 static int set_user_ckpt_trap(struct task_struct *task, unsigned long trap)
230 task->thread.ckpt_regs.trap = trap & 0xfff0;
236 static int get_user_dscr(struct task_struct *task, unsigned long *data)
238 *data = task->thread.dscr;
242 static int set_user_dscr(struct task_struct *task, unsigned long dscr)
244 task->thread.dscr = dscr;
245 task->thread.dscr_inherit = 1;
249 static int get_user_dscr(struct task_struct *task, unsigned long *data)
254 static int set_user_dscr(struct task_struct *task, unsigned long dscr)
261 * We prevent mucking around with the reserved area of trap
262 * which are used internally by the kernel.
264 static int set_user_trap(struct task_struct *task, unsigned long trap)
266 task->thread.regs->trap = trap & 0xfff0;
271 * Get contents of register REGNO in task TASK.
273 int ptrace_get_reg(struct task_struct *task, int regno, unsigned long *data)
275 if ((task->thread.regs == NULL) || !data)
278 if (regno == PT_MSR) {
279 *data = get_user_msr(task);
283 if (regno == PT_DSCR)
284 return get_user_dscr(task, data);
286 if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) {
287 *data = ((unsigned long *)task->thread.regs)[regno];
295 * Write contents of register REGNO in task TASK.
297 int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data)
299 if (task->thread.regs == NULL)
303 return set_user_msr(task, data);
304 if (regno == PT_TRAP)
305 return set_user_trap(task, data);
306 if (regno == PT_DSCR)
307 return set_user_dscr(task, data);
309 if (regno <= PT_MAX_PUT_REG) {
310 ((unsigned long *)task->thread.regs)[regno] = data;
316 static int gpr_get(struct task_struct *target, const struct user_regset *regset,
317 unsigned int pos, unsigned int count,
318 void *kbuf, void __user *ubuf)
322 if (target->thread.regs == NULL)
325 if (!FULL_REGS(target->thread.regs)) {
326 /* We have a partial register set. Fill 14-31 with bogus values */
327 for (i = 14; i < 32; i++)
328 target->thread.regs->gpr[i] = NV_REG_POISON;
331 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
333 0, offsetof(struct pt_regs, msr));
335 unsigned long msr = get_user_msr(target);
336 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr,
337 offsetof(struct pt_regs, msr),
338 offsetof(struct pt_regs, msr) +
342 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
343 offsetof(struct pt_regs, msr) + sizeof(long));
346 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
347 &target->thread.regs->orig_gpr3,
348 offsetof(struct pt_regs, orig_gpr3),
349 sizeof(struct pt_regs));
351 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
352 sizeof(struct pt_regs), -1);
357 static int gpr_set(struct task_struct *target, const struct user_regset *regset,
358 unsigned int pos, unsigned int count,
359 const void *kbuf, const void __user *ubuf)
364 if (target->thread.regs == NULL)
367 CHECK_FULL_REGS(target->thread.regs);
369 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
371 0, PT_MSR * sizeof(reg));
373 if (!ret && count > 0) {
374 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®,
375 PT_MSR * sizeof(reg),
376 (PT_MSR + 1) * sizeof(reg));
378 ret = set_user_msr(target, reg);
381 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
382 offsetof(struct pt_regs, msr) + sizeof(long));
385 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
386 &target->thread.regs->orig_gpr3,
387 PT_ORIG_R3 * sizeof(reg),
388 (PT_MAX_PUT_REG + 1) * sizeof(reg));
390 if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret)
391 ret = user_regset_copyin_ignore(
392 &pos, &count, &kbuf, &ubuf,
393 (PT_MAX_PUT_REG + 1) * sizeof(reg),
394 PT_TRAP * sizeof(reg));
396 if (!ret && count > 0) {
397 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®,
398 PT_TRAP * sizeof(reg),
399 (PT_TRAP + 1) * sizeof(reg));
401 ret = set_user_trap(target, reg);
405 ret = user_regset_copyin_ignore(
406 &pos, &count, &kbuf, &ubuf,
407 (PT_TRAP + 1) * sizeof(reg), -1);
413 * Regardless of transactions, 'fp_state' holds the current running
414 * value of all FPR registers and 'ckfp_state' holds the last checkpointed
415 * value of all FPR registers for the current transaction.
417 * Userspace interface buffer layout:
424 static int fpr_get(struct task_struct *target, const struct user_regset *regset,
425 unsigned int pos, unsigned int count,
426 void *kbuf, void __user *ubuf)
432 flush_fp_to_thread(target);
434 /* copy to local buffer then write that out */
435 for (i = 0; i < 32 ; i++)
436 buf[i] = target->thread.TS_FPR(i);
437 buf[32] = target->thread.fp_state.fpscr;
438 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
440 BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) !=
441 offsetof(struct thread_fp_state, fpr[32]));
443 flush_fp_to_thread(target);
445 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
446 &target->thread.fp_state, 0, -1);
451 * Regardless of transactions, 'fp_state' holds the current running
452 * value of all FPR registers and 'ckfp_state' holds the last checkpointed
453 * value of all FPR registers for the current transaction.
455 * Userspace interface buffer layout:
463 static int fpr_set(struct task_struct *target, const struct user_regset *regset,
464 unsigned int pos, unsigned int count,
465 const void *kbuf, const void __user *ubuf)
471 flush_fp_to_thread(target);
473 for (i = 0; i < 32 ; i++)
474 buf[i] = target->thread.TS_FPR(i);
475 buf[32] = target->thread.fp_state.fpscr;
477 /* copy to local buffer then write that out */
478 i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
482 for (i = 0; i < 32 ; i++)
483 target->thread.TS_FPR(i) = buf[i];
484 target->thread.fp_state.fpscr = buf[32];
487 BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) !=
488 offsetof(struct thread_fp_state, fpr[32]));
490 flush_fp_to_thread(target);
492 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
493 &target->thread.fp_state, 0, -1);
497 #ifdef CONFIG_ALTIVEC
499 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
500 * The transfer totals 34 quadword. Quadwords 0-31 contain the
501 * corresponding vector registers. Quadword 32 contains the vscr as the
502 * last word (offset 12) within that quadword. Quadword 33 contains the
503 * vrsave as the first word (offset 0) within the quadword.
505 * This definition of the VMX state is compatible with the current PPC32
506 * ptrace interface. This allows signal handling and ptrace to use the
507 * same structures. This also simplifies the implementation of a bi-arch
508 * (combined (32- and 64-bit) gdb.
511 static int vr_active(struct task_struct *target,
512 const struct user_regset *regset)
514 flush_altivec_to_thread(target);
515 return target->thread.used_vr ? regset->n : 0;
519 * Regardless of transactions, 'vr_state' holds the current running
520 * value of all the VMX registers and 'ckvr_state' holds the last
521 * checkpointed value of all the VMX registers for the current
522 * transaction to fall back on in case it aborts.
524 * Userspace interface buffer layout:
532 static int vr_get(struct task_struct *target, const struct user_regset *regset,
533 unsigned int pos, unsigned int count,
534 void *kbuf, void __user *ubuf)
538 flush_altivec_to_thread(target);
540 BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) !=
541 offsetof(struct thread_vr_state, vr[32]));
543 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
544 &target->thread.vr_state, 0,
545 33 * sizeof(vector128));
548 * Copy out only the low-order word of vrsave.
555 memset(&vrsave, 0, sizeof(vrsave));
557 vrsave.word = target->thread.vrsave;
559 start = 33 * sizeof(vector128);
560 end = start + sizeof(vrsave);
561 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
569 * Regardless of transactions, 'vr_state' holds the current running
570 * value of all the VMX registers and 'ckvr_state' holds the last
571 * checkpointed value of all the VMX registers for the current
572 * transaction to fall back on in case it aborts.
574 * Userspace interface buffer layout:
582 static int vr_set(struct task_struct *target, const struct user_regset *regset,
583 unsigned int pos, unsigned int count,
584 const void *kbuf, const void __user *ubuf)
588 flush_altivec_to_thread(target);
590 BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) !=
591 offsetof(struct thread_vr_state, vr[32]));
593 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
594 &target->thread.vr_state, 0,
595 33 * sizeof(vector128));
596 if (!ret && count > 0) {
598 * We use only the first word of vrsave.
605 memset(&vrsave, 0, sizeof(vrsave));
607 vrsave.word = target->thread.vrsave;
609 start = 33 * sizeof(vector128);
610 end = start + sizeof(vrsave);
611 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
614 target->thread.vrsave = vrsave.word;
619 #endif /* CONFIG_ALTIVEC */
623 * Currently to set and and get all the vsx state, you need to call
624 * the fp and VMX calls as well. This only get/sets the lower 32
625 * 128bit VSX registers.
628 static int vsr_active(struct task_struct *target,
629 const struct user_regset *regset)
631 flush_vsx_to_thread(target);
632 return target->thread.used_vsr ? regset->n : 0;
636 * Regardless of transactions, 'fp_state' holds the current running
637 * value of all FPR registers and 'ckfp_state' holds the last
638 * checkpointed value of all FPR registers for the current
641 * Userspace interface buffer layout:
647 static int vsr_get(struct task_struct *target, const struct user_regset *regset,
648 unsigned int pos, unsigned int count,
649 void *kbuf, void __user *ubuf)
654 flush_tmregs_to_thread(target);
655 flush_fp_to_thread(target);
656 flush_altivec_to_thread(target);
657 flush_vsx_to_thread(target);
659 for (i = 0; i < 32 ; i++)
660 buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET];
662 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
663 buf, 0, 32 * sizeof(double));
669 * Regardless of transactions, 'fp_state' holds the current running
670 * value of all FPR registers and 'ckfp_state' holds the last
671 * checkpointed value of all FPR registers for the current
674 * Userspace interface buffer layout:
680 static int vsr_set(struct task_struct *target, const struct user_regset *regset,
681 unsigned int pos, unsigned int count,
682 const void *kbuf, const void __user *ubuf)
687 flush_tmregs_to_thread(target);
688 flush_fp_to_thread(target);
689 flush_altivec_to_thread(target);
690 flush_vsx_to_thread(target);
692 for (i = 0; i < 32 ; i++)
693 buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET];
695 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
696 buf, 0, 32 * sizeof(double));
698 for (i = 0; i < 32 ; i++)
699 target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i];
703 #endif /* CONFIG_VSX */
708 * For get_evrregs/set_evrregs functions 'data' has the following layout:
717 static int evr_active(struct task_struct *target,
718 const struct user_regset *regset)
720 flush_spe_to_thread(target);
721 return target->thread.used_spe ? regset->n : 0;
724 static int evr_get(struct task_struct *target, const struct user_regset *regset,
725 unsigned int pos, unsigned int count,
726 void *kbuf, void __user *ubuf)
730 flush_spe_to_thread(target);
732 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
734 0, sizeof(target->thread.evr));
736 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
737 offsetof(struct thread_struct, spefscr));
740 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
742 sizeof(target->thread.evr), -1);
747 static int evr_set(struct task_struct *target, const struct user_regset *regset,
748 unsigned int pos, unsigned int count,
749 const void *kbuf, const void __user *ubuf)
753 flush_spe_to_thread(target);
755 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
757 0, sizeof(target->thread.evr));
759 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
760 offsetof(struct thread_struct, spefscr));
763 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
765 sizeof(target->thread.evr), -1);
769 #endif /* CONFIG_SPE */
771 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
773 * tm_cgpr_active - get active number of registers in CGPR
774 * @target: The target task.
775 * @regset: The user regset structure.
777 * This function checks for the active number of available
778 * regisers in transaction checkpointed GPR category.
780 static int tm_cgpr_active(struct task_struct *target,
781 const struct user_regset *regset)
783 if (!cpu_has_feature(CPU_FTR_TM))
786 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
793 * tm_cgpr_get - get CGPR registers
794 * @target: The target task.
795 * @regset: The user regset structure.
796 * @pos: The buffer position.
797 * @count: Number of bytes to copy.
798 * @kbuf: Kernel buffer to copy from.
799 * @ubuf: User buffer to copy into.
801 * This function gets transaction checkpointed GPR registers.
803 * When the transaction is active, 'ckpt_regs' holds all the checkpointed
804 * GPR register values for the current transaction to fall back on if it
805 * aborts in between. This function gets those checkpointed GPR registers.
806 * The userspace interface buffer layout is as follows.
809 * struct pt_regs ckpt_regs;
812 static int tm_cgpr_get(struct task_struct *target,
813 const struct user_regset *regset,
814 unsigned int pos, unsigned int count,
815 void *kbuf, void __user *ubuf)
819 if (!cpu_has_feature(CPU_FTR_TM))
822 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
825 flush_tmregs_to_thread(target);
826 flush_fp_to_thread(target);
827 flush_altivec_to_thread(target);
829 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
830 &target->thread.ckpt_regs,
831 0, offsetof(struct pt_regs, msr));
833 unsigned long msr = get_user_ckpt_msr(target);
835 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr,
836 offsetof(struct pt_regs, msr),
837 offsetof(struct pt_regs, msr) +
841 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
842 offsetof(struct pt_regs, msr) + sizeof(long));
845 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
846 &target->thread.ckpt_regs.orig_gpr3,
847 offsetof(struct pt_regs, orig_gpr3),
848 sizeof(struct pt_regs));
850 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
851 sizeof(struct pt_regs), -1);
857 * tm_cgpr_set - set the CGPR registers
858 * @target: The target task.
859 * @regset: The user regset structure.
860 * @pos: The buffer position.
861 * @count: Number of bytes to copy.
862 * @kbuf: Kernel buffer to copy into.
863 * @ubuf: User buffer to copy from.
865 * This function sets in transaction checkpointed GPR registers.
867 * When the transaction is active, 'ckpt_regs' holds the checkpointed
868 * GPR register values for the current transaction to fall back on if it
869 * aborts in between. This function sets those checkpointed GPR registers.
870 * The userspace interface buffer layout is as follows.
873 * struct pt_regs ckpt_regs;
876 static int tm_cgpr_set(struct task_struct *target,
877 const struct user_regset *regset,
878 unsigned int pos, unsigned int count,
879 const void *kbuf, const void __user *ubuf)
884 if (!cpu_has_feature(CPU_FTR_TM))
887 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
890 flush_tmregs_to_thread(target);
891 flush_fp_to_thread(target);
892 flush_altivec_to_thread(target);
894 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
895 &target->thread.ckpt_regs,
896 0, PT_MSR * sizeof(reg));
898 if (!ret && count > 0) {
899 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®,
900 PT_MSR * sizeof(reg),
901 (PT_MSR + 1) * sizeof(reg));
903 ret = set_user_ckpt_msr(target, reg);
906 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
907 offsetof(struct pt_regs, msr) + sizeof(long));
910 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
911 &target->thread.ckpt_regs.orig_gpr3,
912 PT_ORIG_R3 * sizeof(reg),
913 (PT_MAX_PUT_REG + 1) * sizeof(reg));
915 if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret)
916 ret = user_regset_copyin_ignore(
917 &pos, &count, &kbuf, &ubuf,
918 (PT_MAX_PUT_REG + 1) * sizeof(reg),
919 PT_TRAP * sizeof(reg));
921 if (!ret && count > 0) {
922 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®,
923 PT_TRAP * sizeof(reg),
924 (PT_TRAP + 1) * sizeof(reg));
926 ret = set_user_ckpt_trap(target, reg);
930 ret = user_regset_copyin_ignore(
931 &pos, &count, &kbuf, &ubuf,
932 (PT_TRAP + 1) * sizeof(reg), -1);
938 * tm_cfpr_active - get active number of registers in CFPR
939 * @target: The target task.
940 * @regset: The user regset structure.
942 * This function checks for the active number of available
943 * regisers in transaction checkpointed FPR category.
945 static int tm_cfpr_active(struct task_struct *target,
946 const struct user_regset *regset)
948 if (!cpu_has_feature(CPU_FTR_TM))
951 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
958 * tm_cfpr_get - get CFPR registers
959 * @target: The target task.
960 * @regset: The user regset structure.
961 * @pos: The buffer position.
962 * @count: Number of bytes to copy.
963 * @kbuf: Kernel buffer to copy from.
964 * @ubuf: User buffer to copy into.
966 * This function gets in transaction checkpointed FPR registers.
968 * When the transaction is active 'ckfp_state' holds the checkpointed
969 * values for the current transaction to fall back on if it aborts
970 * in between. This function gets those checkpointed FPR registers.
971 * The userspace interface buffer layout is as follows.
978 static int tm_cfpr_get(struct task_struct *target,
979 const struct user_regset *regset,
980 unsigned int pos, unsigned int count,
981 void *kbuf, void __user *ubuf)
986 if (!cpu_has_feature(CPU_FTR_TM))
989 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
992 flush_tmregs_to_thread(target);
993 flush_fp_to_thread(target);
994 flush_altivec_to_thread(target);
996 /* copy to local buffer then write that out */
997 for (i = 0; i < 32 ; i++)
998 buf[i] = target->thread.TS_CKFPR(i);
999 buf[32] = target->thread.ckfp_state.fpscr;
1000 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
1004 * tm_cfpr_set - set CFPR registers
1005 * @target: The target task.
1006 * @regset: The user regset structure.
1007 * @pos: The buffer position.
1008 * @count: Number of bytes to copy.
1009 * @kbuf: Kernel buffer to copy into.
1010 * @ubuf: User buffer to copy from.
1012 * This function sets in transaction checkpointed FPR registers.
1014 * When the transaction is active 'ckfp_state' holds the checkpointed
1015 * FPR register values for the current transaction to fall back on
1016 * if it aborts in between. This function sets these checkpointed
1017 * FPR registers. The userspace interface buffer layout is as follows.
1024 static int tm_cfpr_set(struct task_struct *target,
1025 const struct user_regset *regset,
1026 unsigned int pos, unsigned int count,
1027 const void *kbuf, const void __user *ubuf)
1032 if (!cpu_has_feature(CPU_FTR_TM))
1035 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1038 flush_tmregs_to_thread(target);
1039 flush_fp_to_thread(target);
1040 flush_altivec_to_thread(target);
1042 for (i = 0; i < 32; i++)
1043 buf[i] = target->thread.TS_CKFPR(i);
1044 buf[32] = target->thread.ckfp_state.fpscr;
1046 /* copy to local buffer then write that out */
1047 i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
1050 for (i = 0; i < 32 ; i++)
1051 target->thread.TS_CKFPR(i) = buf[i];
1052 target->thread.ckfp_state.fpscr = buf[32];
1057 * tm_cvmx_active - get active number of registers in CVMX
1058 * @target: The target task.
1059 * @regset: The user regset structure.
1061 * This function checks for the active number of available
1062 * regisers in checkpointed VMX category.
1064 static int tm_cvmx_active(struct task_struct *target,
1065 const struct user_regset *regset)
1067 if (!cpu_has_feature(CPU_FTR_TM))
1070 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1077 * tm_cvmx_get - get CMVX registers
1078 * @target: The target task.
1079 * @regset: The user regset structure.
1080 * @pos: The buffer position.
1081 * @count: Number of bytes to copy.
1082 * @kbuf: Kernel buffer to copy from.
1083 * @ubuf: User buffer to copy into.
1085 * This function gets in transaction checkpointed VMX registers.
1087 * When the transaction is active 'ckvr_state' and 'ckvrsave' hold
1088 * the checkpointed values for the current transaction to fall
1089 * back on if it aborts in between. The userspace interface buffer
1090 * layout is as follows.
1098 static int tm_cvmx_get(struct task_struct *target,
1099 const struct user_regset *regset,
1100 unsigned int pos, unsigned int count,
1101 void *kbuf, void __user *ubuf)
1105 BUILD_BUG_ON(TVSO(vscr) != TVSO(vr[32]));
1107 if (!cpu_has_feature(CPU_FTR_TM))
1110 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1113 /* Flush the state */
1114 flush_tmregs_to_thread(target);
1115 flush_fp_to_thread(target);
1116 flush_altivec_to_thread(target);
1118 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1119 &target->thread.ckvr_state, 0,
1120 33 * sizeof(vector128));
1123 * Copy out only the low-order word of vrsave.
1129 memset(&vrsave, 0, sizeof(vrsave));
1130 vrsave.word = target->thread.ckvrsave;
1131 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
1132 33 * sizeof(vector128), -1);
1139 * tm_cvmx_set - set CMVX registers
1140 * @target: The target task.
1141 * @regset: The user regset structure.
1142 * @pos: The buffer position.
1143 * @count: Number of bytes to copy.
1144 * @kbuf: Kernel buffer to copy into.
1145 * @ubuf: User buffer to copy from.
1147 * This function sets in transaction checkpointed VMX registers.
1149 * When the transaction is active 'ckvr_state' and 'ckvrsave' hold
1150 * the checkpointed values for the current transaction to fall
1151 * back on if it aborts in between. The userspace interface buffer
1152 * layout is as follows.
1160 static int tm_cvmx_set(struct task_struct *target,
1161 const struct user_regset *regset,
1162 unsigned int pos, unsigned int count,
1163 const void *kbuf, const void __user *ubuf)
1167 BUILD_BUG_ON(TVSO(vscr) != TVSO(vr[32]));
1169 if (!cpu_has_feature(CPU_FTR_TM))
1172 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1175 flush_tmregs_to_thread(target);
1176 flush_fp_to_thread(target);
1177 flush_altivec_to_thread(target);
1179 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1180 &target->thread.ckvr_state, 0,
1181 33 * sizeof(vector128));
1182 if (!ret && count > 0) {
1184 * We use only the low-order word of vrsave.
1190 memset(&vrsave, 0, sizeof(vrsave));
1191 vrsave.word = target->thread.ckvrsave;
1192 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
1193 33 * sizeof(vector128), -1);
1195 target->thread.ckvrsave = vrsave.word;
1202 * tm_cvsx_active - get active number of registers in CVSX
1203 * @target: The target task.
1204 * @regset: The user regset structure.
1206 * This function checks for the active number of available
1207 * regisers in transaction checkpointed VSX category.
1209 static int tm_cvsx_active(struct task_struct *target,
1210 const struct user_regset *regset)
1212 if (!cpu_has_feature(CPU_FTR_TM))
1215 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1218 flush_vsx_to_thread(target);
1219 return target->thread.used_vsr ? regset->n : 0;
1223 * tm_cvsx_get - get CVSX registers
1224 * @target: The target task.
1225 * @regset: The user regset structure.
1226 * @pos: The buffer position.
1227 * @count: Number of bytes to copy.
1228 * @kbuf: Kernel buffer to copy from.
1229 * @ubuf: User buffer to copy into.
1231 * This function gets in transaction checkpointed VSX registers.
1233 * When the transaction is active 'ckfp_state' holds the checkpointed
1234 * values for the current transaction to fall back on if it aborts
1235 * in between. This function gets those checkpointed VSX registers.
1236 * The userspace interface buffer layout is as follows.
1242 static int tm_cvsx_get(struct task_struct *target,
1243 const struct user_regset *regset,
1244 unsigned int pos, unsigned int count,
1245 void *kbuf, void __user *ubuf)
1250 if (!cpu_has_feature(CPU_FTR_TM))
1253 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1256 /* Flush the state */
1257 flush_tmregs_to_thread(target);
1258 flush_fp_to_thread(target);
1259 flush_altivec_to_thread(target);
1260 flush_vsx_to_thread(target);
1262 for (i = 0; i < 32 ; i++)
1263 buf[i] = target->thread.ckfp_state.fpr[i][TS_VSRLOWOFFSET];
1264 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1265 buf, 0, 32 * sizeof(double));
1271 * tm_cvsx_set - set CFPR registers
1272 * @target: The target task.
1273 * @regset: The user regset structure.
1274 * @pos: The buffer position.
1275 * @count: Number of bytes to copy.
1276 * @kbuf: Kernel buffer to copy into.
1277 * @ubuf: User buffer to copy from.
1279 * This function sets in transaction checkpointed VSX registers.
1281 * When the transaction is active 'ckfp_state' holds the checkpointed
1282 * VSX register values for the current transaction to fall back on
1283 * if it aborts in between. This function sets these checkpointed
1284 * FPR registers. The userspace interface buffer layout is as follows.
1290 static int tm_cvsx_set(struct task_struct *target,
1291 const struct user_regset *regset,
1292 unsigned int pos, unsigned int count,
1293 const void *kbuf, const void __user *ubuf)
1298 if (!cpu_has_feature(CPU_FTR_TM))
1301 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1304 /* Flush the state */
1305 flush_tmregs_to_thread(target);
1306 flush_fp_to_thread(target);
1307 flush_altivec_to_thread(target);
1308 flush_vsx_to_thread(target);
1310 for (i = 0; i < 32 ; i++)
1311 buf[i] = target->thread.ckfp_state.fpr[i][TS_VSRLOWOFFSET];
1313 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1314 buf, 0, 32 * sizeof(double));
1316 for (i = 0; i < 32 ; i++)
1317 target->thread.ckfp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i];
1323 * tm_spr_active - get active number of registers in TM SPR
1324 * @target: The target task.
1325 * @regset: The user regset structure.
1327 * This function checks the active number of available
1328 * regisers in the transactional memory SPR category.
1330 static int tm_spr_active(struct task_struct *target,
1331 const struct user_regset *regset)
1333 if (!cpu_has_feature(CPU_FTR_TM))
1340 * tm_spr_get - get the TM related SPR registers
1341 * @target: The target task.
1342 * @regset: The user regset structure.
1343 * @pos: The buffer position.
1344 * @count: Number of bytes to copy.
1345 * @kbuf: Kernel buffer to copy from.
1346 * @ubuf: User buffer to copy into.
1348 * This function gets transactional memory related SPR registers.
1349 * The userspace interface buffer layout is as follows.
1357 static int tm_spr_get(struct task_struct *target,
1358 const struct user_regset *regset,
1359 unsigned int pos, unsigned int count,
1360 void *kbuf, void __user *ubuf)
1365 BUILD_BUG_ON(TSO(tm_tfhar) + sizeof(u64) != TSO(tm_texasr));
1366 BUILD_BUG_ON(TSO(tm_texasr) + sizeof(u64) != TSO(tm_tfiar));
1367 BUILD_BUG_ON(TSO(tm_tfiar) + sizeof(u64) != TSO(ckpt_regs));
1369 if (!cpu_has_feature(CPU_FTR_TM))
1372 /* Flush the states */
1373 flush_tmregs_to_thread(target);
1374 flush_fp_to_thread(target);
1375 flush_altivec_to_thread(target);
1377 /* TFHAR register */
1378 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1379 &target->thread.tm_tfhar, 0, sizeof(u64));
1381 /* TEXASR register */
1383 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1384 &target->thread.tm_texasr, sizeof(u64),
1387 /* TFIAR register */
1389 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1390 &target->thread.tm_tfiar,
1391 2 * sizeof(u64), 3 * sizeof(u64));
1396 * tm_spr_set - set the TM related SPR registers
1397 * @target: The target task.
1398 * @regset: The user regset structure.
1399 * @pos: The buffer position.
1400 * @count: Number of bytes to copy.
1401 * @kbuf: Kernel buffer to copy into.
1402 * @ubuf: User buffer to copy from.
1404 * This function sets transactional memory related SPR registers.
1405 * The userspace interface buffer layout is as follows.
1413 static int tm_spr_set(struct task_struct *target,
1414 const struct user_regset *regset,
1415 unsigned int pos, unsigned int count,
1416 const void *kbuf, const void __user *ubuf)
1421 BUILD_BUG_ON(TSO(tm_tfhar) + sizeof(u64) != TSO(tm_texasr));
1422 BUILD_BUG_ON(TSO(tm_texasr) + sizeof(u64) != TSO(tm_tfiar));
1423 BUILD_BUG_ON(TSO(tm_tfiar) + sizeof(u64) != TSO(ckpt_regs));
1425 if (!cpu_has_feature(CPU_FTR_TM))
1428 /* Flush the states */
1429 flush_tmregs_to_thread(target);
1430 flush_fp_to_thread(target);
1431 flush_altivec_to_thread(target);
1433 /* TFHAR register */
1434 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1435 &target->thread.tm_tfhar, 0, sizeof(u64));
1437 /* TEXASR register */
1439 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1440 &target->thread.tm_texasr, sizeof(u64),
1443 /* TFIAR register */
1445 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1446 &target->thread.tm_tfiar,
1447 2 * sizeof(u64), 3 * sizeof(u64));
1451 static int tm_tar_active(struct task_struct *target,
1452 const struct user_regset *regset)
1454 if (!cpu_has_feature(CPU_FTR_TM))
1457 if (MSR_TM_ACTIVE(target->thread.regs->msr))
1463 static int tm_tar_get(struct task_struct *target,
1464 const struct user_regset *regset,
1465 unsigned int pos, unsigned int count,
1466 void *kbuf, void __user *ubuf)
1470 if (!cpu_has_feature(CPU_FTR_TM))
1473 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1476 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1477 &target->thread.tm_tar, 0, sizeof(u64));
1481 static int tm_tar_set(struct task_struct *target,
1482 const struct user_regset *regset,
1483 unsigned int pos, unsigned int count,
1484 const void *kbuf, const void __user *ubuf)
1488 if (!cpu_has_feature(CPU_FTR_TM))
1491 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1494 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1495 &target->thread.tm_tar, 0, sizeof(u64));
1499 static int tm_ppr_active(struct task_struct *target,
1500 const struct user_regset *regset)
1502 if (!cpu_has_feature(CPU_FTR_TM))
1505 if (MSR_TM_ACTIVE(target->thread.regs->msr))
1512 static int tm_ppr_get(struct task_struct *target,
1513 const struct user_regset *regset,
1514 unsigned int pos, unsigned int count,
1515 void *kbuf, void __user *ubuf)
1519 if (!cpu_has_feature(CPU_FTR_TM))
1522 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1525 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1526 &target->thread.tm_ppr, 0, sizeof(u64));
1530 static int tm_ppr_set(struct task_struct *target,
1531 const struct user_regset *regset,
1532 unsigned int pos, unsigned int count,
1533 const void *kbuf, const void __user *ubuf)
1537 if (!cpu_has_feature(CPU_FTR_TM))
1540 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1543 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1544 &target->thread.tm_ppr, 0, sizeof(u64));
1548 static int tm_dscr_active(struct task_struct *target,
1549 const struct user_regset *regset)
1551 if (!cpu_has_feature(CPU_FTR_TM))
1554 if (MSR_TM_ACTIVE(target->thread.regs->msr))
1560 static int tm_dscr_get(struct task_struct *target,
1561 const struct user_regset *regset,
1562 unsigned int pos, unsigned int count,
1563 void *kbuf, void __user *ubuf)
1567 if (!cpu_has_feature(CPU_FTR_TM))
1570 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1573 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1574 &target->thread.tm_dscr, 0, sizeof(u64));
1578 static int tm_dscr_set(struct task_struct *target,
1579 const struct user_regset *regset,
1580 unsigned int pos, unsigned int count,
1581 const void *kbuf, const void __user *ubuf)
1585 if (!cpu_has_feature(CPU_FTR_TM))
1588 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1591 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1592 &target->thread.tm_dscr, 0, sizeof(u64));
1595 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1598 static int ppr_get(struct task_struct *target,
1599 const struct user_regset *regset,
1600 unsigned int pos, unsigned int count,
1601 void *kbuf, void __user *ubuf)
1603 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1604 &target->thread.ppr, 0, sizeof(u64));
1607 static int ppr_set(struct task_struct *target,
1608 const struct user_regset *regset,
1609 unsigned int pos, unsigned int count,
1610 const void *kbuf, const void __user *ubuf)
1612 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1613 &target->thread.ppr, 0, sizeof(u64));
1616 static int dscr_get(struct task_struct *target,
1617 const struct user_regset *regset,
1618 unsigned int pos, unsigned int count,
1619 void *kbuf, void __user *ubuf)
1621 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1622 &target->thread.dscr, 0, sizeof(u64));
1624 static int dscr_set(struct task_struct *target,
1625 const struct user_regset *regset,
1626 unsigned int pos, unsigned int count,
1627 const void *kbuf, const void __user *ubuf)
1629 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1630 &target->thread.dscr, 0, sizeof(u64));
1633 #ifdef CONFIG_PPC_BOOK3S_64
1634 static int tar_get(struct task_struct *target,
1635 const struct user_regset *regset,
1636 unsigned int pos, unsigned int count,
1637 void *kbuf, void __user *ubuf)
1639 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1640 &target->thread.tar, 0, sizeof(u64));
1642 static int tar_set(struct task_struct *target,
1643 const struct user_regset *regset,
1644 unsigned int pos, unsigned int count,
1645 const void *kbuf, const void __user *ubuf)
1647 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1648 &target->thread.tar, 0, sizeof(u64));
1651 static int ebb_active(struct task_struct *target,
1652 const struct user_regset *regset)
1654 if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1657 if (target->thread.used_ebb)
1663 static int ebb_get(struct task_struct *target,
1664 const struct user_regset *regset,
1665 unsigned int pos, unsigned int count,
1666 void *kbuf, void __user *ubuf)
1669 BUILD_BUG_ON(TSO(ebbrr) + sizeof(unsigned long) != TSO(ebbhr));
1670 BUILD_BUG_ON(TSO(ebbhr) + sizeof(unsigned long) != TSO(bescr));
1672 if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1675 if (!target->thread.used_ebb)
1678 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1679 &target->thread.ebbrr, 0, 3 * sizeof(unsigned long));
1682 static int ebb_set(struct task_struct *target,
1683 const struct user_regset *regset,
1684 unsigned int pos, unsigned int count,
1685 const void *kbuf, const void __user *ubuf)
1690 BUILD_BUG_ON(TSO(ebbrr) + sizeof(unsigned long) != TSO(ebbhr));
1691 BUILD_BUG_ON(TSO(ebbhr) + sizeof(unsigned long) != TSO(bescr));
1693 if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1696 if (target->thread.used_ebb)
1699 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1700 &target->thread.ebbrr, 0, sizeof(unsigned long));
1703 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1704 &target->thread.ebbhr, sizeof(unsigned long),
1705 2 * sizeof(unsigned long));
1708 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1709 &target->thread.bescr,
1710 2 * sizeof(unsigned long), 3 * sizeof(unsigned long));
1714 static int pmu_active(struct task_struct *target,
1715 const struct user_regset *regset)
1717 if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1723 static int pmu_get(struct task_struct *target,
1724 const struct user_regset *regset,
1725 unsigned int pos, unsigned int count,
1726 void *kbuf, void __user *ubuf)
1729 BUILD_BUG_ON(TSO(siar) + sizeof(unsigned long) != TSO(sdar));
1730 BUILD_BUG_ON(TSO(sdar) + sizeof(unsigned long) != TSO(sier));
1731 BUILD_BUG_ON(TSO(sier) + sizeof(unsigned long) != TSO(mmcr2));
1732 BUILD_BUG_ON(TSO(mmcr2) + sizeof(unsigned long) != TSO(mmcr0));
1734 if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1737 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1738 &target->thread.siar, 0,
1739 5 * sizeof(unsigned long));
1742 static int pmu_set(struct task_struct *target,
1743 const struct user_regset *regset,
1744 unsigned int pos, unsigned int count,
1745 const void *kbuf, const void __user *ubuf)
1750 BUILD_BUG_ON(TSO(siar) + sizeof(unsigned long) != TSO(sdar));
1751 BUILD_BUG_ON(TSO(sdar) + sizeof(unsigned long) != TSO(sier));
1752 BUILD_BUG_ON(TSO(sier) + sizeof(unsigned long) != TSO(mmcr2));
1753 BUILD_BUG_ON(TSO(mmcr2) + sizeof(unsigned long) != TSO(mmcr0));
1755 if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1758 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1759 &target->thread.siar, 0,
1760 sizeof(unsigned long));
1763 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1764 &target->thread.sdar, sizeof(unsigned long),
1765 2 * sizeof(unsigned long));
1768 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1769 &target->thread.sier, 2 * sizeof(unsigned long),
1770 3 * sizeof(unsigned long));
1773 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1774 &target->thread.mmcr2, 3 * sizeof(unsigned long),
1775 4 * sizeof(unsigned long));
1778 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1779 &target->thread.mmcr0, 4 * sizeof(unsigned long),
1780 5 * sizeof(unsigned long));
1785 * These are our native regset flavors.
1787 enum powerpc_regset {
1790 #ifdef CONFIG_ALTIVEC
1799 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1800 REGSET_TM_CGPR, /* TM checkpointed GPR registers */
1801 REGSET_TM_CFPR, /* TM checkpointed FPR registers */
1802 REGSET_TM_CVMX, /* TM checkpointed VMX registers */
1803 REGSET_TM_CVSX, /* TM checkpointed VSX registers */
1804 REGSET_TM_SPR, /* TM specific SPR registers */
1805 REGSET_TM_CTAR, /* TM checkpointed TAR register */
1806 REGSET_TM_CPPR, /* TM checkpointed PPR register */
1807 REGSET_TM_CDSCR, /* TM checkpointed DSCR register */
1810 REGSET_PPR, /* PPR register */
1811 REGSET_DSCR, /* DSCR register */
1813 #ifdef CONFIG_PPC_BOOK3S_64
1814 REGSET_TAR, /* TAR register */
1815 REGSET_EBB, /* EBB registers */
1816 REGSET_PMR, /* Performance Monitor Registers */
1820 static const struct user_regset native_regsets[] = {
1822 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
1823 .size = sizeof(long), .align = sizeof(long),
1824 .get = gpr_get, .set = gpr_set
1827 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
1828 .size = sizeof(double), .align = sizeof(double),
1829 .get = fpr_get, .set = fpr_set
1831 #ifdef CONFIG_ALTIVEC
1833 .core_note_type = NT_PPC_VMX, .n = 34,
1834 .size = sizeof(vector128), .align = sizeof(vector128),
1835 .active = vr_active, .get = vr_get, .set = vr_set
1840 .core_note_type = NT_PPC_VSX, .n = 32,
1841 .size = sizeof(double), .align = sizeof(double),
1842 .active = vsr_active, .get = vsr_get, .set = vsr_set
1847 .core_note_type = NT_PPC_SPE, .n = 35,
1848 .size = sizeof(u32), .align = sizeof(u32),
1849 .active = evr_active, .get = evr_get, .set = evr_set
1852 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1853 [REGSET_TM_CGPR] = {
1854 .core_note_type = NT_PPC_TM_CGPR, .n = ELF_NGREG,
1855 .size = sizeof(long), .align = sizeof(long),
1856 .active = tm_cgpr_active, .get = tm_cgpr_get, .set = tm_cgpr_set
1858 [REGSET_TM_CFPR] = {
1859 .core_note_type = NT_PPC_TM_CFPR, .n = ELF_NFPREG,
1860 .size = sizeof(double), .align = sizeof(double),
1861 .active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set
1863 [REGSET_TM_CVMX] = {
1864 .core_note_type = NT_PPC_TM_CVMX, .n = ELF_NVMX,
1865 .size = sizeof(vector128), .align = sizeof(vector128),
1866 .active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set
1868 [REGSET_TM_CVSX] = {
1869 .core_note_type = NT_PPC_TM_CVSX, .n = ELF_NVSX,
1870 .size = sizeof(double), .align = sizeof(double),
1871 .active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set
1874 .core_note_type = NT_PPC_TM_SPR, .n = ELF_NTMSPRREG,
1875 .size = sizeof(u64), .align = sizeof(u64),
1876 .active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set
1878 [REGSET_TM_CTAR] = {
1879 .core_note_type = NT_PPC_TM_CTAR, .n = 1,
1880 .size = sizeof(u64), .align = sizeof(u64),
1881 .active = tm_tar_active, .get = tm_tar_get, .set = tm_tar_set
1883 [REGSET_TM_CPPR] = {
1884 .core_note_type = NT_PPC_TM_CPPR, .n = 1,
1885 .size = sizeof(u64), .align = sizeof(u64),
1886 .active = tm_ppr_active, .get = tm_ppr_get, .set = tm_ppr_set
1888 [REGSET_TM_CDSCR] = {
1889 .core_note_type = NT_PPC_TM_CDSCR, .n = 1,
1890 .size = sizeof(u64), .align = sizeof(u64),
1891 .active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set
1896 .core_note_type = NT_PPC_PPR, .n = 1,
1897 .size = sizeof(u64), .align = sizeof(u64),
1898 .get = ppr_get, .set = ppr_set
1901 .core_note_type = NT_PPC_DSCR, .n = 1,
1902 .size = sizeof(u64), .align = sizeof(u64),
1903 .get = dscr_get, .set = dscr_set
1906 #ifdef CONFIG_PPC_BOOK3S_64
1908 .core_note_type = NT_PPC_TAR, .n = 1,
1909 .size = sizeof(u64), .align = sizeof(u64),
1910 .get = tar_get, .set = tar_set
1913 .core_note_type = NT_PPC_EBB, .n = ELF_NEBB,
1914 .size = sizeof(u64), .align = sizeof(u64),
1915 .active = ebb_active, .get = ebb_get, .set = ebb_set
1918 .core_note_type = NT_PPC_PMU, .n = ELF_NPMU,
1919 .size = sizeof(u64), .align = sizeof(u64),
1920 .active = pmu_active, .get = pmu_get, .set = pmu_set
1925 static const struct user_regset_view user_ppc_native_view = {
1926 .name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI,
1927 .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets)
1931 #include <linux/compat.h>
1933 static int gpr32_get_common(struct task_struct *target,
1934 const struct user_regset *regset,
1935 unsigned int pos, unsigned int count,
1936 void *kbuf, void __user *ubuf,
1937 unsigned long *regs)
1939 compat_ulong_t *k = kbuf;
1940 compat_ulong_t __user *u = ubuf;
1944 count /= sizeof(reg);
1947 for (; count > 0 && pos < PT_MSR; --count)
1950 for (; count > 0 && pos < PT_MSR; --count)
1951 if (__put_user((compat_ulong_t) regs[pos++], u++))
1954 if (count > 0 && pos == PT_MSR) {
1955 reg = get_user_msr(target);
1958 else if (__put_user(reg, u++))
1965 for (; count > 0 && pos < PT_REGS_COUNT; --count)
1968 for (; count > 0 && pos < PT_REGS_COUNT; --count)
1969 if (__put_user((compat_ulong_t) regs[pos++], u++))
1975 count *= sizeof(reg);
1976 return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
1977 PT_REGS_COUNT * sizeof(reg), -1);
1980 static int gpr32_set_common(struct task_struct *target,
1981 const struct user_regset *regset,
1982 unsigned int pos, unsigned int count,
1983 const void *kbuf, const void __user *ubuf,
1984 unsigned long *regs)
1986 const compat_ulong_t *k = kbuf;
1987 const compat_ulong_t __user *u = ubuf;
1991 count /= sizeof(reg);
1994 for (; count > 0 && pos < PT_MSR; --count)
1997 for (; count > 0 && pos < PT_MSR; --count) {
1998 if (__get_user(reg, u++))
2004 if (count > 0 && pos == PT_MSR) {
2007 else if (__get_user(reg, u++))
2009 set_user_msr(target, reg);
2015 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count)
2017 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
2020 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) {
2021 if (__get_user(reg, u++))
2025 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
2026 if (__get_user(reg, u++))
2030 if (count > 0 && pos == PT_TRAP) {
2033 else if (__get_user(reg, u++))
2035 set_user_trap(target, reg);
2043 count *= sizeof(reg);
2044 return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
2045 (PT_TRAP + 1) * sizeof(reg), -1);
2048 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2049 static int tm_cgpr32_get(struct task_struct *target,
2050 const struct user_regset *regset,
2051 unsigned int pos, unsigned int count,
2052 void *kbuf, void __user *ubuf)
2054 return gpr32_get_common(target, regset, pos, count, kbuf, ubuf,
2055 &target->thread.ckpt_regs.gpr[0]);
2058 static int tm_cgpr32_set(struct task_struct *target,
2059 const struct user_regset *regset,
2060 unsigned int pos, unsigned int count,
2061 const void *kbuf, const void __user *ubuf)
2063 return gpr32_set_common(target, regset, pos, count, kbuf, ubuf,
2064 &target->thread.ckpt_regs.gpr[0]);
2066 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2068 static int gpr32_get(struct task_struct *target,
2069 const struct user_regset *regset,
2070 unsigned int pos, unsigned int count,
2071 void *kbuf, void __user *ubuf)
2075 if (target->thread.regs == NULL)
2078 if (!FULL_REGS(target->thread.regs)) {
2080 * We have a partial register set.
2081 * Fill 14-31 with bogus values.
2083 for (i = 14; i < 32; i++)
2084 target->thread.regs->gpr[i] = NV_REG_POISON;
2086 return gpr32_get_common(target, regset, pos, count, kbuf, ubuf,
2087 &target->thread.regs->gpr[0]);
2090 static int gpr32_set(struct task_struct *target,
2091 const struct user_regset *regset,
2092 unsigned int pos, unsigned int count,
2093 const void *kbuf, const void __user *ubuf)
2095 if (target->thread.regs == NULL)
2098 CHECK_FULL_REGS(target->thread.regs);
2099 return gpr32_set_common(target, regset, pos, count, kbuf, ubuf,
2100 &target->thread.regs->gpr[0]);
2104 * These are the regset flavors matching the CONFIG_PPC32 native set.
2106 static const struct user_regset compat_regsets[] = {
2108 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
2109 .size = sizeof(compat_long_t), .align = sizeof(compat_long_t),
2110 .get = gpr32_get, .set = gpr32_set
2113 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
2114 .size = sizeof(double), .align = sizeof(double),
2115 .get = fpr_get, .set = fpr_set
2117 #ifdef CONFIG_ALTIVEC
2119 .core_note_type = NT_PPC_VMX, .n = 34,
2120 .size = sizeof(vector128), .align = sizeof(vector128),
2121 .active = vr_active, .get = vr_get, .set = vr_set
2126 .core_note_type = NT_PPC_SPE, .n = 35,
2127 .size = sizeof(u32), .align = sizeof(u32),
2128 .active = evr_active, .get = evr_get, .set = evr_set
2131 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2132 [REGSET_TM_CGPR] = {
2133 .core_note_type = NT_PPC_TM_CGPR, .n = ELF_NGREG,
2134 .size = sizeof(long), .align = sizeof(long),
2135 .active = tm_cgpr_active,
2136 .get = tm_cgpr32_get, .set = tm_cgpr32_set
2138 [REGSET_TM_CFPR] = {
2139 .core_note_type = NT_PPC_TM_CFPR, .n = ELF_NFPREG,
2140 .size = sizeof(double), .align = sizeof(double),
2141 .active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set
2143 [REGSET_TM_CVMX] = {
2144 .core_note_type = NT_PPC_TM_CVMX, .n = ELF_NVMX,
2145 .size = sizeof(vector128), .align = sizeof(vector128),
2146 .active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set
2148 [REGSET_TM_CVSX] = {
2149 .core_note_type = NT_PPC_TM_CVSX, .n = ELF_NVSX,
2150 .size = sizeof(double), .align = sizeof(double),
2151 .active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set
2154 .core_note_type = NT_PPC_TM_SPR, .n = ELF_NTMSPRREG,
2155 .size = sizeof(u64), .align = sizeof(u64),
2156 .active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set
2158 [REGSET_TM_CTAR] = {
2159 .core_note_type = NT_PPC_TM_CTAR, .n = 1,
2160 .size = sizeof(u64), .align = sizeof(u64),
2161 .active = tm_tar_active, .get = tm_tar_get, .set = tm_tar_set
2163 [REGSET_TM_CPPR] = {
2164 .core_note_type = NT_PPC_TM_CPPR, .n = 1,
2165 .size = sizeof(u64), .align = sizeof(u64),
2166 .active = tm_ppr_active, .get = tm_ppr_get, .set = tm_ppr_set
2168 [REGSET_TM_CDSCR] = {
2169 .core_note_type = NT_PPC_TM_CDSCR, .n = 1,
2170 .size = sizeof(u64), .align = sizeof(u64),
2171 .active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set
2176 .core_note_type = NT_PPC_PPR, .n = 1,
2177 .size = sizeof(u64), .align = sizeof(u64),
2178 .get = ppr_get, .set = ppr_set
2181 .core_note_type = NT_PPC_DSCR, .n = 1,
2182 .size = sizeof(u64), .align = sizeof(u64),
2183 .get = dscr_get, .set = dscr_set
2186 #ifdef CONFIG_PPC_BOOK3S_64
2188 .core_note_type = NT_PPC_TAR, .n = 1,
2189 .size = sizeof(u64), .align = sizeof(u64),
2190 .get = tar_get, .set = tar_set
2193 .core_note_type = NT_PPC_EBB, .n = ELF_NEBB,
2194 .size = sizeof(u64), .align = sizeof(u64),
2195 .active = ebb_active, .get = ebb_get, .set = ebb_set
2200 static const struct user_regset_view user_ppc_compat_view = {
2201 .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI,
2202 .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets)
2204 #endif /* CONFIG_PPC64 */
2206 const struct user_regset_view *task_user_regset_view(struct task_struct *task)
2209 if (test_tsk_thread_flag(task, TIF_32BIT))
2210 return &user_ppc_compat_view;
2212 return &user_ppc_native_view;
2216 void user_enable_single_step(struct task_struct *task)
2218 struct pt_regs *regs = task->thread.regs;
2221 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2222 task->thread.debug.dbcr0 &= ~DBCR0_BT;
2223 task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
2224 regs->msr |= MSR_DE;
2226 regs->msr &= ~MSR_BE;
2227 regs->msr |= MSR_SE;
2230 set_tsk_thread_flag(task, TIF_SINGLESTEP);
2233 void user_enable_block_step(struct task_struct *task)
2235 struct pt_regs *regs = task->thread.regs;
2238 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2239 task->thread.debug.dbcr0 &= ~DBCR0_IC;
2240 task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT;
2241 regs->msr |= MSR_DE;
2243 regs->msr &= ~MSR_SE;
2244 regs->msr |= MSR_BE;
2247 set_tsk_thread_flag(task, TIF_SINGLESTEP);
2250 void user_disable_single_step(struct task_struct *task)
2252 struct pt_regs *regs = task->thread.regs;
2255 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2257 * The logic to disable single stepping should be as
2258 * simple as turning off the Instruction Complete flag.
2259 * And, after doing so, if all debug flags are off, turn
2260 * off DBCR0(IDM) and MSR(DE) .... Torez
2262 task->thread.debug.dbcr0 &= ~(DBCR0_IC|DBCR0_BT);
2264 * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
2266 if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
2267 task->thread.debug.dbcr1)) {
2269 * All debug events were off.....
2271 task->thread.debug.dbcr0 &= ~DBCR0_IDM;
2272 regs->msr &= ~MSR_DE;
2275 regs->msr &= ~(MSR_SE | MSR_BE);
2278 clear_tsk_thread_flag(task, TIF_SINGLESTEP);
2281 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2282 void ptrace_triggered(struct perf_event *bp,
2283 struct perf_sample_data *data, struct pt_regs *regs)
2285 struct perf_event_attr attr;
2288 * Disable the breakpoint request here since ptrace has defined a
2289 * one-shot behaviour for breakpoint exceptions in PPC64.
2290 * The SIGTRAP signal is generated automatically for us in do_dabr().
2291 * We don't have to do anything about that here
2294 attr.disabled = true;
2295 modify_user_hw_breakpoint(bp, &attr);
2297 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2299 static int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
2302 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2304 struct thread_struct *thread = &(task->thread);
2305 struct perf_event *bp;
2306 struct perf_event_attr attr;
2307 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2308 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
2309 struct arch_hw_breakpoint hw_brk;
2312 /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
2313 * For embedded processors we support one DAC and no IAC's at the
2319 /* The bottom 3 bits in dabr are flags */
2320 if ((data & ~0x7UL) >= TASK_SIZE)
2323 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
2324 /* For processors using DABR (i.e. 970), the bottom 3 bits are flags.
2325 * It was assumed, on previous implementations, that 3 bits were
2326 * passed together with the data address, fitting the design of the
2327 * DABR register, as follows:
2331 * bit 2: Breakpoint translation
2333 * Thus, we use them here as so.
2336 /* Ensure breakpoint translation bit is set */
2337 if (data && !(data & HW_BRK_TYPE_TRANSLATE))
2339 hw_brk.address = data & (~HW_BRK_TYPE_DABR);
2340 hw_brk.type = (data & HW_BRK_TYPE_DABR) | HW_BRK_TYPE_PRIV_ALL;
2342 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2343 bp = thread->ptrace_bps[0];
2344 if ((!data) || !(hw_brk.type & HW_BRK_TYPE_RDWR)) {
2346 unregister_hw_breakpoint(bp);
2347 thread->ptrace_bps[0] = NULL;
2353 attr.bp_addr = hw_brk.address;
2354 arch_bp_generic_fields(hw_brk.type, &attr.bp_type);
2356 /* Enable breakpoint */
2357 attr.disabled = false;
2359 ret = modify_user_hw_breakpoint(bp, &attr);
2363 thread->ptrace_bps[0] = bp;
2364 thread->hw_brk = hw_brk;
2368 /* Create a new breakpoint request if one doesn't exist already */
2369 hw_breakpoint_init(&attr);
2370 attr.bp_addr = hw_brk.address;
2372 arch_bp_generic_fields(hw_brk.type,
2375 thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
2376 ptrace_triggered, NULL, task);
2378 thread->ptrace_bps[0] = NULL;
2382 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2383 task->thread.hw_brk = hw_brk;
2384 #else /* CONFIG_PPC_ADV_DEBUG_REGS */
2385 /* As described above, it was assumed 3 bits were passed with the data
2386 * address, but we will assume only the mode bits will be passed
2387 * as to not cause alignment restrictions for DAC-based processors.
2390 /* DAC's hold the whole address without any mode flags */
2391 task->thread.debug.dac1 = data & ~0x3UL;
2393 if (task->thread.debug.dac1 == 0) {
2394 dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
2395 if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
2396 task->thread.debug.dbcr1)) {
2397 task->thread.regs->msr &= ~MSR_DE;
2398 task->thread.debug.dbcr0 &= ~DBCR0_IDM;
2403 /* Read or Write bits must be set */
2405 if (!(data & 0x3UL))
2408 /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
2410 task->thread.debug.dbcr0 |= DBCR0_IDM;
2412 /* Check for write and read flags and set DBCR0
2414 dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W);
2416 dbcr_dac(task) |= DBCR_DAC1R;
2418 dbcr_dac(task) |= DBCR_DAC1W;
2419 task->thread.regs->msr |= MSR_DE;
2420 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
2425 * Called by kernel/ptrace.c when detaching..
2427 * Make sure single step bits etc are not set.
2429 void ptrace_disable(struct task_struct *child)
2431 /* make sure the single step bit is not set. */
2432 user_disable_single_step(child);
2435 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2436 static long set_instruction_bp(struct task_struct *child,
2437 struct ppc_hw_breakpoint *bp_info)
2440 int slot1_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC1) != 0);
2441 int slot2_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC2) != 0);
2442 int slot3_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC3) != 0);
2443 int slot4_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC4) != 0);
2445 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
2447 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
2450 if (bp_info->addr >= TASK_SIZE)
2453 if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
2455 /* Make sure range is valid. */
2456 if (bp_info->addr2 >= TASK_SIZE)
2459 /* We need a pair of IAC regsisters */
2460 if ((!slot1_in_use) && (!slot2_in_use)) {
2462 child->thread.debug.iac1 = bp_info->addr;
2463 child->thread.debug.iac2 = bp_info->addr2;
2464 child->thread.debug.dbcr0 |= DBCR0_IAC1;
2465 if (bp_info->addr_mode ==
2466 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
2467 dbcr_iac_range(child) |= DBCR_IAC12X;
2469 dbcr_iac_range(child) |= DBCR_IAC12I;
2470 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
2471 } else if ((!slot3_in_use) && (!slot4_in_use)) {
2473 child->thread.debug.iac3 = bp_info->addr;
2474 child->thread.debug.iac4 = bp_info->addr2;
2475 child->thread.debug.dbcr0 |= DBCR0_IAC3;
2476 if (bp_info->addr_mode ==
2477 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
2478 dbcr_iac_range(child) |= DBCR_IAC34X;
2480 dbcr_iac_range(child) |= DBCR_IAC34I;
2485 /* We only need one. If possible leave a pair free in
2486 * case a range is needed later
2488 if (!slot1_in_use) {
2490 * Don't use iac1 if iac1-iac2 are free and either
2491 * iac3 or iac4 (but not both) are free
2493 if (slot2_in_use || (slot3_in_use == slot4_in_use)) {
2495 child->thread.debug.iac1 = bp_info->addr;
2496 child->thread.debug.dbcr0 |= DBCR0_IAC1;
2500 if (!slot2_in_use) {
2502 child->thread.debug.iac2 = bp_info->addr;
2503 child->thread.debug.dbcr0 |= DBCR0_IAC2;
2504 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
2505 } else if (!slot3_in_use) {
2507 child->thread.debug.iac3 = bp_info->addr;
2508 child->thread.debug.dbcr0 |= DBCR0_IAC3;
2509 } else if (!slot4_in_use) {
2511 child->thread.debug.iac4 = bp_info->addr;
2512 child->thread.debug.dbcr0 |= DBCR0_IAC4;
2518 child->thread.debug.dbcr0 |= DBCR0_IDM;
2519 child->thread.regs->msr |= MSR_DE;
2524 static int del_instruction_bp(struct task_struct *child, int slot)
2528 if ((child->thread.debug.dbcr0 & DBCR0_IAC1) == 0)
2531 if (dbcr_iac_range(child) & DBCR_IAC12MODE) {
2532 /* address range - clear slots 1 & 2 */
2533 child->thread.debug.iac2 = 0;
2534 dbcr_iac_range(child) &= ~DBCR_IAC12MODE;
2536 child->thread.debug.iac1 = 0;
2537 child->thread.debug.dbcr0 &= ~DBCR0_IAC1;
2540 if ((child->thread.debug.dbcr0 & DBCR0_IAC2) == 0)
2543 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
2544 /* used in a range */
2546 child->thread.debug.iac2 = 0;
2547 child->thread.debug.dbcr0 &= ~DBCR0_IAC2;
2549 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
2551 if ((child->thread.debug.dbcr0 & DBCR0_IAC3) == 0)
2554 if (dbcr_iac_range(child) & DBCR_IAC34MODE) {
2555 /* address range - clear slots 3 & 4 */
2556 child->thread.debug.iac4 = 0;
2557 dbcr_iac_range(child) &= ~DBCR_IAC34MODE;
2559 child->thread.debug.iac3 = 0;
2560 child->thread.debug.dbcr0 &= ~DBCR0_IAC3;
2563 if ((child->thread.debug.dbcr0 & DBCR0_IAC4) == 0)
2566 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
2567 /* Used in a range */
2569 child->thread.debug.iac4 = 0;
2570 child->thread.debug.dbcr0 &= ~DBCR0_IAC4;
2579 static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
2582 (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT)
2584 int condition_mode =
2585 bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE;
2588 if (byte_enable && (condition_mode == 0))
2591 if (bp_info->addr >= TASK_SIZE)
2594 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) {
2596 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
2597 dbcr_dac(child) |= DBCR_DAC1R;
2598 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
2599 dbcr_dac(child) |= DBCR_DAC1W;
2600 child->thread.debug.dac1 = (unsigned long)bp_info->addr;
2601 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2603 child->thread.debug.dvc1 =
2604 (unsigned long)bp_info->condition_value;
2605 child->thread.debug.dbcr2 |=
2606 ((byte_enable << DBCR2_DVC1BE_SHIFT) |
2607 (condition_mode << DBCR2_DVC1M_SHIFT));
2610 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2611 } else if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
2612 /* Both dac1 and dac2 are part of a range */
2615 } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) {
2617 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
2618 dbcr_dac(child) |= DBCR_DAC2R;
2619 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
2620 dbcr_dac(child) |= DBCR_DAC2W;
2621 child->thread.debug.dac2 = (unsigned long)bp_info->addr;
2622 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2624 child->thread.debug.dvc2 =
2625 (unsigned long)bp_info->condition_value;
2626 child->thread.debug.dbcr2 |=
2627 ((byte_enable << DBCR2_DVC2BE_SHIFT) |
2628 (condition_mode << DBCR2_DVC2M_SHIFT));
2633 child->thread.debug.dbcr0 |= DBCR0_IDM;
2634 child->thread.regs->msr |= MSR_DE;
2639 static int del_dac(struct task_struct *child, int slot)
2642 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0)
2645 child->thread.debug.dac1 = 0;
2646 dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W);
2647 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2648 if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
2649 child->thread.debug.dac2 = 0;
2650 child->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
2652 child->thread.debug.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
2654 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2655 child->thread.debug.dvc1 = 0;
2657 } else if (slot == 2) {
2658 if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0)
2661 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2662 if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE)
2663 /* Part of a range */
2665 child->thread.debug.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
2667 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2668 child->thread.debug.dvc2 = 0;
2670 child->thread.debug.dac2 = 0;
2671 dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W);
2677 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
2679 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2680 static int set_dac_range(struct task_struct *child,
2681 struct ppc_hw_breakpoint *bp_info)
2683 int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK;
2685 /* We don't allow range watchpoints to be used with DVC */
2686 if (bp_info->condition_mode)
2690 * Best effort to verify the address range. The user/supervisor bits
2691 * prevent trapping in kernel space, but let's fail on an obvious bad
2692 * range. The simple test on the mask is not fool-proof, and any
2693 * exclusive range will spill over into kernel space.
2695 if (bp_info->addr >= TASK_SIZE)
2697 if (mode == PPC_BREAKPOINT_MODE_MASK) {
2699 * dac2 is a bitmask. Don't allow a mask that makes a
2700 * kernel space address from a valid dac1 value
2702 if (~((unsigned long)bp_info->addr2) >= TASK_SIZE)
2706 * For range breakpoints, addr2 must also be a valid address
2708 if (bp_info->addr2 >= TASK_SIZE)
2712 if (child->thread.debug.dbcr0 &
2713 (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W))
2716 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
2717 child->thread.debug.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
2718 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
2719 child->thread.debug.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
2720 child->thread.debug.dac1 = bp_info->addr;
2721 child->thread.debug.dac2 = bp_info->addr2;
2722 if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
2723 child->thread.debug.dbcr2 |= DBCR2_DAC12M;
2724 else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
2725 child->thread.debug.dbcr2 |= DBCR2_DAC12MX;
2726 else /* PPC_BREAKPOINT_MODE_MASK */
2727 child->thread.debug.dbcr2 |= DBCR2_DAC12MM;
2728 child->thread.regs->msr |= MSR_DE;
2732 #endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */
2734 static long ppc_set_hwdebug(struct task_struct *child,
2735 struct ppc_hw_breakpoint *bp_info)
2737 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2739 struct thread_struct *thread = &(child->thread);
2740 struct perf_event *bp;
2741 struct perf_event_attr attr;
2742 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2743 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
2744 struct arch_hw_breakpoint brk;
2747 if (bp_info->version != 1)
2749 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2751 * Check for invalid flags and combinations
2753 if ((bp_info->trigger_type == 0) ||
2754 (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE |
2755 PPC_BREAKPOINT_TRIGGER_RW)) ||
2756 (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) ||
2757 (bp_info->condition_mode &
2758 ~(PPC_BREAKPOINT_CONDITION_MODE |
2759 PPC_BREAKPOINT_CONDITION_BE_ALL)))
2761 #if CONFIG_PPC_ADV_DEBUG_DVCS == 0
2762 if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
2766 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) {
2767 if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) ||
2768 (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
2770 return set_instruction_bp(child, bp_info);
2772 if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
2773 return set_dac(child, bp_info);
2775 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2776 return set_dac_range(child, bp_info);
2780 #else /* !CONFIG_PPC_ADV_DEBUG_DVCS */
2782 * We only support one data breakpoint
2784 if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 ||
2785 (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 ||
2786 bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
2789 if ((unsigned long)bp_info->addr >= TASK_SIZE)
2792 brk.address = bp_info->addr & ~7UL;
2793 brk.type = HW_BRK_TYPE_TRANSLATE;
2795 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
2796 brk.type |= HW_BRK_TYPE_READ;
2797 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
2798 brk.type |= HW_BRK_TYPE_WRITE;
2799 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2801 * Check if the request is for 'range' breakpoints. We can
2802 * support it if range < 8 bytes.
2804 if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
2805 len = bp_info->addr2 - bp_info->addr;
2806 else if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
2810 bp = thread->ptrace_bps[0];
2814 /* Create a new breakpoint request if one doesn't exist already */
2815 hw_breakpoint_init(&attr);
2816 attr.bp_addr = (unsigned long)bp_info->addr & ~HW_BREAKPOINT_ALIGN;
2818 arch_bp_generic_fields(brk.type, &attr.bp_type);
2820 thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
2821 ptrace_triggered, NULL, child);
2823 thread->ptrace_bps[0] = NULL;
2828 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2830 if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT)
2833 if (child->thread.hw_brk.address)
2836 child->thread.hw_brk = brk;
2839 #endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */
2842 static long ppc_del_hwdebug(struct task_struct *child, long data)
2844 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2846 struct thread_struct *thread = &(child->thread);
2847 struct perf_event *bp;
2848 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2849 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2853 rc = del_instruction_bp(child, (int)data);
2855 rc = del_dac(child, (int)data - 4);
2858 if (!DBCR_ACTIVE_EVENTS(child->thread.debug.dbcr0,
2859 child->thread.debug.dbcr1)) {
2860 child->thread.debug.dbcr0 &= ~DBCR0_IDM;
2861 child->thread.regs->msr &= ~MSR_DE;
2869 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2870 bp = thread->ptrace_bps[0];
2872 unregister_hw_breakpoint(bp);
2873 thread->ptrace_bps[0] = NULL;
2877 #else /* CONFIG_HAVE_HW_BREAKPOINT */
2878 if (child->thread.hw_brk.address == 0)
2881 child->thread.hw_brk.address = 0;
2882 child->thread.hw_brk.type = 0;
2883 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2889 long arch_ptrace(struct task_struct *child, long request,
2890 unsigned long addr, unsigned long data)
2893 void __user *datavp = (void __user *) data;
2894 unsigned long __user *datalp = datavp;
2897 /* read the word at location addr in the USER area. */
2898 case PTRACE_PEEKUSR: {
2899 unsigned long index, tmp;
2902 /* convert to index and check */
2905 if ((addr & 3) || (index > PT_FPSCR)
2906 || (child->thread.regs == NULL))
2909 if ((addr & 7) || (index > PT_FPSCR))
2913 CHECK_FULL_REGS(child->thread.regs);
2914 if (index < PT_FPR0) {
2915 ret = ptrace_get_reg(child, (int) index, &tmp);
2919 unsigned int fpidx = index - PT_FPR0;
2921 flush_fp_to_thread(child);
2922 if (fpidx < (PT_FPSCR - PT_FPR0))
2923 if (IS_ENABLED(CONFIG_PPC32)) {
2924 // On 32-bit the index we are passed refers to 32-bit words
2925 tmp = ((u32 *)child->thread.fp_state.fpr)[fpidx];
2927 memcpy(&tmp, &child->thread.TS_FPR(fpidx),
2931 tmp = child->thread.fp_state.fpscr;
2933 ret = put_user(tmp, datalp);
2937 /* write the word at location addr in the USER area */
2938 case PTRACE_POKEUSR: {
2939 unsigned long index;
2942 /* convert to index and check */
2945 if ((addr & 3) || (index > PT_FPSCR)
2946 || (child->thread.regs == NULL))
2949 if ((addr & 7) || (index > PT_FPSCR))
2953 CHECK_FULL_REGS(child->thread.regs);
2954 if (index < PT_FPR0) {
2955 ret = ptrace_put_reg(child, index, data);
2957 unsigned int fpidx = index - PT_FPR0;
2959 flush_fp_to_thread(child);
2960 if (fpidx < (PT_FPSCR - PT_FPR0))
2961 if (IS_ENABLED(CONFIG_PPC32)) {
2962 // On 32-bit the index we are passed refers to 32-bit words
2963 ((u32 *)child->thread.fp_state.fpr)[fpidx] = data;
2965 memcpy(&child->thread.TS_FPR(fpidx), &data,
2969 child->thread.fp_state.fpscr = data;
2975 case PPC_PTRACE_GETHWDBGINFO: {
2976 struct ppc_debug_info dbginfo;
2978 dbginfo.version = 1;
2979 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2980 dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS;
2981 dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS;
2982 dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS;
2983 dbginfo.data_bp_alignment = 4;
2984 dbginfo.sizeof_condition = 4;
2985 dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE |
2986 PPC_DEBUG_FEATURE_INSN_BP_MASK;
2987 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2989 PPC_DEBUG_FEATURE_DATA_BP_RANGE |
2990 PPC_DEBUG_FEATURE_DATA_BP_MASK;
2992 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
2993 dbginfo.num_instruction_bps = 0;
2994 dbginfo.num_data_bps = 1;
2995 dbginfo.num_condition_regs = 0;
2997 dbginfo.data_bp_alignment = 8;
2999 dbginfo.data_bp_alignment = 4;
3001 dbginfo.sizeof_condition = 0;
3002 #ifdef CONFIG_HAVE_HW_BREAKPOINT
3003 dbginfo.features = PPC_DEBUG_FEATURE_DATA_BP_RANGE;
3004 if (cpu_has_feature(CPU_FTR_DAWR))
3005 dbginfo.features |= PPC_DEBUG_FEATURE_DATA_BP_DAWR;
3007 dbginfo.features = 0;
3008 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
3009 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
3011 if (!access_ok(VERIFY_WRITE, datavp,
3012 sizeof(struct ppc_debug_info)))
3014 ret = __copy_to_user(datavp, &dbginfo,
3015 sizeof(struct ppc_debug_info)) ?
3020 case PPC_PTRACE_SETHWDEBUG: {
3021 struct ppc_hw_breakpoint bp_info;
3023 if (!access_ok(VERIFY_READ, datavp,
3024 sizeof(struct ppc_hw_breakpoint)))
3026 ret = __copy_from_user(&bp_info, datavp,
3027 sizeof(struct ppc_hw_breakpoint)) ?
3030 ret = ppc_set_hwdebug(child, &bp_info);
3034 case PPC_PTRACE_DELHWDEBUG: {
3035 ret = ppc_del_hwdebug(child, data);
3039 case PTRACE_GET_DEBUGREG: {
3040 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
3041 unsigned long dabr_fake;
3044 /* We only support one DABR and no IABRS at the moment */
3047 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
3048 ret = put_user(child->thread.debug.dac1, datalp);
3050 dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) |
3051 (child->thread.hw_brk.type & HW_BRK_TYPE_DABR));
3052 ret = put_user(dabr_fake, datalp);
3057 case PTRACE_SET_DEBUGREG:
3058 ret = ptrace_set_debugreg(child, addr, data);
3062 case PTRACE_GETREGS64:
3064 case PTRACE_GETREGS: /* Get all pt_regs from the child. */
3065 return copy_regset_to_user(child, &user_ppc_native_view,
3067 0, sizeof(struct pt_regs),
3071 case PTRACE_SETREGS64:
3073 case PTRACE_SETREGS: /* Set all gp regs in the child. */
3074 return copy_regset_from_user(child, &user_ppc_native_view,
3076 0, sizeof(struct pt_regs),
3079 case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */
3080 return copy_regset_to_user(child, &user_ppc_native_view,
3082 0, sizeof(elf_fpregset_t),
3085 case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */
3086 return copy_regset_from_user(child, &user_ppc_native_view,
3088 0, sizeof(elf_fpregset_t),
3091 #ifdef CONFIG_ALTIVEC
3092 case PTRACE_GETVRREGS:
3093 return copy_regset_to_user(child, &user_ppc_native_view,
3095 0, (33 * sizeof(vector128) +
3099 case PTRACE_SETVRREGS:
3100 return copy_regset_from_user(child, &user_ppc_native_view,
3102 0, (33 * sizeof(vector128) +
3107 case PTRACE_GETVSRREGS:
3108 return copy_regset_to_user(child, &user_ppc_native_view,
3110 0, 32 * sizeof(double),
3113 case PTRACE_SETVSRREGS:
3114 return copy_regset_from_user(child, &user_ppc_native_view,
3116 0, 32 * sizeof(double),
3120 case PTRACE_GETEVRREGS:
3121 /* Get the child spe register state. */
3122 return copy_regset_to_user(child, &user_ppc_native_view,
3123 REGSET_SPE, 0, 35 * sizeof(u32),
3126 case PTRACE_SETEVRREGS:
3127 /* Set the child spe register state. */
3128 return copy_regset_from_user(child, &user_ppc_native_view,
3129 REGSET_SPE, 0, 35 * sizeof(u32),
3134 ret = ptrace_request(child, request, addr, data);
3140 #ifdef CONFIG_SECCOMP
3141 static int do_seccomp(struct pt_regs *regs)
3143 if (!test_thread_flag(TIF_SECCOMP))
3147 * The ABI we present to seccomp tracers is that r3 contains
3148 * the syscall return value and orig_gpr3 contains the first
3149 * syscall parameter. This is different to the ptrace ABI where
3150 * both r3 and orig_gpr3 contain the first syscall parameter.
3152 regs->gpr[3] = -ENOSYS;
3155 * We use the __ version here because we have already checked
3156 * TIF_SECCOMP. If this fails, there is nothing left to do, we
3157 * have already loaded -ENOSYS into r3, or seccomp has put
3158 * something else in r3 (via SECCOMP_RET_ERRNO/TRACE).
3160 if (__secure_computing(NULL))
3164 * The syscall was allowed by seccomp, restore the register
3165 * state to what audit expects.
3166 * Note that we use orig_gpr3, which means a seccomp tracer can
3167 * modify the first syscall parameter (in orig_gpr3) and also
3168 * allow the syscall to proceed.
3170 regs->gpr[3] = regs->orig_gpr3;
3175 static inline int do_seccomp(struct pt_regs *regs) { return 0; }
3176 #endif /* CONFIG_SECCOMP */
3179 * do_syscall_trace_enter() - Do syscall tracing on kernel entry.
3180 * @regs: the pt_regs of the task to trace (current)
3182 * Performs various types of tracing on syscall entry. This includes seccomp,
3183 * ptrace, syscall tracepoints and audit.
3185 * The pt_regs are potentially visible to userspace via ptrace, so their
3188 * One or more of the tracers may modify the contents of pt_regs, in particular
3189 * to modify arguments or even the syscall number itself.
3191 * It's also possible that a tracer can choose to reject the system call. In
3192 * that case this function will return an illegal syscall number, and will put
3193 * an appropriate return value in regs->r3.
3195 * Return: the (possibly changed) syscall number.
3197 long do_syscall_trace_enter(struct pt_regs *regs)
3202 * The tracer may decide to abort the syscall, if so tracehook
3203 * will return !0. Note that the tracer may also just change
3204 * regs->gpr[0] to an invalid syscall number, that is handled
3205 * below on the exit path.
3207 if (test_thread_flag(TIF_SYSCALL_TRACE) &&
3208 tracehook_report_syscall_entry(regs))
3211 /* Run seccomp after ptrace; allow it to set gpr[3]. */
3212 if (do_seccomp(regs))
3215 /* Avoid trace and audit when syscall is invalid. */
3216 if (regs->gpr[0] >= NR_syscalls)
3219 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
3220 trace_sys_enter(regs, regs->gpr[0]);
3223 if (!is_32bit_task())
3224 audit_syscall_entry(regs->gpr[0], regs->gpr[3], regs->gpr[4],
3225 regs->gpr[5], regs->gpr[6]);
3228 audit_syscall_entry(regs->gpr[0],
3229 regs->gpr[3] & 0xffffffff,
3230 regs->gpr[4] & 0xffffffff,
3231 regs->gpr[5] & 0xffffffff,
3232 regs->gpr[6] & 0xffffffff);
3234 /* Return the possibly modified but valid syscall number */
3235 return regs->gpr[0];
3239 * If we are aborting explicitly, or if the syscall number is
3240 * now invalid, set the return value to -ENOSYS.
3242 regs->gpr[3] = -ENOSYS;
3246 void do_syscall_trace_leave(struct pt_regs *regs)
3250 audit_syscall_exit(regs);
3252 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
3253 trace_sys_exit(regs, regs->result);
3255 step = test_thread_flag(TIF_SINGLESTEP);
3256 if (step || test_thread_flag(TIF_SYSCALL_TRACE))
3257 tracehook_report_syscall_exit(regs, step);