2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
28 #include <linux/shmem_fs.h>
29 #include <linux/list.h>
30 #include <linux/syscalls.h>
31 #include <linux/irq.h>
32 #include <linux/vmalloc.h>
33 #include <linux/slab.h>
34 #include <linux/vgaarb.h>
36 #include <asm/processor.h>
39 #include <asm/pci-bridge.h>
40 #include <asm/byteorder.h>
41 #include <asm/machdep.h>
42 #include <asm/ppc-pci.h>
45 /* hose_spinlock protects accesses to the the phb_bitmap. */
46 static DEFINE_SPINLOCK(hose_spinlock);
49 /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
50 #define MAX_PHBS 0x10000
53 * For dynamic PHB numbering: used/free PHBs tracking bitmap.
54 * Accesses to this bitmap should be protected by hose_spinlock.
56 static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
58 /* ISA Memory physical address */
59 resource_size_t isa_mem_base;
60 EXPORT_SYMBOL(isa_mem_base);
63 static const struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
65 void set_pci_dma_ops(const struct dma_map_ops *dma_ops)
67 pci_dma_ops = dma_ops;
70 const struct dma_map_ops *get_pci_dma_ops(void)
74 EXPORT_SYMBOL(get_pci_dma_ops);
76 static int get_phb_number(struct device_node *dn)
82 * Try fixed PHB numbering first, by checking archs and reading
83 * the respective device-tree properties. Firstly, try reading
84 * standard "linux,pci-domain", then try reading "ibm,opal-phbid"
85 * (only present in powernv OPAL environment), then try device-tree
86 * alias and as the last try to use lower bits of "reg" property.
88 ret = of_get_pci_domain_nr(dn);
94 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
97 ret = of_alias_get_id(dn, "pci");
105 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
110 phb_id = (int)(prop & (MAX_PHBS - 1));
112 spin_lock(&hose_spinlock);
114 /* We need to be sure to not use the same PHB number twice. */
115 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
118 /* If everything fails then fallback to dynamic PHB numbering. */
119 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
120 BUG_ON(phb_id >= MAX_PHBS);
121 set_bit(phb_id, phb_bitmap);
124 spin_unlock(&hose_spinlock);
129 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
131 struct pci_controller *phb;
133 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
137 phb->global_number = get_phb_number(dev);
139 spin_lock(&hose_spinlock);
140 list_add_tail(&phb->list_node, &hose_list);
141 spin_unlock(&hose_spinlock);
144 phb->is_dynamic = slab_is_available();
147 int nid = of_node_to_nid(dev);
149 if (nid < 0 || !node_online(nid))
152 PHB_SET_NODE(phb, nid);
157 EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
159 void pcibios_free_controller(struct pci_controller *phb)
161 spin_lock(&hose_spinlock);
163 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */
164 if (phb->global_number < MAX_PHBS)
165 clear_bit(phb->global_number, phb_bitmap);
167 list_del(&phb->list_node);
168 spin_unlock(&hose_spinlock);
173 EXPORT_SYMBOL_GPL(pcibios_free_controller);
176 * This function is used to call pcibios_free_controller()
177 * in a deferred manner: a callback from the PCI subsystem.
179 * _*DO NOT*_ call pcibios_free_controller() explicitly if
180 * this is used (or it may access an invalid *phb pointer).
182 * The callback occurs when all references to the root bus
183 * are dropped (e.g., child buses/devices and their users).
185 * It's called as .release_fn() of 'struct pci_host_bridge'
186 * which is associated with the 'struct pci_controller.bus'
187 * (root bus) - it expects .release_data to hold a pointer
188 * to 'struct pci_controller'.
190 * In order to use it, register .release_fn()/release_data
193 * pci_set_host_bridge_release(bridge,
194 * pcibios_free_controller_deferred
197 * e.g. in the pcibios_root_bridge_prepare() callback from
198 * pci_create_root_bus().
200 void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
202 struct pci_controller *phb = (struct pci_controller *)
203 bridge->release_data;
205 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
207 pcibios_free_controller(phb);
209 EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
212 * The function is used to return the minimal alignment
213 * for memory or I/O windows of the associated P2P bridge.
214 * By default, 4KiB alignment for I/O windows and 1MiB for
217 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
220 struct pci_controller *phb = pci_bus_to_host(bus);
222 if (phb->controller_ops.window_alignment)
223 return phb->controller_ops.window_alignment(bus, type);
226 * PCI core will figure out the default
227 * alignment: 4KiB for I/O and 1MiB for
233 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
235 struct pci_controller *hose = pci_bus_to_host(bus);
237 if (hose->controller_ops.setup_bridge)
238 hose->controller_ops.setup_bridge(bus, type);
241 void pcibios_reset_secondary_bus(struct pci_dev *dev)
243 struct pci_controller *phb = pci_bus_to_host(dev->bus);
245 if (phb->controller_ops.reset_secondary_bus) {
246 phb->controller_ops.reset_secondary_bus(dev);
250 pci_reset_secondary_bus(dev);
253 resource_size_t pcibios_default_alignment(void)
255 if (ppc_md.pcibios_default_alignment)
256 return ppc_md.pcibios_default_alignment();
261 #ifdef CONFIG_PCI_IOV
262 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
264 if (ppc_md.pcibios_iov_resource_alignment)
265 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
267 return pci_iov_resource_size(pdev, resno);
269 #endif /* CONFIG_PCI_IOV */
271 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
274 return hose->pci_io_size;
276 return resource_size(&hose->io_resource);
280 int pcibios_vaddr_is_ioport(void __iomem *address)
283 struct pci_controller *hose;
284 resource_size_t size;
286 spin_lock(&hose_spinlock);
287 list_for_each_entry(hose, &hose_list, list_node) {
288 size = pcibios_io_size(hose);
289 if (address >= hose->io_base_virt &&
290 address < (hose->io_base_virt + size)) {
295 spin_unlock(&hose_spinlock);
299 unsigned long pci_address_to_pio(phys_addr_t address)
301 struct pci_controller *hose;
302 resource_size_t size;
303 unsigned long ret = ~0;
305 spin_lock(&hose_spinlock);
306 list_for_each_entry(hose, &hose_list, list_node) {
307 size = pcibios_io_size(hose);
308 if (address >= hose->io_base_phys &&
309 address < (hose->io_base_phys + size)) {
311 (unsigned long)hose->io_base_virt - _IO_BASE;
312 ret = base + (address - hose->io_base_phys);
316 spin_unlock(&hose_spinlock);
320 EXPORT_SYMBOL_GPL(pci_address_to_pio);
323 * Return the domain number for this bus.
325 int pci_domain_nr(struct pci_bus *bus)
327 struct pci_controller *hose = pci_bus_to_host(bus);
329 return hose->global_number;
331 EXPORT_SYMBOL(pci_domain_nr);
333 /* This routine is meant to be used early during boot, when the
334 * PCI bus numbers have not yet been assigned, and you need to
335 * issue PCI config cycles to an OF device.
336 * It could also be used to "fix" RTAS config cycles if you want
337 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
340 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
343 struct pci_controller *hose, *tmp;
344 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
345 if (hose->dn == node)
353 * Reads the interrupt pin to determine if interrupt is use by card.
354 * If the interrupt is used, then gets the interrupt line from the
355 * openfirmware and sets it in the pci_dev and pci_config line.
357 static int pci_read_irq_line(struct pci_dev *pci_dev)
359 struct of_phandle_args oirq;
362 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
365 memset(&oirq, 0xff, sizeof(oirq));
367 /* Try to get a mapping from the device-tree */
368 if (of_irq_parse_pci(pci_dev, &oirq)) {
371 /* If that fails, lets fallback to what is in the config
372 * space and map that through the default controller. We
373 * also set the type to level low since that's what PCI
374 * interrupts are. If your platform does differently, then
375 * either provide a proper interrupt tree or don't use this
378 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
382 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
383 line == 0xff || line == 0) {
386 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
389 virq = irq_create_mapping(NULL, line);
391 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
393 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %pOF\n",
394 oirq.args_count, oirq.args[0], oirq.args[1], oirq.np);
396 virq = irq_create_of_mapping(&oirq);
400 pr_debug(" Failed to map !\n");
404 pr_debug(" Mapped to linux irq %d\n", virq);
412 * Platform support for /proc/bus/pci/X/Y mmap()s,
413 * modelled on the sparc64 implementation by Dave Miller.
418 * Adjust vm_pgoff of VMA such that it is the physical page offset
419 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
421 * Basically, the user finds the base address for his device which he wishes
422 * to mmap. They read the 32-bit value from the config space base register,
423 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
424 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
426 * Returns negative error code on failure, zero on success.
428 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
429 resource_size_t *offset,
430 enum pci_mmap_state mmap_state)
432 struct pci_controller *hose = pci_bus_to_host(dev->bus);
433 unsigned long io_offset = 0;
437 return NULL; /* should never happen */
439 /* If memory, add on the PCI bridge address offset */
440 if (mmap_state == pci_mmap_mem) {
441 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
442 *offset += hose->pci_mem_offset;
444 res_bit = IORESOURCE_MEM;
446 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
447 *offset += io_offset;
448 res_bit = IORESOURCE_IO;
452 * Check that the offset requested corresponds to one of the
453 * resources of the device.
455 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
456 struct resource *rp = &dev->resource[i];
457 int flags = rp->flags;
459 /* treat ROM as memory (should be already) */
460 if (i == PCI_ROM_RESOURCE)
461 flags |= IORESOURCE_MEM;
463 /* Active and same type? */
464 if ((flags & res_bit) == 0)
467 /* In the range of this resource? */
468 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
471 /* found it! construct the final physical address */
472 if (mmap_state == pci_mmap_io)
473 *offset += hose->io_base_phys - io_offset;
481 * This one is used by /dev/mem and fbdev who have no clue about the
482 * PCI device, it tries to find the PCI device first and calls the
485 pgprot_t pci_phys_mem_access_prot(struct file *file,
490 struct pci_dev *pdev = NULL;
491 struct resource *found = NULL;
492 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
495 if (page_is_ram(pfn))
498 prot = pgprot_noncached(prot);
499 for_each_pci_dev(pdev) {
500 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
501 struct resource *rp = &pdev->resource[i];
502 int flags = rp->flags;
504 /* Active and same type? */
505 if ((flags & IORESOURCE_MEM) == 0)
507 /* In the range of this resource? */
508 if (offset < (rp->start & PAGE_MASK) ||
518 if (found->flags & IORESOURCE_PREFETCH)
519 prot = pgprot_noncached_wc(prot);
523 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
524 (unsigned long long)offset, pgprot_val(prot));
531 * Perform the actual remap of the pages for a PCI device mapping, as
532 * appropriate for this architecture. The region in the process to map
533 * is described by vm_start and vm_end members of VMA, the base physical
534 * address is found in vm_pgoff.
535 * The pci device structure is provided so that architectures may make mapping
536 * decisions on a per-device or per-bus basis.
538 * Returns a negative error code on failure, zero on success.
540 int pci_mmap_page_range(struct pci_dev *dev, int bar,
541 struct vm_area_struct *vma,
542 enum pci_mmap_state mmap_state, int write_combine)
544 resource_size_t offset =
545 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
549 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
553 vma->vm_pgoff = offset >> PAGE_SHIFT;
555 vma->vm_page_prot = pgprot_noncached_wc(vma->vm_page_prot);
557 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
559 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
560 vma->vm_end - vma->vm_start, vma->vm_page_prot);
565 /* This provides legacy IO read access on a bus */
566 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
568 unsigned long offset;
569 struct pci_controller *hose = pci_bus_to_host(bus);
570 struct resource *rp = &hose->io_resource;
573 /* Check if port can be supported by that bus. We only check
574 * the ranges of the PHB though, not the bus itself as the rules
575 * for forwarding legacy cycles down bridges are not our problem
576 * here. So if the host bridge supports it, we do it.
578 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
581 if (!(rp->flags & IORESOURCE_IO))
583 if (offset < rp->start || (offset + size) > rp->end)
585 addr = hose->io_base_virt + port;
589 *((u8 *)val) = in_8(addr);
594 *((u16 *)val) = in_le16(addr);
599 *((u32 *)val) = in_le32(addr);
605 /* This provides legacy IO write access on a bus */
606 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
608 unsigned long offset;
609 struct pci_controller *hose = pci_bus_to_host(bus);
610 struct resource *rp = &hose->io_resource;
613 /* Check if port can be supported by that bus. We only check
614 * the ranges of the PHB though, not the bus itself as the rules
615 * for forwarding legacy cycles down bridges are not our problem
616 * here. So if the host bridge supports it, we do it.
618 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
621 if (!(rp->flags & IORESOURCE_IO))
623 if (offset < rp->start || (offset + size) > rp->end)
625 addr = hose->io_base_virt + port;
627 /* WARNING: The generic code is idiotic. It gets passed a pointer
628 * to what can be a 1, 2 or 4 byte quantity and always reads that
629 * as a u32, which means that we have to correct the location of
630 * the data read within those 32 bits for size 1 and 2
634 out_8(addr, val >> 24);
639 out_le16(addr, val >> 16);
650 /* This provides legacy IO or memory mmap access on a bus */
651 int pci_mmap_legacy_page_range(struct pci_bus *bus,
652 struct vm_area_struct *vma,
653 enum pci_mmap_state mmap_state)
655 struct pci_controller *hose = pci_bus_to_host(bus);
656 resource_size_t offset =
657 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
658 resource_size_t size = vma->vm_end - vma->vm_start;
661 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
662 pci_domain_nr(bus), bus->number,
663 mmap_state == pci_mmap_mem ? "MEM" : "IO",
664 (unsigned long long)offset,
665 (unsigned long long)(offset + size - 1));
667 if (mmap_state == pci_mmap_mem) {
670 * Because X is lame and can fail starting if it gets an error trying
671 * to mmap legacy_mem (instead of just moving on without legacy memory
672 * access) we fake it here by giving it anonymous memory, effectively
673 * behaving just like /dev/zero
675 if ((offset + size) > hose->isa_mem_size) {
677 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
678 current->comm, current->pid, pci_domain_nr(bus), bus->number);
679 if (vma->vm_flags & VM_SHARED)
680 return shmem_zero_setup(vma);
683 offset += hose->isa_mem_phys;
685 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
686 unsigned long roffset = offset + io_offset;
687 rp = &hose->io_resource;
688 if (!(rp->flags & IORESOURCE_IO))
690 if (roffset < rp->start || (roffset + size) > rp->end)
692 offset += hose->io_base_phys;
694 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
696 vma->vm_pgoff = offset >> PAGE_SHIFT;
697 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
698 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
699 vma->vm_end - vma->vm_start,
703 void pci_resource_to_user(const struct pci_dev *dev, int bar,
704 const struct resource *rsrc,
705 resource_size_t *start, resource_size_t *end)
707 struct pci_bus_region region;
709 if (rsrc->flags & IORESOURCE_IO) {
710 pcibios_resource_to_bus(dev->bus, ®ion,
711 (struct resource *) rsrc);
712 *start = region.start;
717 /* We pass a CPU physical address to userland for MMIO instead of a
718 * BAR value because X is lame and expects to be able to use that
719 * to pass to /dev/mem!
721 * That means we may have 64-bit values where some apps only expect
722 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
724 *start = rsrc->start;
729 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
730 * @hose: newly allocated pci_controller to be setup
731 * @dev: device node of the host bridge
732 * @primary: set if primary bus (32 bits only, soon to be deprecated)
734 * This function will parse the "ranges" property of a PCI host bridge device
735 * node and setup the resource mapping of a pci controller based on its
738 * Life would be boring if it wasn't for a few issues that we have to deal
741 * - We can only cope with one IO space range and up to 3 Memory space
742 * ranges. However, some machines (thanks Apple !) tend to split their
743 * space into lots of small contiguous ranges. So we have to coalesce.
745 * - Some busses have IO space not starting at 0, which causes trouble with
746 * the way we do our IO resource renumbering. The code somewhat deals with
747 * it for 64 bits but I would expect problems on 32 bits.
749 * - Some 32 bits platforms such as 4xx can have physical space larger than
750 * 32 bits so we need to use 64 bits values for the parsing
752 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
753 struct device_node *dev, int primary)
756 struct resource *res;
757 struct of_pci_range range;
758 struct of_pci_range_parser parser;
760 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n",
761 dev, primary ? "(primary)" : "");
763 /* Check for ranges property */
764 if (of_pci_range_parser_init(&parser, dev))
768 for_each_of_pci_range(&parser, &range) {
769 /* If we failed translation or got a zero-sized region
770 * (some FW try to feed us with non sensical zero sized regions
771 * such as power3 which look like some kind of attempt at exposing
772 * the VGA memory hole)
774 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
777 /* Act based on address space type */
779 switch (range.flags & IORESOURCE_TYPE_BITS) {
782 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
783 range.cpu_addr, range.cpu_addr + range.size - 1,
786 /* We support only one IO range */
787 if (hose->pci_io_size) {
789 " \\--> Skipped (too many) !\n");
793 /* On 32 bits, limit I/O space to 16MB */
794 if (range.size > 0x01000000)
795 range.size = 0x01000000;
797 /* 32 bits needs to map IOs here */
798 hose->io_base_virt = ioremap(range.cpu_addr,
801 /* Expect trouble if pci_addr is not 0 */
804 (unsigned long)hose->io_base_virt;
805 #endif /* CONFIG_PPC32 */
806 /* pci_io_size and io_base_phys always represent IO
807 * space starting at 0 so we factor in pci_addr
809 hose->pci_io_size = range.pci_addr + range.size;
810 hose->io_base_phys = range.cpu_addr - range.pci_addr;
813 res = &hose->io_resource;
814 range.cpu_addr = range.pci_addr;
818 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
819 range.cpu_addr, range.cpu_addr + range.size - 1,
821 (range.pci_space & 0x40000000) ?
824 /* We support only 3 memory ranges */
827 " \\--> Skipped (too many) !\n");
830 /* Handles ISA memory hole space here */
831 if (range.pci_addr == 0) {
832 if (primary || isa_mem_base == 0)
833 isa_mem_base = range.cpu_addr;
834 hose->isa_mem_phys = range.cpu_addr;
835 hose->isa_mem_size = range.size;
839 hose->mem_offset[memno] = range.cpu_addr -
841 res = &hose->mem_resources[memno++];
845 res->name = dev->full_name;
846 res->flags = range.flags;
847 res->start = range.cpu_addr;
848 res->end = range.cpu_addr + range.size - 1;
849 res->parent = res->child = res->sibling = NULL;
854 /* Decide whether to display the domain number in /proc */
855 int pci_proc_domain(struct pci_bus *bus)
857 struct pci_controller *hose = pci_bus_to_host(bus);
859 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
861 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
862 return hose->global_number != 0;
866 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
868 if (ppc_md.pcibios_root_bridge_prepare)
869 return ppc_md.pcibios_root_bridge_prepare(bridge);
874 /* This header fixup will do the resource fixup for all devices as they are
875 * probed, but not for bridge ranges
877 static void pcibios_fixup_resources(struct pci_dev *dev)
879 struct pci_controller *hose = pci_bus_to_host(dev->bus);
883 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
891 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
892 struct resource *res = dev->resource + i;
893 struct pci_bus_region reg;
897 /* If we're going to re-assign everything, we mark all resources
898 * as unset (and 0-base them). In addition, we mark BARs starting
899 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
900 * since in that case, we don't want to re-assign anything
902 pcibios_resource_to_bus(dev->bus, ®, res);
903 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
904 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
905 /* Only print message if not re-assigning */
906 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
907 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
908 pci_name(dev), i, res);
909 res->end -= res->start;
911 res->flags |= IORESOURCE_UNSET;
915 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
918 /* Call machine specific resource fixup */
919 if (ppc_md.pcibios_fixup_resources)
920 ppc_md.pcibios_fixup_resources(dev);
922 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
924 /* This function tries to figure out if a bridge resource has been initialized
925 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
926 * things go more smoothly when it gets it right. It should covers cases such
927 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
929 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
930 struct resource *res)
932 struct pci_controller *hose = pci_bus_to_host(bus);
933 struct pci_dev *dev = bus->self;
934 resource_size_t offset;
935 struct pci_bus_region region;
939 /* We don't do anything if PCI_PROBE_ONLY is set */
940 if (pci_has_flag(PCI_PROBE_ONLY))
943 /* Job is a bit different between memory and IO */
944 if (res->flags & IORESOURCE_MEM) {
945 pcibios_resource_to_bus(dev->bus, ®ion, res);
947 /* If the BAR is non-0 then it's probably been initialized */
948 if (region.start != 0)
951 /* The BAR is 0, let's check if memory decoding is enabled on
952 * the bridge. If not, we consider it unassigned
954 pci_read_config_word(dev, PCI_COMMAND, &command);
955 if ((command & PCI_COMMAND_MEMORY) == 0)
958 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
959 * resources covers that starting address (0 then it's good enough for
960 * us for memory space)
962 for (i = 0; i < 3; i++) {
963 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
964 hose->mem_resources[i].start == hose->mem_offset[i])
968 /* Well, it starts at 0 and we know it will collide so we may as
969 * well consider it as unassigned. That covers the Apple case.
973 /* If the BAR is non-0, then we consider it assigned */
974 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
975 if (((res->start - offset) & 0xfffffffful) != 0)
978 /* Here, we are a bit different than memory as typically IO space
979 * starting at low addresses -is- valid. What we do instead if that
980 * we consider as unassigned anything that doesn't have IO enabled
981 * in the PCI command register, and that's it.
983 pci_read_config_word(dev, PCI_COMMAND, &command);
984 if (command & PCI_COMMAND_IO)
987 /* It's starting at 0 and IO is disabled in the bridge, consider
994 /* Fixup resources of a PCI<->PCI bridge */
995 static void pcibios_fixup_bridge(struct pci_bus *bus)
997 struct resource *res;
1000 struct pci_dev *dev = bus->self;
1002 pci_bus_for_each_resource(bus, res, i) {
1003 if (!res || !res->flags)
1005 if (i >= 3 && bus->self->transparent)
1008 /* If we're going to reassign everything, we can
1009 * shrink the P2P resource to have size as being
1010 * of 0 in order to save space.
1012 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1013 res->flags |= IORESOURCE_UNSET;
1019 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
1021 /* Try to detect uninitialized P2P bridge resources,
1022 * and clear them out so they get re-assigned later
1024 if (pcibios_uninitialized_bridge_resource(bus, res)) {
1026 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
1031 void pcibios_setup_bus_self(struct pci_bus *bus)
1033 struct pci_controller *phb;
1035 /* Fix up the bus resources for P2P bridges */
1036 if (bus->self != NULL)
1037 pcibios_fixup_bridge(bus);
1039 /* Platform specific bus fixups. This is currently only used
1040 * by fsl_pci and I'm hoping to get rid of it at some point
1042 if (ppc_md.pcibios_fixup_bus)
1043 ppc_md.pcibios_fixup_bus(bus);
1045 /* Setup bus DMA mappings */
1046 phb = pci_bus_to_host(bus);
1047 if (phb->controller_ops.dma_bus_setup)
1048 phb->controller_ops.dma_bus_setup(bus);
1051 static void pcibios_setup_device(struct pci_dev *dev)
1053 struct pci_controller *phb;
1054 /* Fixup NUMA node as it may not be setup yet by the generic
1055 * code and is needed by the DMA init
1057 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1059 /* Hook up default DMA ops */
1060 set_dma_ops(&dev->dev, pci_dma_ops);
1061 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
1063 /* Additional platform DMA/iommu setup */
1064 phb = pci_bus_to_host(dev->bus);
1065 if (phb->controller_ops.dma_dev_setup)
1066 phb->controller_ops.dma_dev_setup(dev);
1068 /* Read default IRQs and fixup if necessary */
1069 pci_read_irq_line(dev);
1070 if (ppc_md.pci_irq_fixup)
1071 ppc_md.pci_irq_fixup(dev);
1074 int pcibios_add_device(struct pci_dev *dev)
1077 * We can only call pcibios_setup_device() after bus setup is complete,
1078 * since some of the platform specific DMA setup code depends on it.
1080 if (dev->bus->is_added)
1081 pcibios_setup_device(dev);
1083 #ifdef CONFIG_PCI_IOV
1084 if (ppc_md.pcibios_fixup_sriov)
1085 ppc_md.pcibios_fixup_sriov(dev);
1086 #endif /* CONFIG_PCI_IOV */
1091 void pcibios_setup_bus_devices(struct pci_bus *bus)
1093 struct pci_dev *dev;
1095 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1096 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1098 list_for_each_entry(dev, &bus->devices, bus_list) {
1099 /* Cardbus can call us to add new devices to a bus, so ignore
1100 * those who are already fully discovered
1105 pcibios_setup_device(dev);
1109 void pcibios_set_master(struct pci_dev *dev)
1111 /* No special bus mastering setup handling */
1114 void pcibios_fixup_bus(struct pci_bus *bus)
1116 /* When called from the generic PCI probe, read PCI<->PCI bridge
1117 * bases. This is -not- called when generating the PCI tree from
1118 * the OF device-tree.
1120 pci_read_bridge_bases(bus);
1122 /* Now fixup the bus bus */
1123 pcibios_setup_bus_self(bus);
1125 /* Now fixup devices on that bus */
1126 pcibios_setup_bus_devices(bus);
1128 EXPORT_SYMBOL(pcibios_fixup_bus);
1130 void pci_fixup_cardbus(struct pci_bus *bus)
1132 /* Now fixup devices on that bus */
1133 pcibios_setup_bus_devices(bus);
1137 static int skip_isa_ioresource_align(struct pci_dev *dev)
1139 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1140 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1146 * We need to avoid collisions with `mirrored' VGA ports
1147 * and other strange ISA hardware, so we always want the
1148 * addresses to be allocated in the 0x000-0x0ff region
1151 * Why? Because some silly external IO cards only decode
1152 * the low 10 bits of the IO address. The 0x00-0xff region
1153 * is reserved for motherboard devices that decode all 16
1154 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1155 * but we want to try to avoid allocating at 0x2900-0x2bff
1156 * which might have be mirrored at 0x0100-0x03ff..
1158 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1159 resource_size_t size, resource_size_t align)
1161 struct pci_dev *dev = data;
1162 resource_size_t start = res->start;
1164 if (res->flags & IORESOURCE_IO) {
1165 if (skip_isa_ioresource_align(dev))
1168 start = (start + 0x3ff) & ~0x3ff;
1173 EXPORT_SYMBOL(pcibios_align_resource);
1176 * Reparent resource children of pr that conflict with res
1177 * under res, and make res replace those children.
1179 static int reparent_resources(struct resource *parent,
1180 struct resource *res)
1182 struct resource *p, **pp;
1183 struct resource **firstpp = NULL;
1185 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1186 if (p->end < res->start)
1188 if (res->end < p->start)
1190 if (p->start < res->start || p->end > res->end)
1191 return -1; /* not completely contained */
1192 if (firstpp == NULL)
1195 if (firstpp == NULL)
1196 return -1; /* didn't find any conflicting entries? */
1197 res->parent = parent;
1198 res->child = *firstpp;
1202 for (p = res->child; p != NULL; p = p->sibling) {
1204 pr_debug("PCI: Reparented %s %pR under %s\n",
1205 p->name, p, res->name);
1211 * Handle resources of PCI devices. If the world were perfect, we could
1212 * just allocate all the resource regions and do nothing more. It isn't.
1213 * On the other hand, we cannot just re-allocate all devices, as it would
1214 * require us to know lots of host bridge internals. So we attempt to
1215 * keep as much of the original configuration as possible, but tweak it
1216 * when it's found to be wrong.
1218 * Known BIOS problems we have to work around:
1219 * - I/O or memory regions not configured
1220 * - regions configured, but not enabled in the command register
1221 * - bogus I/O addresses above 64K used
1222 * - expansion ROMs left enabled (this may sound harmless, but given
1223 * the fact the PCI specs explicitly allow address decoders to be
1224 * shared between expansion ROMs and other resource regions, it's
1225 * at least dangerous)
1228 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1229 * This gives us fixed barriers on where we can allocate.
1230 * (2) Allocate resources for all enabled devices. If there is
1231 * a collision, just mark the resource as unallocated. Also
1232 * disable expansion ROMs during this step.
1233 * (3) Try to allocate resources for disabled devices. If the
1234 * resources were assigned correctly, everything goes well,
1235 * if they weren't, they won't disturb allocation of other
1237 * (4) Assign new addresses to resources which were either
1238 * not configured at all or misconfigured. If explicitly
1239 * requested by the user, configure expansion ROM address
1243 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1247 struct resource *res, *pr;
1249 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1250 pci_domain_nr(bus), bus->number);
1252 pci_bus_for_each_resource(bus, res, i) {
1253 if (!res || !res->flags || res->start > res->end || res->parent)
1256 /* If the resource was left unset at this point, we clear it */
1257 if (res->flags & IORESOURCE_UNSET)
1258 goto clear_resource;
1260 if (bus->parent == NULL)
1261 pr = (res->flags & IORESOURCE_IO) ?
1262 &ioport_resource : &iomem_resource;
1264 pr = pci_find_parent_resource(bus->self, res);
1266 /* this happens when the generic PCI
1267 * code (wrongly) decides that this
1268 * bridge is transparent -- paulus
1274 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1275 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1276 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1278 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1279 struct pci_dev *dev = bus->self;
1281 if (request_resource(pr, res) == 0)
1284 * Must be a conflict with an existing entry.
1285 * Move that entry (or entries) under the
1286 * bridge resource and try again.
1288 if (reparent_resources(pr, res) == 0)
1291 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1292 pci_claim_bridge_resource(dev,
1293 i + PCI_BRIDGE_RESOURCES) == 0)
1296 pr_warning("PCI: Cannot allocate resource region "
1297 "%d of PCI bridge %d, will remap\n", i, bus->number);
1299 /* The resource might be figured out when doing
1300 * reassignment based on the resources required
1301 * by the downstream PCI devices. Here we set
1302 * the size of the resource to be 0 in order to
1310 list_for_each_entry(b, &bus->children, node)
1311 pcibios_allocate_bus_resources(b);
1314 static inline void alloc_resource(struct pci_dev *dev, int idx)
1316 struct resource *pr, *r = &dev->resource[idx];
1318 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1319 pci_name(dev), idx, r);
1321 pr = pci_find_parent_resource(dev, r);
1322 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1323 request_resource(pr, r) < 0) {
1324 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1325 " of device %s, will remap\n", idx, pci_name(dev));
1327 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1328 /* We'll assign a new address later */
1329 r->flags |= IORESOURCE_UNSET;
1335 static void __init pcibios_allocate_resources(int pass)
1337 struct pci_dev *dev = NULL;
1342 for_each_pci_dev(dev) {
1343 pci_read_config_word(dev, PCI_COMMAND, &command);
1344 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1345 r = &dev->resource[idx];
1346 if (r->parent) /* Already allocated */
1348 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1349 continue; /* Not assigned at all */
1350 /* We only allocate ROMs on pass 1 just in case they
1351 * have been screwed up by firmware
1353 if (idx == PCI_ROM_RESOURCE )
1355 if (r->flags & IORESOURCE_IO)
1356 disabled = !(command & PCI_COMMAND_IO);
1358 disabled = !(command & PCI_COMMAND_MEMORY);
1359 if (pass == disabled)
1360 alloc_resource(dev, idx);
1364 r = &dev->resource[PCI_ROM_RESOURCE];
1366 /* Turn the ROM off, leave the resource region,
1367 * but keep it unregistered.
1370 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1371 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1372 pr_debug("PCI: Switching off ROM of %s\n",
1374 r->flags &= ~IORESOURCE_ROM_ENABLE;
1375 pci_write_config_dword(dev, dev->rom_base_reg,
1376 reg & ~PCI_ROM_ADDRESS_ENABLE);
1382 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1384 struct pci_controller *hose = pci_bus_to_host(bus);
1385 resource_size_t offset;
1386 struct resource *res, *pres;
1389 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1392 if (!(hose->io_resource.flags & IORESOURCE_IO))
1394 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1395 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1396 BUG_ON(res == NULL);
1397 res->name = "Legacy IO";
1398 res->flags = IORESOURCE_IO;
1399 res->start = offset;
1400 res->end = (offset + 0xfff) & 0xfffffffful;
1401 pr_debug("Candidate legacy IO: %pR\n", res);
1402 if (request_resource(&hose->io_resource, res)) {
1404 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1405 pci_domain_nr(bus), bus->number, res);
1410 /* Check for memory */
1411 for (i = 0; i < 3; i++) {
1412 pres = &hose->mem_resources[i];
1413 offset = hose->mem_offset[i];
1414 if (!(pres->flags & IORESOURCE_MEM))
1416 pr_debug("hose mem res: %pR\n", pres);
1417 if ((pres->start - offset) <= 0xa0000 &&
1418 (pres->end - offset) >= 0xbffff)
1423 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1424 BUG_ON(res == NULL);
1425 res->name = "Legacy VGA memory";
1426 res->flags = IORESOURCE_MEM;
1427 res->start = 0xa0000 + offset;
1428 res->end = 0xbffff + offset;
1429 pr_debug("Candidate VGA memory: %pR\n", res);
1430 if (request_resource(pres, res)) {
1432 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1433 pci_domain_nr(bus), bus->number, res);
1438 void __init pcibios_resource_survey(void)
1442 /* Allocate and assign resources */
1443 list_for_each_entry(b, &pci_root_buses, node)
1444 pcibios_allocate_bus_resources(b);
1445 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1446 pcibios_allocate_resources(0);
1447 pcibios_allocate_resources(1);
1450 /* Before we start assigning unassigned resource, we try to reserve
1451 * the low IO area and the VGA memory area if they intersect the
1452 * bus available resources to avoid allocating things on top of them
1454 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1455 list_for_each_entry(b, &pci_root_buses, node)
1456 pcibios_reserve_legacy_regions(b);
1459 /* Now, if the platform didn't decide to blindly trust the firmware,
1460 * we proceed to assigning things that were left unassigned
1462 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1463 pr_debug("PCI: Assigning unassigned resources...\n");
1464 pci_assign_unassigned_resources();
1467 /* Call machine dependent fixup */
1468 if (ppc_md.pcibios_fixup)
1469 ppc_md.pcibios_fixup();
1472 /* This is used by the PCI hotplug driver to allocate resource
1473 * of newly plugged busses. We can try to consolidate with the
1474 * rest of the code later, for now, keep it as-is as our main
1475 * resource allocation function doesn't deal with sub-trees yet.
1477 void pcibios_claim_one_bus(struct pci_bus *bus)
1479 struct pci_dev *dev;
1480 struct pci_bus *child_bus;
1482 list_for_each_entry(dev, &bus->devices, bus_list) {
1485 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1486 struct resource *r = &dev->resource[i];
1488 if (r->parent || !r->start || !r->flags)
1491 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1492 pci_name(dev), i, r);
1494 if (pci_claim_resource(dev, i) == 0)
1497 pci_claim_bridge_resource(dev, i);
1501 list_for_each_entry(child_bus, &bus->children, node)
1502 pcibios_claim_one_bus(child_bus);
1504 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1507 /* pcibios_finish_adding_to_bus
1509 * This is to be called by the hotplug code after devices have been
1510 * added to a bus, this include calling it for a PHB that is just
1513 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1515 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1516 pci_domain_nr(bus), bus->number);
1518 /* Allocate bus and devices resources */
1519 pcibios_allocate_bus_resources(bus);
1520 pcibios_claim_one_bus(bus);
1521 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1523 pci_assign_unassigned_bridge_resources(bus->self);
1525 pci_assign_unassigned_bus_resources(bus);
1529 eeh_add_device_tree_late(bus);
1531 /* Add new devices to global lists. Register in proc, sysfs. */
1532 pci_bus_add_devices(bus);
1534 /* sysfs files should only be added after devices are added */
1535 eeh_add_sysfs_files(bus);
1537 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1539 int pcibios_enable_device(struct pci_dev *dev, int mask)
1541 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1543 if (phb->controller_ops.enable_device_hook)
1544 if (!phb->controller_ops.enable_device_hook(dev))
1547 return pci_enable_resources(dev, mask);
1550 void pcibios_disable_device(struct pci_dev *dev)
1552 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1554 if (phb->controller_ops.disable_device)
1555 phb->controller_ops.disable_device(dev);
1558 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1560 return (unsigned long) hose->io_base_virt - _IO_BASE;
1563 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1564 struct list_head *resources)
1566 struct resource *res;
1567 resource_size_t offset;
1570 /* Hookup PHB IO resource */
1571 res = &hose->io_resource;
1574 pr_debug("PCI: I/O resource not set for host"
1575 " bridge %pOF (domain %d)\n",
1576 hose->dn, hose->global_number);
1578 offset = pcibios_io_space_offset(hose);
1580 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1581 res, (unsigned long long)offset);
1582 pci_add_resource_offset(resources, res, offset);
1585 /* Hookup PHB Memory resources */
1586 for (i = 0; i < 3; ++i) {
1587 res = &hose->mem_resources[i];
1591 offset = hose->mem_offset[i];
1592 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1593 res, (unsigned long long)offset);
1595 pci_add_resource_offset(resources, res, offset);
1600 * Null PCI config access functions, for the case when we can't
1603 #define NULL_PCI_OP(rw, size, type) \
1605 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1607 return PCIBIOS_DEVICE_NOT_FOUND; \
1611 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1614 return PCIBIOS_DEVICE_NOT_FOUND;
1618 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1621 return PCIBIOS_DEVICE_NOT_FOUND;
1624 static struct pci_ops null_pci_ops =
1626 .read = null_read_config,
1627 .write = null_write_config,
1631 * These functions are used early on before PCI scanning is done
1632 * and all of the pci_dev and pci_bus structures have been created.
1634 static struct pci_bus *
1635 fake_pci_bus(struct pci_controller *hose, int busnr)
1637 static struct pci_bus bus;
1640 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1644 bus.ops = hose? hose->ops: &null_pci_ops;
1648 #define EARLY_PCI_OP(rw, size, type) \
1649 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1650 int devfn, int offset, type value) \
1652 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1653 devfn, offset, value); \
1656 EARLY_PCI_OP(read, byte, u8 *)
1657 EARLY_PCI_OP(read, word, u16 *)
1658 EARLY_PCI_OP(read, dword, u32 *)
1659 EARLY_PCI_OP(write, byte, u8)
1660 EARLY_PCI_OP(write, word, u16)
1661 EARLY_PCI_OP(write, dword, u32)
1663 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1666 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1669 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1671 struct pci_controller *hose = bus->sysdata;
1673 return of_node_get(hose->dn);
1677 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1678 * @hose: Pointer to the PCI host controller instance structure
1680 void pcibios_scan_phb(struct pci_controller *hose)
1682 LIST_HEAD(resources);
1683 struct pci_bus *bus;
1684 struct device_node *node = hose->dn;
1687 pr_debug("PCI: Scanning PHB %pOF\n", node);
1689 /* Get some IO space for the new PHB */
1690 pcibios_setup_phb_io_space(hose);
1692 /* Wire up PHB bus resources */
1693 pcibios_setup_phb_resources(hose, &resources);
1695 hose->busn.start = hose->first_busno;
1696 hose->busn.end = hose->last_busno;
1697 hose->busn.flags = IORESOURCE_BUS;
1698 pci_add_resource(&resources, &hose->busn);
1700 /* Create an empty bus for the toplevel */
1701 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1702 hose->ops, hose, &resources);
1704 pr_err("Failed to create bus for PCI domain %04x\n",
1705 hose->global_number);
1706 pci_free_resource_list(&resources);
1711 /* Get probe mode and perform scan */
1712 mode = PCI_PROBE_NORMAL;
1713 if (node && hose->controller_ops.probe_mode)
1714 mode = hose->controller_ops.probe_mode(bus);
1715 pr_debug(" probe mode: %d\n", mode);
1716 if (mode == PCI_PROBE_DEVTREE)
1717 of_scan_bus(node, bus);
1719 if (mode == PCI_PROBE_NORMAL) {
1720 pci_bus_update_busn_res_end(bus, 255);
1721 hose->last_busno = pci_scan_child_bus(bus);
1722 pci_bus_update_busn_res_end(bus, hose->last_busno);
1725 /* Platform gets a chance to do some global fixups before
1726 * we proceed to resource allocation
1728 if (ppc_md.pcibios_fixup_phb)
1729 ppc_md.pcibios_fixup_phb(hose);
1731 /* Configure PCI Express settings */
1732 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1733 struct pci_bus *child;
1734 list_for_each_entry(child, &bus->children, node)
1735 pcie_bus_configure_settings(child);
1738 EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1740 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1742 int i, class = dev->class >> 8;
1743 /* When configured as agent, programing interface = 1 */
1744 int prog_if = dev->class & 0xf;
1746 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1747 class == PCI_CLASS_BRIDGE_OTHER) &&
1748 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1750 (dev->bus->parent == NULL)) {
1751 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1752 dev->resource[i].start = 0;
1753 dev->resource[i].end = 0;
1754 dev->resource[i].flags = 0;
1758 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1759 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1761 static void fixup_vga(struct pci_dev *pdev)
1765 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1766 if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device())
1767 vga_set_default_device(pdev);
1770 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1771 PCI_CLASS_DISPLAY_VGA, 8, fixup_vga);