1 // SPDX-License-Identifier: GPL-2.0+
3 * Turris 1.x Device Tree Source
5 * Copyright 2013 - 2022 CZ.NIC z.s.p.o. (http://www.nic.cz/)
7 * Pinout, Schematics and Altium hardware design files are open source
8 * and available at: https://docs.turris.cz/hw/turris-1x/turris-1x/
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/leds/common.h>
14 /include/ "fsl/p2020si-pre.dtsi"
18 compatible = "cznic,turris1x", "fsl,P2020RDB-PC"; /* fsl,P2020RDB-PC is required for booting Linux */
33 device_type = "memory";
37 ranges = <0x0 0x0 0xffe00000 0x00100000>;
40 /* PCA9557PW GPIO controller for boot config */
42 compatible = "nxp,pca9557";
50 /* STM32F030R8T6 MCU for power control */
53 * Turris Power Control firmware runs on STM32F0 MCU.
54 * This firmware is open source and available at:
55 * https://gitlab.nic.cz/turris/hw/turris_power_control
60 /* DDR3 SPD/EEPROM PSWP instruction */
65 /* SA56004ED temperature control */
66 temperature-sensor@4c {
67 compatible = "nxp,sa56004";
69 interrupt-parent = <&gpio>;
70 interrupts = <12 IRQ_TYPE_LEVEL_LOW>, /* GPIO12 - ALERT pin */
71 <13 IRQ_TYPE_LEVEL_LOW>; /* GPIO13 - CRIT pin */
75 /* Local temperature sensor (SA56004ED internal) */
81 /* Remote temperature sensor (D+/D- connected to P2020 CPU Temperature Diode) */
90 compatible = "atmel,spd";
94 /* MCP79402-I/ST Protected EEPROM */
99 /* ATSHA204-TH-DA-T crypto module */
101 compatible = "atmel,atsha204";
105 /* IDT6V49205BNLGI clock generator */
107 compatible = "idt,6v49205b";
111 /* MCP79402-I/ST RTC */
113 compatible = "microchip,mcp7940x";
115 interrupt-parent = <&gpio>;
116 interrupts = <14 0>; /* GPIO14 - MFP pin */
120 /* SPI on connector P1 */
124 gpio: gpio-controller@fc00 {
125 #interrupt-cells = <2>;
126 interrupt-controller;
129 /* Connected to SMSC USB2412-DZK 2-Port USB 2.0 Hub Controller */
135 enet0: ethernet@24000 {
136 /* Connected to port 6 of QCA8337N-AL3C switch */
137 phy-connection-type = "rgmii-id";
146 /* KSZ9031RNXCA ethernet phy for WAN port */
147 phy: ethernet-phy@7 {
148 interrupts = <3 1 0 0>;
152 /* QCA8337N-AL3C switch with integrated ethernet PHYs for LAN ports */
154 compatible = "qca,qca8337";
155 interrupts = <2 1 0 0>;
159 #address-cells = <1>;
166 phy-mode = "rgmii-id";
203 phy-mode = "rgmii-id";
215 fsl,tclk-period = <5>;
216 fsl,tmr-prsc = <200>;
217 fsl,tmr-add = <0xcccccccd>;
218 fsl,tmr-fiper1 = <0x3b9ac9fb>;
219 fsl,tmr-fiper2 = <0x0001869b>;
220 fsl,max-adj = <249999999>;
223 enet1: ethernet@25000 {
224 /* Connected to port 0 of QCA8337N-AL3C switch */
225 phy-connection-type = "rgmii-id";
237 enet2: ethernet@26000 {
238 /* Connected to KSZ9031RNXCA ethernet phy (WAN port) */
241 phy-connection-type = "rgmii-id";
250 cd-gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
254 lbc: localbus@ffe05000 {
255 reg = <0 0xffe05000 0 0x1000>;
257 ranges = <0x0 0x0 0x0 0xef000000 0x01000000>, /* NOR */
258 <0x1 0x0 0x0 0xff800000 0x00040000>, /* NAND */
259 <0x3 0x0 0x0 0xffa00000 0x00020000>; /* CPLD */
261 /* S29GL128P90TFIR10 NOR */
263 compatible = "cfi-flash";
264 reg = <0x0 0x0 0x01000000>;
269 compatible = "fixed-partitions";
270 #address-cells = <1>;
274 /* 128 kB for Device Tree Blob */
275 reg = <0x00000000 0x00020000>;
280 /* 1.7 MB for Linux Kernel Image */
281 reg = <0x00020000 0x001a0000>;
286 /* 1.5 MB for Rescue JFFS2 Root File System */
287 reg = <0x001c0000 0x00180000>;
292 /* 11 MB for TAR.XZ Archive with Factory content of NAND Root File System */
293 reg = <0x00340000 0x00b00000>;
298 /* 768 kB for Certificates JFFS2 File System */
299 reg = <0x00e40000 0x000c0000>;
300 label = "certificates";
303 /* free unused space 0x00f00000-0x00f20000 */
306 /* 128 kB for U-Boot Environment Variables */
307 reg = <0x00f20000 0x00020000>;
308 label = "u-boot-env";
312 /* 768 kB for U-Boot Bootloader Image */
313 reg = <0x00f40000 0x000c0000>;
319 /* MT29F2G08ABAEAWP:E NAND */
321 compatible = "fsl,p2020-fcm-nand", "fsl,elbc-fcm-nand";
322 reg = <0x1 0x0 0x00040000>;
323 nand-ecc-mode = "soft";
324 nand-ecc-algo = "bch";
327 compatible = "fixed-partitions";
328 #address-cells = <1>;
332 /* 256 MB for UBI with one volume: UBIFS Root File System */
333 reg = <0x00000000 0x10000000>;
339 /* LCMXO1200C-3FTN256C FPGA */
342 * Turris CPLD firmware which runs on this Lattice FPGA,
343 * is extended version of P1021RDB-PC CPLD v4.1 firmware.
344 * It is backward compatible with its original version
345 * and the only extension is support for Turris LEDs.
346 * Turris CPLD firmware is open source and available at:
347 * https://gitlab.nic.cz/turris/hw/turris_cpld/-/blob/master/CZ_NIC_Router_CPLD.v
349 compatible = "cznic,turris1x-cpld", "fsl,p1021rdb-pc-cpld", "simple-bus", "syscon";
350 reg = <0x3 0x0 0x30>;
351 #address-cells = <1>;
353 ranges = <0x0 0x3 0x0 0x00020000>;
355 /* MAX6370KA+T watchdog */
358 * CPLD firmware maps SET0, SET1 and SET2
359 * input logic of MAX6370KA+T chip to CPLD
360 * memory space at byte offset 0x2. WDI
361 * input logic is outside of the CPLD and
362 * connected via external GPIO.
364 compatible = "maxim,max6370";
366 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
370 compatible = "syscon-reboot";
379 * LEDs are controlled by CPLD firmware.
380 * All five LAN LEDs share common RGB settings
381 * and so it is not possible to set different
382 * colors on different LAN ports.
384 compatible = "cznic,turris1x-leds";
386 #address-cells = <1>;
391 color = <LED_COLOR_ID_RGB>;
392 function = LED_FUNCTION_WAN;
397 color = <LED_COLOR_ID_RGB>;
398 function = LED_FUNCTION_LAN;
399 function-enumerator = <5>;
404 color = <LED_COLOR_ID_RGB>;
405 function = LED_FUNCTION_LAN;
406 function-enumerator = <4>;
411 color = <LED_COLOR_ID_RGB>;
412 function = LED_FUNCTION_LAN;
413 function-enumerator = <3>;
418 color = <LED_COLOR_ID_RGB>;
419 function = LED_FUNCTION_LAN;
420 function-enumerator = <2>;
425 color = <LED_COLOR_ID_RGB>;
426 function = LED_FUNCTION_LAN;
427 function-enumerator = <1>;
432 color = <LED_COLOR_ID_RGB>;
433 function = LED_FUNCTION_WLAN;
438 color = <LED_COLOR_ID_RGB>;
439 function = LED_FUNCTION_POWER;
445 pci2: pcie@ffe08000 {
447 * PCIe bus for on-board TUSB7340RKM USB 3.0 xHCI controller.
448 * This xHCI controller is available only on Turris 1.1 boards.
449 * Turris 1.0 boards have nothing connected to this PCIe bus,
450 * so system would see only PCIe Root Port of this PCIe Root
451 * Complex. TUSB7340RKM xHCI controller has four SuperSpeed
452 * channels. Channel 0 is connected to the front USB 3.0 port,
453 * channel 1 (but only USB 2.0 subset) to USB 2.0 pins on mPCIe
454 * slot 1 (CN5), channels 2 and 3 to connector P600.
456 * P2020 PCIe Root Port does not use PCIe MEM and xHCI controller
457 * uses 64kB + 8kB of PCIe MEM. No PCIe IO is used or required.
458 * So allocate 128kB of PCIe MEM for this PCIe bus.
460 reg = <0 0xffe08000 0 0x1000>;
461 ranges = <0x02000000 0x0 0xc0000000 0 0xc0000000 0x0 0x00020000>, /* MEM */
462 <0x01000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>; /* IO */
469 pci1: pcie@ffe09000 {
470 /* PCIe bus on mPCIe slot 2 (CN6) for expansion mPCIe card */
471 reg = <0 0xffe09000 0 0x1000>;
472 ranges = <0x02000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000>, /* MEM */
473 <0x01000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>; /* IO */
480 pci0: pcie@ffe0a000 {
482 * PCIe bus on mPCIe slot 1 (CN5) for expansion mPCIe card.
483 * Turris 1.1 boards have in this mPCIe slot additional USB 2.0
484 * pins via channel 1 of TUSB7340RKM xHCI controller and also
485 * additional SIM card slot, both for USB-based WWAN cards.
487 reg = <0 0xffe0a000 0 0x1000>;
488 ranges = <0x02000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000>, /* MEM */
489 <0x01000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>; /* IO */
497 /include/ "fsl/p2020si-post.dtsi"