1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
4 #ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H
5 #define _DT_BINDINGS_POWER_QCOM_RPMPD_H
7 /* SDM845 Power Domain Indexes */
10 #define SDM845_MX_AO 2
12 #define SDM845_CX_AO 4
18 /* SDX55 Power Domain Indexes */
23 /* SDX65 Power Domain Indexes */
31 /* SM6350 Power Domain Indexes */
39 /* SM8150 Power Domain Indexes */
46 #define SM8150_MX_AO 6
48 #define SM8150_CX_AO 8
50 #define SM8150_MMCX_AO 10
52 /* SM8250 Power Domain Indexes */
54 #define SM8250_CX_AO 1
60 #define SM8250_MMCX_AO 7
62 #define SM8250_MX_AO 9
64 /* SM8350 Power Domain Indexes */
66 #define SM8350_CX_AO 1
72 #define SM8350_MMCX_AO 7
74 #define SM8350_MX_AO 9
76 #define SM8350_MXC_AO 11
79 /* SM8450 Power Domain Indexes */
81 #define SM8450_CX_AO 1
87 #define SM8450_MMCX_AO 7
89 #define SM8450_MX_AO 9
91 #define SM8450_MXC_AO 11
94 /* SC7180 Power Domain Indexes */
96 #define SC7180_CX_AO 1
99 #define SC7180_MX_AO 4
104 /* SC7280 Power Domain Indexes */
106 #define SC7280_CX_AO 1
110 #define SC7280_MX_AO 5
115 /* SC8180X Power Domain Indexes */
117 #define SC8180X_CX_AO 1
118 #define SC8180X_EBI 2
119 #define SC8180X_GFX 3
120 #define SC8180X_LCX 4
121 #define SC8180X_LMX 5
122 #define SC8180X_MMCX 6
123 #define SC8180X_MMCX_AO 7
124 #define SC8180X_MSS 8
126 #define SC8180X_MX_AO 10
128 /* SC8280XP Power Domain Indexes */
129 #define SC8280XP_CX 0
130 #define SC8280XP_CX_AO 1
131 #define SC8280XP_DDR 2
132 #define SC8280XP_EBI 3
133 #define SC8280XP_GFX 4
134 #define SC8280XP_LCX 5
135 #define SC8280XP_LMX 6
136 #define SC8280XP_MMCX 7
137 #define SC8280XP_MMCX_AO 8
138 #define SC8280XP_MSS 9
139 #define SC8280XP_MX 10
140 #define SC8280XP_MXC 12
141 #define SC8280XP_MX_AO 11
142 #define SC8280XP_NSP 13
143 #define SC8280XP_QPHY 14
144 #define SC8280XP_XO 15
146 /* SDM845 Power Domain performance levels */
147 #define RPMH_REGULATOR_LEVEL_RETENTION 16
148 #define RPMH_REGULATOR_LEVEL_MIN_SVS 48
149 #define RPMH_REGULATOR_LEVEL_LOW_SVS 64
150 #define RPMH_REGULATOR_LEVEL_SVS 128
151 #define RPMH_REGULATOR_LEVEL_SVS_L0 144
152 #define RPMH_REGULATOR_LEVEL_SVS_L1 192
153 #define RPMH_REGULATOR_LEVEL_SVS_L2 224
154 #define RPMH_REGULATOR_LEVEL_NOM 256
155 #define RPMH_REGULATOR_LEVEL_NOM_L1 320
156 #define RPMH_REGULATOR_LEVEL_NOM_L2 336
157 #define RPMH_REGULATOR_LEVEL_TURBO 384
158 #define RPMH_REGULATOR_LEVEL_TURBO_L1 416
160 /* MDM9607 Power Domains */
161 #define MDM9607_VDDCX 0
162 #define MDM9607_VDDCX_AO 1
163 #define MDM9607_VDDCX_VFL 2
164 #define MDM9607_VDDMX 3
165 #define MDM9607_VDDMX_AO 4
166 #define MDM9607_VDDMX_VFL 5
168 /* MSM8226 Power Domain Indexes */
169 #define MSM8226_VDDCX 0
170 #define MSM8226_VDDCX_AO 1
171 #define MSM8226_VDDCX_VFC 2
173 /* MSM8939 Power Domains */
174 #define MSM8939_VDDMDCX 0
175 #define MSM8939_VDDMDCX_AO 1
176 #define MSM8939_VDDMDCX_VFC 2
177 #define MSM8939_VDDCX 3
178 #define MSM8939_VDDCX_AO 4
179 #define MSM8939_VDDCX_VFC 5
180 #define MSM8939_VDDMX 6
181 #define MSM8939_VDDMX_AO 7
183 /* MSM8916 Power Domain Indexes */
184 #define MSM8916_VDDCX 0
185 #define MSM8916_VDDCX_AO 1
186 #define MSM8916_VDDCX_VFC 2
187 #define MSM8916_VDDMX 3
188 #define MSM8916_VDDMX_AO 4
190 /* MSM8909 Power Domain Indexes */
191 #define MSM8909_VDDCX MSM8916_VDDCX
192 #define MSM8909_VDDCX_AO MSM8916_VDDCX_AO
193 #define MSM8909_VDDCX_VFC MSM8916_VDDCX_VFC
194 #define MSM8909_VDDMX MSM8916_VDDMX
195 #define MSM8909_VDDMX_AO MSM8916_VDDMX_AO
197 /* MSM8953 Power Domain Indexes */
198 #define MSM8953_VDDMD 0
199 #define MSM8953_VDDMD_AO 1
200 #define MSM8953_VDDCX 2
201 #define MSM8953_VDDCX_AO 3
202 #define MSM8953_VDDCX_VFL 4
203 #define MSM8953_VDDMX 5
204 #define MSM8953_VDDMX_AO 6
206 /* MSM8976 Power Domain Indexes */
207 #define MSM8976_VDDCX 0
208 #define MSM8976_VDDCX_AO 1
209 #define MSM8976_VDDCX_VFL 2
210 #define MSM8976_VDDMX 3
211 #define MSM8976_VDDMX_AO 4
212 #define MSM8976_VDDMX_VFL 5
214 /* MSM8994 Power Domain Indexes */
215 #define MSM8994_VDDCX 0
216 #define MSM8994_VDDCX_AO 1
217 #define MSM8994_VDDCX_VFC 2
218 #define MSM8994_VDDMX 3
219 #define MSM8994_VDDMX_AO 4
220 #define MSM8994_VDDGFX 5
221 #define MSM8994_VDDGFX_VFC 6
223 /* MSM8996 Power Domain Indexes */
224 #define MSM8996_VDDCX 0
225 #define MSM8996_VDDCX_AO 1
226 #define MSM8996_VDDCX_VFC 2
227 #define MSM8996_VDDMX 3
228 #define MSM8996_VDDMX_AO 4
229 #define MSM8996_VDDSSCX 5
230 #define MSM8996_VDDSSCX_VFC 6
232 /* MSM8998 Power Domain Indexes */
233 #define MSM8998_VDDCX 0
234 #define MSM8998_VDDCX_AO 1
235 #define MSM8998_VDDCX_VFL 2
236 #define MSM8998_VDDMX 3
237 #define MSM8998_VDDMX_AO 4
238 #define MSM8998_VDDMX_VFL 5
239 #define MSM8998_SSCCX 6
240 #define MSM8998_SSCCX_VFL 7
241 #define MSM8998_SSCMX 8
242 #define MSM8998_SSCMX_VFL 9
244 /* QCS404 Power Domains */
245 #define QCS404_VDDMX 0
246 #define QCS404_VDDMX_AO 1
247 #define QCS404_VDDMX_VFL 2
248 #define QCS404_LPICX 3
249 #define QCS404_LPICX_VFL 4
250 #define QCS404_LPIMX 5
251 #define QCS404_LPIMX_VFL 6
253 /* SDM660 Power Domains */
254 #define SDM660_VDDCX 0
255 #define SDM660_VDDCX_AO 1
256 #define SDM660_VDDCX_VFL 2
257 #define SDM660_VDDMX 3
258 #define SDM660_VDDMX_AO 4
259 #define SDM660_VDDMX_VFL 5
260 #define SDM660_SSCCX 6
261 #define SDM660_SSCCX_VFL 7
262 #define SDM660_SSCMX 8
263 #define SDM660_SSCMX_VFL 9
265 /* SM6115 Power Domains */
266 #define SM6115_VDDCX 0
267 #define SM6115_VDDCX_AO 1
268 #define SM6115_VDDCX_VFL 2
269 #define SM6115_VDDMX 3
270 #define SM6115_VDDMX_AO 4
271 #define SM6115_VDDMX_VFL 5
272 #define SM6115_VDD_LPI_CX 6
273 #define SM6115_VDD_LPI_MX 7
275 /* SM6125 Power Domains */
276 #define SM6125_VDDCX 0
277 #define SM6125_VDDCX_AO 1
278 #define SM6125_VDDCX_VFL 2
279 #define SM6125_VDDMX 3
280 #define SM6125_VDDMX_AO 4
281 #define SM6125_VDDMX_VFL 5
283 /* QCM2290 Power Domains */
284 #define QCM2290_VDDCX 0
285 #define QCM2290_VDDCX_AO 1
286 #define QCM2290_VDDCX_VFL 2
287 #define QCM2290_VDDMX 3
288 #define QCM2290_VDDMX_AO 4
289 #define QCM2290_VDDMX_VFL 5
290 #define QCM2290_VDD_LPI_CX 6
291 #define QCM2290_VDD_LPI_MX 7
293 /* RPM SMD Power Domain performance levels */
294 #define RPM_SMD_LEVEL_RETENTION 16
295 #define RPM_SMD_LEVEL_RETENTION_PLUS 32
296 #define RPM_SMD_LEVEL_MIN_SVS 48
297 #define RPM_SMD_LEVEL_LOW_SVS 64
298 #define RPM_SMD_LEVEL_SVS 128
299 #define RPM_SMD_LEVEL_SVS_PLUS 192
300 #define RPM_SMD_LEVEL_NOM 256
301 #define RPM_SMD_LEVEL_NOM_PLUS 320
302 #define RPM_SMD_LEVEL_TURBO 384
303 #define RPM_SMD_LEVEL_TURBO_NO_CPR 416
304 #define RPM_SMD_LEVEL_TURBO_HIGH 448
305 #define RPM_SMD_LEVEL_BINNING 512