1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/soc/tegra/pmc.c
5 * Copyright (c) 2010 Google, Inc
6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
9 * Colin Cross <ccross@google.com>
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/clkdev.h>
18 #include <linux/clk/clk-conf.h>
19 #include <linux/clk/tegra.h>
20 #include <linux/debugfs.h>
21 #include <linux/delay.h>
22 #include <linux/device.h>
23 #include <linux/err.h>
24 #include <linux/export.h>
25 #include <linux/init.h>
27 #include <linux/iopoll.h>
28 #include <linux/irqdomain.h>
29 #include <linux/irq.h>
30 #include <linux/kernel.h>
31 #include <linux/of_address.h>
32 #include <linux/of_clk.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_platform.h>
36 #include <linux/pinctrl/pinconf-generic.h>
37 #include <linux/pinctrl/pinconf.h>
38 #include <linux/pinctrl/pinctrl.h>
39 #include <linux/platform_device.h>
40 #include <linux/pm_domain.h>
41 #include <linux/reboot.h>
42 #include <linux/reset.h>
43 #include <linux/seq_file.h>
44 #include <linux/slab.h>
45 #include <linux/spinlock.h>
47 #include <soc/tegra/common.h>
48 #include <soc/tegra/fuse.h>
49 #include <soc/tegra/pmc.h>
51 #include <dt-bindings/interrupt-controller/arm-gic.h>
52 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
53 #include <dt-bindings/gpio/tegra186-gpio.h>
54 #include <dt-bindings/gpio/tegra194-gpio.h>
55 #include <dt-bindings/soc/tegra-pmc.h>
58 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
59 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
60 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
61 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
62 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
63 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
64 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8)
65 #define PMC_CNTRL_BLINK_EN 7
66 #define PMC_CNTRL_MAIN_RST BIT(4)
68 #define PMC_WAKE_MASK 0x0c
69 #define PMC_WAKE_LEVEL 0x10
70 #define PMC_WAKE_STATUS 0x14
71 #define PMC_SW_WAKE_STATUS 0x18
72 #define PMC_DPD_PADS_ORIDE 0x1c
73 #define PMC_DPD_PADS_ORIDE_BLINK 20
75 #define DPD_SAMPLE 0x020
76 #define DPD_SAMPLE_ENABLE BIT(0)
77 #define DPD_SAMPLE_DISABLE (0 << 0)
79 #define PWRGATE_TOGGLE 0x30
80 #define PWRGATE_TOGGLE_START BIT(8)
82 #define REMOVE_CLAMPING 0x34
84 #define PWRGATE_STATUS 0x38
86 #define PMC_BLINK_TIMER 0x40
87 #define PMC_IMPL_E_33V_PWR 0x40
89 #define PMC_PWR_DET 0x48
91 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
92 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
93 #define PMC_SCRATCH0_MODE_RCM BIT(1)
94 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
95 PMC_SCRATCH0_MODE_BOOTLOADER | \
96 PMC_SCRATCH0_MODE_RCM)
98 #define PMC_CPUPWRGOOD_TIMER 0xc8
99 #define PMC_CPUPWROFF_TIMER 0xcc
100 #define PMC_COREPWRGOOD_TIMER 0x3c
101 #define PMC_COREPWROFF_TIMER 0xe0
103 #define PMC_PWR_DET_VALUE 0xe4
105 #define PMC_SCRATCH41 0x140
107 #define PMC_WAKE2_MASK 0x160
108 #define PMC_WAKE2_LEVEL 0x164
109 #define PMC_WAKE2_STATUS 0x168
110 #define PMC_SW_WAKE2_STATUS 0x16c
112 #define PMC_CLK_OUT_CNTRL 0x1a8
113 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0)
114 #define PMC_SENSOR_CTRL 0x1b0
115 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
116 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
118 #define PMC_RST_STATUS_POR 0
119 #define PMC_RST_STATUS_WATCHDOG 1
120 #define PMC_RST_STATUS_SENSOR 2
121 #define PMC_RST_STATUS_SW_MAIN 3
122 #define PMC_RST_STATUS_LP0 4
123 #define PMC_RST_STATUS_AOTAG 5
125 #define IO_DPD_REQ 0x1b8
126 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
127 #define IO_DPD_REQ_CODE_OFF (1U << 30)
128 #define IO_DPD_REQ_CODE_ON (2U << 30)
129 #define IO_DPD_REQ_CODE_MASK (3U << 30)
131 #define IO_DPD_STATUS 0x1bc
132 #define IO_DPD2_REQ 0x1c0
133 #define IO_DPD2_STATUS 0x1c4
134 #define SEL_DPD_TIM 0x1c8
136 #define PMC_SCRATCH54 0x258
137 #define PMC_SCRATCH54_DATA_SHIFT 8
138 #define PMC_SCRATCH54_ADDR_SHIFT 0
140 #define PMC_SCRATCH55 0x25c
141 #define PMC_SCRATCH55_RESET_TEGRA BIT(31)
142 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
143 #define PMC_SCRATCH55_PINMUX_SHIFT 24
144 #define PMC_SCRATCH55_16BITOP BIT(15)
145 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
146 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
148 #define GPU_RG_CNTRL 0x2d4
150 /* Tegra186 and later */
151 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
152 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
153 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
154 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
155 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
156 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
157 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
158 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
159 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
161 #define WAKE_AOWAKE_CTRL 0x4f4
162 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
165 #define TEGRA_SMC_PMC 0xc2fffe00
166 #define TEGRA_SMC_PMC_READ 0xaa
167 #define TEGRA_SMC_PMC_WRITE 0xbb
176 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
178 struct pmc_clk_gate {
184 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
186 struct pmc_clk_init_data {
188 const char *const *parents;
195 static const char * const clk_out1_parents[] = { "osc", "osc_div2",
196 "osc_div4", "extern1",
199 static const char * const clk_out2_parents[] = { "osc", "osc_div2",
200 "osc_div4", "extern2",
203 static const char * const clk_out3_parents[] = { "osc", "osc_div2",
204 "osc_div4", "extern3",
207 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
209 .name = "pmc_clk_out_1",
210 .parents = clk_out1_parents,
211 .num_parents = ARRAY_SIZE(clk_out1_parents),
212 .clk_id = TEGRA_PMC_CLK_OUT_1,
217 .name = "pmc_clk_out_2",
218 .parents = clk_out2_parents,
219 .num_parents = ARRAY_SIZE(clk_out2_parents),
220 .clk_id = TEGRA_PMC_CLK_OUT_2,
222 .force_en_shift = 10,
225 .name = "pmc_clk_out_3",
226 .parents = clk_out3_parents,
227 .num_parents = ARRAY_SIZE(clk_out3_parents),
228 .clk_id = TEGRA_PMC_CLK_OUT_3,
230 .force_en_shift = 18,
234 struct tegra_powergate {
235 struct generic_pm_domain genpd;
236 struct tegra_pmc *pmc;
239 unsigned int num_clks;
240 struct reset_control *reset;
243 struct tegra_io_pad_soc {
244 enum tegra_io_pad id;
246 unsigned int voltage;
250 struct tegra_pmc_regs {
251 unsigned int scratch0;
252 unsigned int dpd_req;
253 unsigned int dpd_status;
254 unsigned int dpd2_req;
255 unsigned int dpd2_status;
256 unsigned int rst_status;
257 unsigned int rst_source_shift;
258 unsigned int rst_source_mask;
259 unsigned int rst_level_shift;
260 unsigned int rst_level_mask;
263 struct tegra_wake_event {
268 unsigned int instance;
273 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \
279 .instance = UINT_MAX, \
284 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \
290 .instance = _instance, \
295 struct tegra_pmc_soc {
296 unsigned int num_powergates;
297 const char *const *powergates;
298 unsigned int num_cpu_powergates;
299 const u8 *cpu_powergates;
301 bool has_tsense_reset;
303 bool needs_mbist_war;
304 bool has_impl_33v_pwr;
307 const struct tegra_io_pad_soc *io_pads;
308 unsigned int num_io_pads;
310 const struct pinctrl_pin_desc *pin_descs;
311 unsigned int num_pin_descs;
313 const struct tegra_pmc_regs *regs;
314 void (*init)(struct tegra_pmc *pmc);
315 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
316 struct device_node *np,
318 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
319 int (*irq_set_type)(struct irq_data *data, unsigned int type);
320 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id,
323 const char * const *reset_sources;
324 unsigned int num_reset_sources;
325 const char * const *reset_levels;
326 unsigned int num_reset_levels;
329 * These describe events that can wake the system from sleep (i.e.
330 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
331 * are dealt with in the LIC.
333 const struct tegra_wake_event *wake_events;
334 unsigned int num_wake_events;
336 const struct pmc_clk_init_data *pmc_clks_data;
337 unsigned int num_pmc_clks;
338 bool has_blink_output;
342 * struct tegra_pmc - NVIDIA Tegra PMC
343 * @dev: pointer to PMC device structure
344 * @base: pointer to I/O remapped register region
345 * @wake: pointer to I/O remapped region for WAKE registers
346 * @aotag: pointer to I/O remapped region for AOTAG registers
347 * @scratch: pointer to I/O remapped region for scratch registers
348 * @clk: pointer to pclk clock
349 * @soc: pointer to SoC data structure
350 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
351 * @debugfs: pointer to debugfs entry
352 * @rate: currently configured rate of pclk
353 * @suspend_mode: lowest suspend mode available
354 * @cpu_good_time: CPU power good time (in microseconds)
355 * @cpu_off_time: CPU power off time (in microsecends)
356 * @core_osc_time: core power good OSC time (in microseconds)
357 * @core_pmu_time: core power good PMU time (in microseconds)
358 * @core_off_time: core power off time (in microseconds)
359 * @corereq_high: core power request is active-high
360 * @sysclkreq_high: system clock request is active-high
361 * @combined_req: combined power request for CPU & core
362 * @cpu_pwr_good_en: CPU power good signal is enabled
363 * @lp0_vec_phys: physical base address of the LP0 warm boot code
364 * @lp0_vec_size: size of the LP0 warm boot code
365 * @powergates_available: Bitmap of available power gates
366 * @powergates_lock: mutex for power gate register access
367 * @pctl_dev: pin controller exposed by the PMC
368 * @domain: IRQ domain provided by the PMC
369 * @irq: chip implementation for the IRQ domain
370 * @clk_nb: pclk clock changes handler
377 void __iomem *scratch;
379 struct dentry *debugfs;
381 const struct tegra_pmc_soc *soc;
386 enum tegra_suspend_mode suspend_mode;
395 bool cpu_pwr_good_en;
398 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
400 struct mutex powergates_lock;
402 struct pinctrl_dev *pctl_dev;
404 struct irq_domain *domain;
407 struct notifier_block clk_nb;
410 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
412 .suspend_mode = TEGRA_SUSPEND_NONE,
415 static inline struct tegra_powergate *
416 to_powergate(struct generic_pm_domain *domain)
418 return container_of(domain, struct tegra_powergate, genpd);
421 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
423 struct arm_smccc_res res;
426 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
430 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
433 pr_warn("%s(): SMC failed: %lu\n", __func__,
440 return readl(pmc->base + offset);
443 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
444 unsigned long offset)
446 struct arm_smccc_res res;
449 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
450 value, 0, 0, 0, 0, &res);
453 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
456 pr_warn("%s(): SMC failed: %lu\n", __func__,
460 writel(value, pmc->base + offset);
464 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
467 return tegra_pmc_readl(pmc, offset);
469 return readl(pmc->scratch + offset);
472 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
473 unsigned long offset)
476 tegra_pmc_writel(pmc, value, offset);
478 writel(value, pmc->scratch + offset);
482 * TODO Figure out a way to call this with the struct tegra_pmc * passed in.
483 * This currently doesn't work because readx_poll_timeout() can only operate
484 * on functions that take a single argument.
486 static inline bool tegra_powergate_state(int id)
488 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
489 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
491 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
494 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
496 return (pmc->soc && pmc->soc->powergates[id]);
499 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
501 return test_bit(id, pmc->powergates_available);
504 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
508 if (!pmc || !pmc->soc || !name)
511 for (i = 0; i < pmc->soc->num_powergates; i++) {
512 if (!tegra_powergate_is_valid(pmc, i))
515 if (!strcmp(name, pmc->soc->powergates[i]))
522 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id,
525 unsigned int retries = 100;
530 * As per TRM documentation, the toggle command will be dropped by PMC
531 * if there is contention with a HW-initiated toggling (i.e. CPU core
532 * power-gated), the command should be retried in that case.
535 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
537 /* wait for PMC to execute the command */
538 ret = readx_poll_timeout(tegra_powergate_state, id, status,
539 status == new_state, 1, 10);
540 } while (ret == -ETIMEDOUT && retries--);
545 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc)
547 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START);
550 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id,
556 /* wait while PMC power gating is contended */
557 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
558 status == true, 1, 100);
562 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
564 /* wait for PMC to accept the command */
565 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
566 status == true, 1, 100);
570 /* wait for PMC to execute the command */
571 err = readx_poll_timeout(tegra_powergate_state, id, status,
572 status == new_state, 10, 100000);
580 * tegra_powergate_set() - set the state of a partition
581 * @pmc: power management controller
583 * @new_state: new state of the partition
585 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
590 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
593 mutex_lock(&pmc->powergates_lock);
595 if (tegra_powergate_state(id) == new_state) {
596 mutex_unlock(&pmc->powergates_lock);
600 err = pmc->soc->powergate_set(pmc, id, new_state);
602 mutex_unlock(&pmc->powergates_lock);
607 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
612 mutex_lock(&pmc->powergates_lock);
615 * On Tegra124 and later, the clamps for the GPU are controlled by a
616 * separate register (with different semantics).
618 if (id == TEGRA_POWERGATE_3D) {
619 if (pmc->soc->has_gpu_clamps) {
620 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
626 * Tegra 2 has a bug where PCIE and VDE clamping masks are
627 * swapped relatively to the partition ids
629 if (id == TEGRA_POWERGATE_VDEC)
630 mask = (1 << TEGRA_POWERGATE_PCIE);
631 else if (id == TEGRA_POWERGATE_PCIE)
632 mask = (1 << TEGRA_POWERGATE_VDEC);
636 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
639 mutex_unlock(&pmc->powergates_lock);
644 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
648 for (i = 0; i < pg->num_clks; i++)
649 clk_disable_unprepare(pg->clks[i]);
652 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
657 for (i = 0; i < pg->num_clks; i++) {
658 err = clk_prepare_enable(pg->clks[i]);
667 clk_disable_unprepare(pg->clks[i]);
672 int __weak tegra210_clk_handle_mbist_war(unsigned int id)
677 static int tegra_powergate_power_up(struct tegra_powergate *pg,
682 err = reset_control_assert(pg->reset);
686 usleep_range(10, 20);
688 err = tegra_powergate_set(pg->pmc, pg->id, true);
692 usleep_range(10, 20);
694 err = tegra_powergate_enable_clocks(pg);
698 usleep_range(10, 20);
700 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
704 usleep_range(10, 20);
706 err = reset_control_deassert(pg->reset);
710 usleep_range(10, 20);
712 if (pg->pmc->soc->needs_mbist_war)
713 err = tegra210_clk_handle_mbist_war(pg->id);
718 tegra_powergate_disable_clocks(pg);
723 tegra_powergate_disable_clocks(pg);
724 usleep_range(10, 20);
727 tegra_powergate_set(pg->pmc, pg->id, false);
732 static int tegra_powergate_power_down(struct tegra_powergate *pg)
736 err = tegra_powergate_enable_clocks(pg);
740 usleep_range(10, 20);
742 err = reset_control_assert(pg->reset);
746 usleep_range(10, 20);
748 tegra_powergate_disable_clocks(pg);
750 usleep_range(10, 20);
752 err = tegra_powergate_set(pg->pmc, pg->id, false);
759 tegra_powergate_enable_clocks(pg);
760 usleep_range(10, 20);
761 reset_control_deassert(pg->reset);
762 usleep_range(10, 20);
765 tegra_powergate_disable_clocks(pg);
770 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
772 struct tegra_powergate *pg = to_powergate(domain);
773 struct device *dev = pg->pmc->dev;
776 err = tegra_powergate_power_up(pg, true);
778 dev_err(dev, "failed to turn on PM domain %s: %d\n",
779 pg->genpd.name, err);
783 reset_control_release(pg->reset);
789 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
791 struct tegra_powergate *pg = to_powergate(domain);
792 struct device *dev = pg->pmc->dev;
795 err = reset_control_acquire(pg->reset);
797 pr_err("failed to acquire resets: %d\n", err);
801 err = tegra_powergate_power_down(pg);
803 dev_err(dev, "failed to turn off PM domain %s: %d\n",
804 pg->genpd.name, err);
805 reset_control_release(pg->reset);
812 * tegra_powergate_power_on() - power on partition
815 int tegra_powergate_power_on(unsigned int id)
817 if (!tegra_powergate_is_available(pmc, id))
820 return tegra_powergate_set(pmc, id, true);
822 EXPORT_SYMBOL(tegra_powergate_power_on);
825 * tegra_powergate_power_off() - power off partition
828 int tegra_powergate_power_off(unsigned int id)
830 if (!tegra_powergate_is_available(pmc, id))
833 return tegra_powergate_set(pmc, id, false);
835 EXPORT_SYMBOL(tegra_powergate_power_off);
838 * tegra_powergate_is_powered() - check if partition is powered
839 * @pmc: power management controller
842 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
844 if (!tegra_powergate_is_valid(pmc, id))
847 return tegra_powergate_state(id);
851 * tegra_powergate_remove_clamping() - remove power clamps for partition
854 int tegra_powergate_remove_clamping(unsigned int id)
856 if (!tegra_powergate_is_available(pmc, id))
859 return __tegra_powergate_remove_clamping(pmc, id);
861 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
864 * tegra_powergate_sequence_power_up() - power up partition
866 * @clk: clock for partition
867 * @rst: reset for partition
869 * Must be called with clk disabled, and returns with clk enabled.
871 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
872 struct reset_control *rst)
874 struct tegra_powergate *pg;
877 if (!tegra_powergate_is_available(pmc, id))
880 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
890 err = tegra_powergate_power_up(pg, false);
892 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
899 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
902 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
903 * @pmc: power management controller
904 * @cpuid: CPU partition ID
906 * Returns the partition ID corresponding to the CPU partition ID or a
907 * negative error code on failure.
909 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
912 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
913 return pmc->soc->cpu_powergates[cpuid];
919 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
920 * @cpuid: CPU partition ID
922 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
926 id = tegra_get_cpu_powergate_id(pmc, cpuid);
930 return tegra_powergate_is_powered(pmc, id);
934 * tegra_pmc_cpu_power_on() - power on CPU partition
935 * @cpuid: CPU partition ID
937 int tegra_pmc_cpu_power_on(unsigned int cpuid)
941 id = tegra_get_cpu_powergate_id(pmc, cpuid);
945 return tegra_powergate_set(pmc, id, true);
949 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
950 * @cpuid: CPU partition ID
952 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
956 id = tegra_get_cpu_powergate_id(pmc, cpuid);
960 return tegra_powergate_remove_clamping(id);
963 static int tegra_pmc_restart_notify(struct notifier_block *this,
964 unsigned long action, void *data)
966 const char *cmd = data;
969 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
970 value &= ~PMC_SCRATCH0_MODE_MASK;
973 if (strcmp(cmd, "recovery") == 0)
974 value |= PMC_SCRATCH0_MODE_RECOVERY;
976 if (strcmp(cmd, "bootloader") == 0)
977 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
979 if (strcmp(cmd, "forced-recovery") == 0)
980 value |= PMC_SCRATCH0_MODE_RCM;
983 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
985 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
986 value = tegra_pmc_readl(pmc, PMC_CNTRL);
987 value |= PMC_CNTRL_MAIN_RST;
988 tegra_pmc_writel(pmc, value, PMC_CNTRL);
993 static struct notifier_block tegra_pmc_restart_handler = {
994 .notifier_call = tegra_pmc_restart_notify,
998 static int powergate_show(struct seq_file *s, void *data)
1003 seq_printf(s, " powergate powered\n");
1004 seq_printf(s, "------------------\n");
1006 for (i = 0; i < pmc->soc->num_powergates; i++) {
1007 status = tegra_powergate_is_powered(pmc, i);
1011 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
1012 status ? "yes" : "no");
1018 DEFINE_SHOW_ATTRIBUTE(powergate);
1020 static int tegra_powergate_debugfs_init(void)
1022 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
1030 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
1031 struct device_node *np)
1034 unsigned int i, count;
1037 count = of_clk_get_parent_count(np);
1041 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
1045 for (i = 0; i < count; i++) {
1046 pg->clks[i] = of_clk_get(np, i);
1047 if (IS_ERR(pg->clks[i])) {
1048 err = PTR_ERR(pg->clks[i]);
1053 pg->num_clks = count;
1059 clk_put(pg->clks[i]);
1066 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
1067 struct device_node *np, bool off)
1069 struct device *dev = pg->pmc->dev;
1072 pg->reset = of_reset_control_array_get_exclusive_released(np);
1073 if (IS_ERR(pg->reset)) {
1074 err = PTR_ERR(pg->reset);
1075 dev_err(dev, "failed to get device resets: %d\n", err);
1079 err = reset_control_acquire(pg->reset);
1081 pr_err("failed to acquire resets: %d\n", err);
1086 err = reset_control_assert(pg->reset);
1088 err = reset_control_deassert(pg->reset);
1092 reset_control_release(pg->reset);
1097 reset_control_release(pg->reset);
1098 reset_control_put(pg->reset);
1104 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
1106 struct device *dev = pmc->dev;
1107 struct tegra_powergate *pg;
1111 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
1115 id = tegra_powergate_lookup(pmc, np->name);
1117 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
1123 * Clear the bit for this powergate so it cannot be managed
1124 * directly via the legacy APIs for controlling powergates.
1126 clear_bit(id, pmc->powergates_available);
1129 pg->genpd.name = np->name;
1130 pg->genpd.power_off = tegra_genpd_power_off;
1131 pg->genpd.power_on = tegra_genpd_power_on;
1134 off = !tegra_powergate_is_powered(pmc, pg->id);
1136 err = tegra_powergate_of_get_clks(pg, np);
1138 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);
1142 err = tegra_powergate_of_get_resets(pg, np, off);
1144 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);
1148 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
1150 WARN_ON(tegra_powergate_power_up(pg, true));
1155 err = pm_genpd_init(&pg->genpd, NULL, off);
1157 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,
1162 err = of_genpd_add_provider_simple(np, &pg->genpd);
1164 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",
1169 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
1174 pm_genpd_remove(&pg->genpd);
1177 reset_control_put(pg->reset);
1180 while (pg->num_clks--)
1181 clk_put(pg->clks[pg->num_clks]);
1186 set_bit(id, pmc->powergates_available);
1194 static int tegra_powergate_init(struct tegra_pmc *pmc,
1195 struct device_node *parent)
1197 struct device_node *np, *child;
1200 np = of_get_child_by_name(parent, "powergates");
1204 for_each_child_of_node(np, child) {
1205 err = tegra_powergate_add(pmc, child);
1217 static void tegra_powergate_remove(struct generic_pm_domain *genpd)
1219 struct tegra_powergate *pg = to_powergate(genpd);
1221 reset_control_put(pg->reset);
1223 while (pg->num_clks--)
1224 clk_put(pg->clks[pg->num_clks]);
1228 set_bit(pg->id, pmc->powergates_available);
1233 static void tegra_powergate_remove_all(struct device_node *parent)
1235 struct generic_pm_domain *genpd;
1236 struct device_node *np, *child;
1238 np = of_get_child_by_name(parent, "powergates");
1242 for_each_child_of_node(np, child) {
1243 of_genpd_del_provider(child);
1245 genpd = of_genpd_remove_last(child);
1249 tegra_powergate_remove(genpd);
1255 static const struct tegra_io_pad_soc *
1256 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1260 for (i = 0; i < pmc->soc->num_io_pads; i++)
1261 if (pmc->soc->io_pads[i].id == id)
1262 return &pmc->soc->io_pads[i];
1267 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc,
1268 enum tegra_io_pad id,
1269 unsigned long *request,
1270 unsigned long *status,
1273 const struct tegra_io_pad_soc *pad;
1275 pad = tegra_io_pad_find(pmc, id);
1277 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1281 if (pad->dpd == UINT_MAX)
1284 *mask = BIT(pad->dpd % 32);
1286 if (pad->dpd < 32) {
1287 *status = pmc->soc->regs->dpd_status;
1288 *request = pmc->soc->regs->dpd_req;
1290 *status = pmc->soc->regs->dpd2_status;
1291 *request = pmc->soc->regs->dpd2_req;
1297 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id,
1298 unsigned long *request, unsigned long *status,
1301 unsigned long rate, value;
1304 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask);
1311 dev_err(pmc->dev, "failed to get clock rate\n");
1315 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1317 /* must be at least 200 ns, in APB (PCLK) clock cycles */
1318 value = DIV_ROUND_UP(1000000000, rate);
1319 value = DIV_ROUND_UP(200, value);
1320 tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1326 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1327 u32 mask, u32 val, unsigned long timeout)
1331 timeout = jiffies + msecs_to_jiffies(timeout);
1333 while (time_after(timeout, jiffies)) {
1334 value = tegra_pmc_readl(pmc, offset);
1335 if ((value & mask) == val)
1338 usleep_range(250, 1000);
1344 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1347 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1351 * tegra_io_pad_power_enable() - enable power to I/O pad
1352 * @id: Tegra I/O pad ID for which to enable power
1354 * Returns: 0 on success or a negative error code on failure.
1356 int tegra_io_pad_power_enable(enum tegra_io_pad id)
1358 unsigned long request, status;
1362 mutex_lock(&pmc->powergates_lock);
1364 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1366 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1370 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1372 err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1374 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1378 tegra_io_pad_unprepare(pmc);
1381 mutex_unlock(&pmc->powergates_lock);
1384 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1387 * tegra_io_pad_power_disable() - disable power to I/O pad
1388 * @id: Tegra I/O pad ID for which to disable power
1390 * Returns: 0 on success or a negative error code on failure.
1392 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1394 unsigned long request, status;
1398 mutex_lock(&pmc->powergates_lock);
1400 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1402 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1406 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1408 err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1410 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1414 tegra_io_pad_unprepare(pmc);
1417 mutex_unlock(&pmc->powergates_lock);
1420 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1422 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1424 unsigned long request, status;
1428 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status,
1433 value = tegra_pmc_readl(pmc, status);
1435 return !(value & mask);
1438 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1441 const struct tegra_io_pad_soc *pad;
1444 pad = tegra_io_pad_find(pmc, id);
1448 if (pad->voltage == UINT_MAX)
1451 mutex_lock(&pmc->powergates_lock);
1453 if (pmc->soc->has_impl_33v_pwr) {
1454 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1456 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1457 value &= ~BIT(pad->voltage);
1459 value |= BIT(pad->voltage);
1461 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1463 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1464 value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1465 value |= BIT(pad->voltage);
1466 tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1468 /* update I/O voltage */
1469 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1471 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1472 value &= ~BIT(pad->voltage);
1474 value |= BIT(pad->voltage);
1476 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1479 mutex_unlock(&pmc->powergates_lock);
1481 usleep_range(100, 250);
1486 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1488 const struct tegra_io_pad_soc *pad;
1491 pad = tegra_io_pad_find(pmc, id);
1495 if (pad->voltage == UINT_MAX)
1498 if (pmc->soc->has_impl_33v_pwr)
1499 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1501 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1503 if ((value & BIT(pad->voltage)) == 0)
1504 return TEGRA_IO_PAD_VOLTAGE_1V8;
1506 return TEGRA_IO_PAD_VOLTAGE_3V3;
1510 * tegra_io_rail_power_on() - enable power to I/O rail
1511 * @id: Tegra I/O pad ID for which to enable power
1513 * See also: tegra_io_pad_power_enable()
1515 int tegra_io_rail_power_on(unsigned int id)
1517 return tegra_io_pad_power_enable(id);
1519 EXPORT_SYMBOL(tegra_io_rail_power_on);
1522 * tegra_io_rail_power_off() - disable power to I/O rail
1523 * @id: Tegra I/O pad ID for which to disable power
1525 * See also: tegra_io_pad_power_disable()
1527 int tegra_io_rail_power_off(unsigned int id)
1529 return tegra_io_pad_power_disable(id);
1531 EXPORT_SYMBOL(tegra_io_rail_power_off);
1533 #ifdef CONFIG_PM_SLEEP
1534 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1536 return pmc->suspend_mode;
1539 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1541 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1544 pmc->suspend_mode = mode;
1547 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1549 unsigned long long rate = 0;
1554 case TEGRA_SUSPEND_LP1:
1558 case TEGRA_SUSPEND_LP2:
1566 if (WARN_ON_ONCE(rate == 0))
1569 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1570 do_div(ticks, USEC_PER_SEC);
1571 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1573 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1574 do_div(ticks, USEC_PER_SEC);
1575 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1577 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1578 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1579 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1580 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1584 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1586 u32 value, values[2];
1588 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1592 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1596 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1600 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1604 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1609 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1611 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1612 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1614 pmc->cpu_good_time = value;
1616 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1617 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1619 pmc->cpu_off_time = value;
1621 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1622 values, ARRAY_SIZE(values)))
1623 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1625 pmc->core_osc_time = values[0];
1626 pmc->core_pmu_time = values[1];
1628 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1629 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1631 pmc->core_off_time = value;
1633 pmc->corereq_high = of_property_read_bool(np,
1634 "nvidia,core-power-req-active-high");
1636 pmc->sysclkreq_high = of_property_read_bool(np,
1637 "nvidia,sys-clock-req-active-high");
1639 pmc->combined_req = of_property_read_bool(np,
1640 "nvidia,combined-power-req");
1642 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1643 "nvidia,cpu-pwr-good-en");
1645 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1646 ARRAY_SIZE(values)))
1647 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1648 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1650 pmc->lp0_vec_phys = values[0];
1651 pmc->lp0_vec_size = values[1];
1656 static void tegra_pmc_init(struct tegra_pmc *pmc)
1659 pmc->soc->init(pmc);
1662 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1664 static const char disabled[] = "emergency thermal reset disabled";
1665 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1666 struct device *dev = pmc->dev;
1667 struct device_node *np;
1668 u32 value, checksum;
1670 if (!pmc->soc->has_tsense_reset)
1673 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1675 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1679 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1680 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1684 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1685 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1689 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
1690 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1694 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
1695 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1699 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1702 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1703 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1704 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1706 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1707 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1708 tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
1710 value = PMC_SCRATCH55_RESET_TEGRA;
1711 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1712 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1713 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1716 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1717 * contain the checksum and are currently zero, so they are not added.
1719 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1720 + ((value >> 24) & 0xff);
1722 checksum = 0x100 - checksum;
1724 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1726 tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
1728 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1729 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1730 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1732 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1738 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)
1740 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1742 return pmc->soc->num_io_pads;
1745 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl,
1748 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
1750 return pmc->soc->io_pads[group].name;
1753 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,
1755 const unsigned int **pins,
1756 unsigned int *num_pins)
1758 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1760 *pins = &pmc->soc->io_pads[group].id;
1766 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {
1767 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count,
1768 .get_group_name = tegra_io_pad_pinctrl_get_group_name,
1769 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins,
1770 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1771 .dt_free_map = pinconf_generic_dt_free_map,
1774 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,
1775 unsigned int pin, unsigned long *config)
1777 enum pin_config_param param = pinconf_to_config_param(*config);
1778 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1779 const struct tegra_io_pad_soc *pad;
1783 pad = tegra_io_pad_find(pmc, pin);
1788 case PIN_CONFIG_POWER_SOURCE:
1789 ret = tegra_io_pad_get_voltage(pmc, pad->id);
1796 case PIN_CONFIG_LOW_POWER_MODE:
1797 ret = tegra_io_pad_is_powered(pmc, pad->id);
1808 *config = pinconf_to_config_packed(param, arg);
1813 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,
1814 unsigned int pin, unsigned long *configs,
1815 unsigned int num_configs)
1817 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1818 const struct tegra_io_pad_soc *pad;
1819 enum pin_config_param param;
1824 pad = tegra_io_pad_find(pmc, pin);
1828 for (i = 0; i < num_configs; ++i) {
1829 param = pinconf_to_config_param(configs[i]);
1830 arg = pinconf_to_config_argument(configs[i]);
1833 case PIN_CONFIG_LOW_POWER_MODE:
1835 err = tegra_io_pad_power_disable(pad->id);
1837 err = tegra_io_pad_power_enable(pad->id);
1841 case PIN_CONFIG_POWER_SOURCE:
1842 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&
1843 arg != TEGRA_IO_PAD_VOLTAGE_3V3)
1845 err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
1857 static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
1858 .pin_config_get = tegra_io_pad_pinconf_get,
1859 .pin_config_set = tegra_io_pad_pinconf_set,
1863 static struct pinctrl_desc tegra_pmc_pctl_desc = {
1864 .pctlops = &tegra_io_pad_pinctrl_ops,
1865 .confops = &tegra_io_pad_pinconf_ops,
1868 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
1872 if (!pmc->soc->num_pin_descs)
1875 tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
1876 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
1877 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
1879 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
1881 if (IS_ERR(pmc->pctl_dev)) {
1882 err = PTR_ERR(pmc->pctl_dev);
1883 dev_err(pmc->dev, "failed to register pin controller: %d\n",
1891 static ssize_t reset_reason_show(struct device *dev,
1892 struct device_attribute *attr, char *buf)
1896 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1897 value &= pmc->soc->regs->rst_source_mask;
1898 value >>= pmc->soc->regs->rst_source_shift;
1900 if (WARN_ON(value >= pmc->soc->num_reset_sources))
1901 return sprintf(buf, "%s\n", "UNKNOWN");
1903 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
1906 static DEVICE_ATTR_RO(reset_reason);
1908 static ssize_t reset_level_show(struct device *dev,
1909 struct device_attribute *attr, char *buf)
1913 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1914 value &= pmc->soc->regs->rst_level_mask;
1915 value >>= pmc->soc->regs->rst_level_shift;
1917 if (WARN_ON(value >= pmc->soc->num_reset_levels))
1918 return sprintf(buf, "%s\n", "UNKNOWN");
1920 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
1923 static DEVICE_ATTR_RO(reset_level);
1925 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
1927 struct device *dev = pmc->dev;
1930 if (pmc->soc->reset_sources) {
1931 err = device_create_file(dev, &dev_attr_reset_reason);
1934 "failed to create attr \"reset_reason\": %d\n",
1938 if (pmc->soc->reset_levels) {
1939 err = device_create_file(dev, &dev_attr_reset_level);
1942 "failed to create attr \"reset_level\": %d\n",
1947 static int tegra_pmc_irq_translate(struct irq_domain *domain,
1948 struct irq_fwspec *fwspec,
1949 unsigned long *hwirq,
1952 if (WARN_ON(fwspec->param_count < 2))
1955 *hwirq = fwspec->param[0];
1956 *type = fwspec->param[1];
1961 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
1962 unsigned int num_irqs, void *data)
1964 struct tegra_pmc *pmc = domain->host_data;
1965 const struct tegra_pmc_soc *soc = pmc->soc;
1966 struct irq_fwspec *fwspec = data;
1970 if (WARN_ON(num_irqs > 1))
1973 for (i = 0; i < soc->num_wake_events; i++) {
1974 const struct tegra_wake_event *event = &soc->wake_events[i];
1976 if (fwspec->param_count == 2) {
1977 struct irq_fwspec spec;
1979 if (event->id != fwspec->param[0])
1982 err = irq_domain_set_hwirq_and_chip(domain, virq,
1988 spec.fwnode = &pmc->dev->of_node->fwnode;
1989 spec.param_count = 3;
1990 spec.param[0] = GIC_SPI;
1991 spec.param[1] = event->irq;
1992 spec.param[2] = fwspec->param[1];
1994 err = irq_domain_alloc_irqs_parent(domain, virq,
2000 if (fwspec->param_count == 3) {
2001 if (event->gpio.instance != fwspec->param[0] ||
2002 event->gpio.pin != fwspec->param[1])
2005 err = irq_domain_set_hwirq_and_chip(domain, virq,
2009 /* GPIO hierarchies stop at the PMC level */
2010 if (!err && domain->parent)
2011 err = irq_domain_disconnect_hierarchy(domain->parent,
2017 /* If there is no wake-up event, there is no PMC mapping */
2018 if (i == soc->num_wake_events)
2019 err = irq_domain_disconnect_hierarchy(domain, virq);
2024 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
2025 .translate = tegra_pmc_irq_translate,
2026 .alloc = tegra_pmc_irq_alloc,
2029 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2031 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2032 unsigned int offset, bit;
2035 offset = data->hwirq / 32;
2036 bit = data->hwirq % 32;
2038 /* clear wake status */
2039 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
2040 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
2042 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
2043 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
2045 /* enable PMC wake */
2046 if (data->hwirq >= 32)
2047 offset = PMC_WAKE2_MASK;
2049 offset = PMC_WAKE_MASK;
2051 value = tegra_pmc_readl(pmc, offset);
2058 tegra_pmc_writel(pmc, value, offset);
2063 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2065 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2066 unsigned int offset, bit;
2069 offset = data->hwirq / 32;
2070 bit = data->hwirq % 32;
2072 if (data->hwirq >= 32)
2073 offset = PMC_WAKE2_LEVEL;
2075 offset = PMC_WAKE_LEVEL;
2077 value = tegra_pmc_readl(pmc, offset);
2080 case IRQ_TYPE_EDGE_RISING:
2081 case IRQ_TYPE_LEVEL_HIGH:
2085 case IRQ_TYPE_EDGE_FALLING:
2086 case IRQ_TYPE_LEVEL_LOW:
2090 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2098 tegra_pmc_writel(pmc, value, offset);
2103 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2105 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2106 unsigned int offset, bit;
2109 offset = data->hwirq / 32;
2110 bit = data->hwirq % 32;
2112 /* clear wake status */
2113 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
2115 /* route wake to tier 2 */
2116 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2119 value &= ~(1 << bit);
2123 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2125 /* enable wakeup event */
2126 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
2131 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2133 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2136 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2139 case IRQ_TYPE_EDGE_RISING:
2140 case IRQ_TYPE_LEVEL_HIGH:
2141 value |= WAKE_AOWAKE_CNTRL_LEVEL;
2144 case IRQ_TYPE_EDGE_FALLING:
2145 case IRQ_TYPE_LEVEL_LOW:
2146 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
2149 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2150 value ^= WAKE_AOWAKE_CNTRL_LEVEL;
2157 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2162 static void tegra_irq_mask_parent(struct irq_data *data)
2164 if (data->parent_data)
2165 irq_chip_mask_parent(data);
2168 static void tegra_irq_unmask_parent(struct irq_data *data)
2170 if (data->parent_data)
2171 irq_chip_unmask_parent(data);
2174 static void tegra_irq_eoi_parent(struct irq_data *data)
2176 if (data->parent_data)
2177 irq_chip_eoi_parent(data);
2180 static int tegra_irq_set_affinity_parent(struct irq_data *data,
2181 const struct cpumask *dest,
2184 if (data->parent_data)
2185 return irq_chip_set_affinity_parent(data, dest, force);
2190 static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
2192 struct irq_domain *parent = NULL;
2193 struct device_node *np;
2195 np = of_irq_find_parent(pmc->dev->of_node);
2197 parent = irq_find_host(np);
2204 pmc->irq.name = dev_name(pmc->dev);
2205 pmc->irq.irq_mask = tegra_irq_mask_parent;
2206 pmc->irq.irq_unmask = tegra_irq_unmask_parent;
2207 pmc->irq.irq_eoi = tegra_irq_eoi_parent;
2208 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent;
2209 pmc->irq.irq_set_type = pmc->soc->irq_set_type;
2210 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake;
2212 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
2213 &tegra_pmc_irq_domain_ops, pmc);
2215 dev_err(pmc->dev, "failed to allocate domain\n");
2222 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
2223 unsigned long action, void *ptr)
2225 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb);
2226 struct clk_notifier_data *data = ptr;
2229 case PRE_RATE_CHANGE:
2230 mutex_lock(&pmc->powergates_lock);
2233 case POST_RATE_CHANGE:
2234 pmc->rate = data->new_rate;
2237 case ABORT_RATE_CHANGE:
2238 mutex_unlock(&pmc->powergates_lock);
2243 return notifier_from_errno(-EINVAL);
2249 static void pmc_clk_fence_udelay(u32 offset)
2251 tegra_pmc_readl(pmc, offset);
2252 /* pmc clk propagation delay 2 us */
2256 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
2258 struct pmc_clk *clk = to_pmc_clk(hw);
2261 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
2262 val &= PMC_CLK_OUT_MUX_MASK;
2267 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
2269 struct pmc_clk *clk = to_pmc_clk(hw);
2272 val = tegra_pmc_readl(pmc, clk->offs);
2273 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift);
2274 val |= index << clk->mux_shift;
2275 tegra_pmc_writel(pmc, val, clk->offs);
2276 pmc_clk_fence_udelay(clk->offs);
2281 static int pmc_clk_is_enabled(struct clk_hw *hw)
2283 struct pmc_clk *clk = to_pmc_clk(hw);
2286 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);
2291 static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
2295 val = tegra_pmc_readl(pmc, offs);
2296 val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
2297 tegra_pmc_writel(pmc, val, offs);
2298 pmc_clk_fence_udelay(offs);
2301 static int pmc_clk_enable(struct clk_hw *hw)
2303 struct pmc_clk *clk = to_pmc_clk(hw);
2305 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1);
2310 static void pmc_clk_disable(struct clk_hw *hw)
2312 struct pmc_clk *clk = to_pmc_clk(hw);
2314 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0);
2317 static const struct clk_ops pmc_clk_ops = {
2318 .get_parent = pmc_clk_mux_get_parent,
2319 .set_parent = pmc_clk_mux_set_parent,
2320 .determine_rate = __clk_mux_determine_rate,
2321 .is_enabled = pmc_clk_is_enabled,
2322 .enable = pmc_clk_enable,
2323 .disable = pmc_clk_disable,
2327 tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
2328 const struct pmc_clk_init_data *data,
2329 unsigned long offset)
2331 struct clk_init_data init;
2332 struct pmc_clk *pmc_clk;
2334 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);
2336 return ERR_PTR(-ENOMEM);
2338 init.name = data->name;
2339 init.ops = &pmc_clk_ops;
2340 init.parent_names = data->parents;
2341 init.num_parents = data->num_parents;
2342 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
2343 CLK_SET_PARENT_GATE;
2345 pmc_clk->hw.init = &init;
2346 pmc_clk->offs = offset;
2347 pmc_clk->mux_shift = data->mux_shift;
2348 pmc_clk->force_en_shift = data->force_en_shift;
2350 return clk_register(NULL, &pmc_clk->hw);
2353 static int pmc_clk_gate_is_enabled(struct clk_hw *hw)
2355 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2357 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
2360 static int pmc_clk_gate_enable(struct clk_hw *hw)
2362 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2364 pmc_clk_set_state(gate->offs, gate->shift, 1);
2369 static void pmc_clk_gate_disable(struct clk_hw *hw)
2371 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2373 pmc_clk_set_state(gate->offs, gate->shift, 0);
2376 static const struct clk_ops pmc_clk_gate_ops = {
2377 .is_enabled = pmc_clk_gate_is_enabled,
2378 .enable = pmc_clk_gate_enable,
2379 .disable = pmc_clk_gate_disable,
2383 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name,
2384 const char *parent_name, unsigned long offset,
2387 struct clk_init_data init;
2388 struct pmc_clk_gate *gate;
2390 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL);
2392 return ERR_PTR(-ENOMEM);
2395 init.ops = &pmc_clk_gate_ops;
2396 init.parent_names = &parent_name;
2397 init.num_parents = 1;
2400 gate->hw.init = &init;
2401 gate->offs = offset;
2402 gate->shift = shift;
2404 return clk_register(NULL, &gate->hw);
2407 static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
2408 struct device_node *np)
2411 struct clk_onecell_data *clk_data;
2412 unsigned int num_clks;
2415 num_clks = pmc->soc->num_pmc_clks;
2416 if (pmc->soc->has_blink_output)
2422 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL);
2426 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX,
2427 sizeof(*clk_data->clks), GFP_KERNEL);
2428 if (!clk_data->clks)
2431 clk_data->clk_num = TEGRA_PMC_CLK_MAX;
2433 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
2434 clk_data->clks[i] = ERR_PTR(-ENOENT);
2436 for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
2437 const struct pmc_clk_init_data *data;
2439 data = pmc->soc->pmc_clks_data + i;
2441 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL);
2443 dev_warn(pmc->dev, "unable to register clock %s: %d\n",
2444 data->name, PTR_ERR_OR_ZERO(clk));
2448 err = clk_register_clkdev(clk, data->name, NULL);
2451 "unable to register %s clock lookup: %d\n",
2456 clk_data->clks[data->clk_id] = clk;
2459 if (pmc->soc->has_blink_output) {
2460 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);
2461 clk = tegra_pmc_clk_gate_register(pmc,
2462 "pmc_blink_override",
2465 PMC_DPD_PADS_ORIDE_BLINK);
2468 "unable to register pmc_blink_override: %d\n",
2469 PTR_ERR_OR_ZERO(clk));
2473 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink",
2474 "pmc_blink_override",
2476 PMC_CNTRL_BLINK_EN);
2479 "unable to register pmc_blink: %d\n",
2480 PTR_ERR_OR_ZERO(clk));
2484 err = clk_register_clkdev(clk, "pmc_blink", NULL);
2487 "unable to register pmc_blink lookup: %d\n",
2492 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk;
2495 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
2497 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n",
2501 static int tegra_pmc_probe(struct platform_device *pdev)
2504 struct resource *res;
2508 * Early initialisation should have configured an initial
2509 * register mapping and setup the soc data pointer. If these
2510 * are not valid then something went badly wrong!
2512 if (WARN_ON(!pmc->base || !pmc->soc))
2515 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2519 /* take over the memory region from the early initialization */
2520 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2521 base = devm_ioremap_resource(&pdev->dev, res);
2523 return PTR_ERR(base);
2525 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
2527 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2528 if (IS_ERR(pmc->wake))
2529 return PTR_ERR(pmc->wake);
2534 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
2536 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2537 if (IS_ERR(pmc->aotag))
2538 return PTR_ERR(pmc->aotag);
2543 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
2545 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2546 if (IS_ERR(pmc->scratch))
2547 return PTR_ERR(pmc->scratch);
2549 pmc->scratch = base;
2552 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
2553 if (IS_ERR(pmc->clk)) {
2554 err = PTR_ERR(pmc->clk);
2556 if (err != -ENOENT) {
2557 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
2565 * PCLK clock rate can't be retrieved using CLK API because it
2566 * causes lockup if CPU enters LP2 idle state from some other
2567 * CLK notifier, hence we're caching the rate's value locally.
2570 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;
2571 err = clk_notifier_register(pmc->clk, &pmc->clk_nb);
2574 "failed to register clk notifier\n");
2578 pmc->rate = clk_get_rate(pmc->clk);
2581 pmc->dev = &pdev->dev;
2583 tegra_pmc_init(pmc);
2585 tegra_pmc_init_tsense_reset(pmc);
2587 tegra_pmc_reset_sysfs_init(pmc);
2589 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2590 err = tegra_powergate_debugfs_init();
2595 err = register_restart_handler(&tegra_pmc_restart_handler);
2597 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
2599 goto cleanup_debugfs;
2602 err = tegra_pmc_pinctrl_init(pmc);
2604 goto cleanup_restart_handler;
2606 err = tegra_powergate_init(pmc, pdev->dev.of_node);
2608 goto cleanup_powergates;
2610 err = tegra_pmc_irq_init(pmc);
2612 goto cleanup_powergates;
2614 mutex_lock(&pmc->powergates_lock);
2617 mutex_unlock(&pmc->powergates_lock);
2619 tegra_pmc_clock_register(pmc, pdev->dev.of_node);
2620 platform_set_drvdata(pdev, pmc);
2625 tegra_powergate_remove_all(pdev->dev.of_node);
2626 cleanup_restart_handler:
2627 unregister_restart_handler(&tegra_pmc_restart_handler);
2629 debugfs_remove(pmc->debugfs);
2631 device_remove_file(&pdev->dev, &dev_attr_reset_reason);
2632 device_remove_file(&pdev->dev, &dev_attr_reset_level);
2633 clk_notifier_unregister(pmc->clk, &pmc->clk_nb);
2638 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
2639 static int tegra_pmc_suspend(struct device *dev)
2641 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2643 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
2648 static int tegra_pmc_resume(struct device *dev)
2650 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2652 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
2657 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
2661 static const char * const tegra20_powergates[] = {
2662 [TEGRA_POWERGATE_CPU] = "cpu",
2663 [TEGRA_POWERGATE_3D] = "3d",
2664 [TEGRA_POWERGATE_VENC] = "venc",
2665 [TEGRA_POWERGATE_VDEC] = "vdec",
2666 [TEGRA_POWERGATE_PCIE] = "pcie",
2667 [TEGRA_POWERGATE_L2] = "l2",
2668 [TEGRA_POWERGATE_MPE] = "mpe",
2671 static const struct tegra_pmc_regs tegra20_pmc_regs = {
2674 .dpd_status = 0x1bc,
2676 .dpd2_status = 0x1c4,
2677 .rst_status = 0x1b4,
2678 .rst_source_shift = 0x0,
2679 .rst_source_mask = 0x7,
2680 .rst_level_shift = 0x0,
2681 .rst_level_mask = 0x0,
2684 static void tegra20_pmc_init(struct tegra_pmc *pmc)
2686 u32 value, osc, pmu, off;
2688 /* Always enable CPU power request */
2689 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2690 value |= PMC_CNTRL_CPU_PWRREQ_OE;
2691 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2693 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2695 if (pmc->sysclkreq_high)
2696 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
2698 value |= PMC_CNTRL_SYSCLK_POLARITY;
2700 if (pmc->corereq_high)
2701 value &= ~PMC_CNTRL_PWRREQ_POLARITY;
2703 value |= PMC_CNTRL_PWRREQ_POLARITY;
2705 /* configure the output polarity while the request is tristated */
2706 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2708 /* now enable the request */
2709 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2710 value |= PMC_CNTRL_SYSCLK_OE;
2711 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2713 /* program core timings which are applicable only for suspend state */
2714 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) {
2715 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);
2716 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);
2717 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);
2718 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
2719 PMC_COREPWRGOOD_TIMER);
2720 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
2724 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
2725 struct device_node *np,
2730 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2733 value |= PMC_CNTRL_INTR_POLARITY;
2735 value &= ~PMC_CNTRL_INTR_POLARITY;
2737 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2740 static const struct tegra_pmc_soc tegra20_pmc_soc = {
2741 .num_powergates = ARRAY_SIZE(tegra20_powergates),
2742 .powergates = tegra20_powergates,
2743 .num_cpu_powergates = 0,
2744 .cpu_powergates = NULL,
2745 .has_tsense_reset = false,
2746 .has_gpu_clamps = false,
2747 .needs_mbist_war = false,
2748 .has_impl_33v_pwr = false,
2749 .maybe_tz_only = false,
2754 .regs = &tegra20_pmc_regs,
2755 .init = tegra20_pmc_init,
2756 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2757 .powergate_set = tegra20_powergate_set,
2758 .reset_sources = NULL,
2759 .num_reset_sources = 0,
2760 .reset_levels = NULL,
2761 .num_reset_levels = 0,
2762 .pmc_clks_data = NULL,
2764 .has_blink_output = true,
2767 static const char * const tegra30_powergates[] = {
2768 [TEGRA_POWERGATE_CPU] = "cpu0",
2769 [TEGRA_POWERGATE_3D] = "3d0",
2770 [TEGRA_POWERGATE_VENC] = "venc",
2771 [TEGRA_POWERGATE_VDEC] = "vdec",
2772 [TEGRA_POWERGATE_PCIE] = "pcie",
2773 [TEGRA_POWERGATE_L2] = "l2",
2774 [TEGRA_POWERGATE_MPE] = "mpe",
2775 [TEGRA_POWERGATE_HEG] = "heg",
2776 [TEGRA_POWERGATE_SATA] = "sata",
2777 [TEGRA_POWERGATE_CPU1] = "cpu1",
2778 [TEGRA_POWERGATE_CPU2] = "cpu2",
2779 [TEGRA_POWERGATE_CPU3] = "cpu3",
2780 [TEGRA_POWERGATE_CELP] = "celp",
2781 [TEGRA_POWERGATE_3D1] = "3d1",
2784 static const u8 tegra30_cpu_powergates[] = {
2785 TEGRA_POWERGATE_CPU,
2786 TEGRA_POWERGATE_CPU1,
2787 TEGRA_POWERGATE_CPU2,
2788 TEGRA_POWERGATE_CPU3,
2791 static const char * const tegra30_reset_sources[] = {
2799 static const struct tegra_pmc_soc tegra30_pmc_soc = {
2800 .num_powergates = ARRAY_SIZE(tegra30_powergates),
2801 .powergates = tegra30_powergates,
2802 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
2803 .cpu_powergates = tegra30_cpu_powergates,
2804 .has_tsense_reset = true,
2805 .has_gpu_clamps = false,
2806 .needs_mbist_war = false,
2807 .has_impl_33v_pwr = false,
2808 .maybe_tz_only = false,
2813 .regs = &tegra20_pmc_regs,
2814 .init = tegra20_pmc_init,
2815 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2816 .powergate_set = tegra20_powergate_set,
2817 .reset_sources = tegra30_reset_sources,
2818 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2819 .reset_levels = NULL,
2820 .num_reset_levels = 0,
2821 .pmc_clks_data = tegra_pmc_clks_data,
2822 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
2823 .has_blink_output = true,
2826 static const char * const tegra114_powergates[] = {
2827 [TEGRA_POWERGATE_CPU] = "crail",
2828 [TEGRA_POWERGATE_3D] = "3d",
2829 [TEGRA_POWERGATE_VENC] = "venc",
2830 [TEGRA_POWERGATE_VDEC] = "vdec",
2831 [TEGRA_POWERGATE_MPE] = "mpe",
2832 [TEGRA_POWERGATE_HEG] = "heg",
2833 [TEGRA_POWERGATE_CPU1] = "cpu1",
2834 [TEGRA_POWERGATE_CPU2] = "cpu2",
2835 [TEGRA_POWERGATE_CPU3] = "cpu3",
2836 [TEGRA_POWERGATE_CELP] = "celp",
2837 [TEGRA_POWERGATE_CPU0] = "cpu0",
2838 [TEGRA_POWERGATE_C0NC] = "c0nc",
2839 [TEGRA_POWERGATE_C1NC] = "c1nc",
2840 [TEGRA_POWERGATE_DIS] = "dis",
2841 [TEGRA_POWERGATE_DISB] = "disb",
2842 [TEGRA_POWERGATE_XUSBA] = "xusba",
2843 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2844 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2847 static const u8 tegra114_cpu_powergates[] = {
2848 TEGRA_POWERGATE_CPU0,
2849 TEGRA_POWERGATE_CPU1,
2850 TEGRA_POWERGATE_CPU2,
2851 TEGRA_POWERGATE_CPU3,
2854 static const struct tegra_pmc_soc tegra114_pmc_soc = {
2855 .num_powergates = ARRAY_SIZE(tegra114_powergates),
2856 .powergates = tegra114_powergates,
2857 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
2858 .cpu_powergates = tegra114_cpu_powergates,
2859 .has_tsense_reset = true,
2860 .has_gpu_clamps = false,
2861 .needs_mbist_war = false,
2862 .has_impl_33v_pwr = false,
2863 .maybe_tz_only = false,
2868 .regs = &tegra20_pmc_regs,
2869 .init = tegra20_pmc_init,
2870 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2871 .powergate_set = tegra114_powergate_set,
2872 .reset_sources = tegra30_reset_sources,
2873 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2874 .reset_levels = NULL,
2875 .num_reset_levels = 0,
2876 .pmc_clks_data = tegra_pmc_clks_data,
2877 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
2878 .has_blink_output = true,
2881 static const char * const tegra124_powergates[] = {
2882 [TEGRA_POWERGATE_CPU] = "crail",
2883 [TEGRA_POWERGATE_3D] = "3d",
2884 [TEGRA_POWERGATE_VENC] = "venc",
2885 [TEGRA_POWERGATE_PCIE] = "pcie",
2886 [TEGRA_POWERGATE_VDEC] = "vdec",
2887 [TEGRA_POWERGATE_MPE] = "mpe",
2888 [TEGRA_POWERGATE_HEG] = "heg",
2889 [TEGRA_POWERGATE_SATA] = "sata",
2890 [TEGRA_POWERGATE_CPU1] = "cpu1",
2891 [TEGRA_POWERGATE_CPU2] = "cpu2",
2892 [TEGRA_POWERGATE_CPU3] = "cpu3",
2893 [TEGRA_POWERGATE_CELP] = "celp",
2894 [TEGRA_POWERGATE_CPU0] = "cpu0",
2895 [TEGRA_POWERGATE_C0NC] = "c0nc",
2896 [TEGRA_POWERGATE_C1NC] = "c1nc",
2897 [TEGRA_POWERGATE_SOR] = "sor",
2898 [TEGRA_POWERGATE_DIS] = "dis",
2899 [TEGRA_POWERGATE_DISB] = "disb",
2900 [TEGRA_POWERGATE_XUSBA] = "xusba",
2901 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2902 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2903 [TEGRA_POWERGATE_VIC] = "vic",
2904 [TEGRA_POWERGATE_IRAM] = "iram",
2907 static const u8 tegra124_cpu_powergates[] = {
2908 TEGRA_POWERGATE_CPU0,
2909 TEGRA_POWERGATE_CPU1,
2910 TEGRA_POWERGATE_CPU2,
2911 TEGRA_POWERGATE_CPU3,
2914 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \
2915 ((struct tegra_io_pad_soc) { \
2918 .voltage = (_voltage), \
2922 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \
2923 ((struct pinctrl_pin_desc) { \
2928 #define TEGRA124_IO_PAD_TABLE(_pad) \
2929 /* .id .dpd .voltage .name */ \
2930 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
2931 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \
2932 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \
2933 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \
2934 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
2935 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \
2936 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \
2937 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
2938 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
2939 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
2940 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
2941 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
2942 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
2943 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \
2944 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
2945 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2946 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \
2947 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
2948 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
2949 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
2950 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
2951 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \
2952 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \
2953 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \
2954 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \
2955 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
2956 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
2957 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
2958 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
2959 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias")
2961 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
2962 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD)
2965 static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
2966 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
2969 static const struct tegra_pmc_soc tegra124_pmc_soc = {
2970 .num_powergates = ARRAY_SIZE(tegra124_powergates),
2971 .powergates = tegra124_powergates,
2972 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
2973 .cpu_powergates = tegra124_cpu_powergates,
2974 .has_tsense_reset = true,
2975 .has_gpu_clamps = true,
2976 .needs_mbist_war = false,
2977 .has_impl_33v_pwr = false,
2978 .maybe_tz_only = false,
2979 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
2980 .io_pads = tegra124_io_pads,
2981 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
2982 .pin_descs = tegra124_pin_descs,
2983 .regs = &tegra20_pmc_regs,
2984 .init = tegra20_pmc_init,
2985 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2986 .powergate_set = tegra114_powergate_set,
2987 .reset_sources = tegra30_reset_sources,
2988 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2989 .reset_levels = NULL,
2990 .num_reset_levels = 0,
2991 .pmc_clks_data = tegra_pmc_clks_data,
2992 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
2993 .has_blink_output = true,
2996 static const char * const tegra210_powergates[] = {
2997 [TEGRA_POWERGATE_CPU] = "crail",
2998 [TEGRA_POWERGATE_3D] = "3d",
2999 [TEGRA_POWERGATE_VENC] = "venc",
3000 [TEGRA_POWERGATE_PCIE] = "pcie",
3001 [TEGRA_POWERGATE_MPE] = "mpe",
3002 [TEGRA_POWERGATE_SATA] = "sata",
3003 [TEGRA_POWERGATE_CPU1] = "cpu1",
3004 [TEGRA_POWERGATE_CPU2] = "cpu2",
3005 [TEGRA_POWERGATE_CPU3] = "cpu3",
3006 [TEGRA_POWERGATE_CPU0] = "cpu0",
3007 [TEGRA_POWERGATE_C0NC] = "c0nc",
3008 [TEGRA_POWERGATE_SOR] = "sor",
3009 [TEGRA_POWERGATE_DIS] = "dis",
3010 [TEGRA_POWERGATE_DISB] = "disb",
3011 [TEGRA_POWERGATE_XUSBA] = "xusba",
3012 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3013 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3014 [TEGRA_POWERGATE_VIC] = "vic",
3015 [TEGRA_POWERGATE_IRAM] = "iram",
3016 [TEGRA_POWERGATE_NVDEC] = "nvdec",
3017 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
3018 [TEGRA_POWERGATE_AUD] = "aud",
3019 [TEGRA_POWERGATE_DFD] = "dfd",
3020 [TEGRA_POWERGATE_VE2] = "ve2",
3023 static const u8 tegra210_cpu_powergates[] = {
3024 TEGRA_POWERGATE_CPU0,
3025 TEGRA_POWERGATE_CPU1,
3026 TEGRA_POWERGATE_CPU2,
3027 TEGRA_POWERGATE_CPU3,
3030 #define TEGRA210_IO_PAD_TABLE(_pad) \
3031 /* .id .dpd .voltage .name */ \
3032 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \
3033 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \
3034 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \
3035 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3036 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3037 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \
3038 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \
3039 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \
3040 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \
3041 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \
3042 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \
3043 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \
3044 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \
3045 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3046 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
3047 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
3048 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
3049 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \
3050 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \
3051 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \
3052 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
3053 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3054 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
3055 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3056 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
3057 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
3058 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3059 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \
3060 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \
3061 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \
3062 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \
3063 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \
3064 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \
3065 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3066 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3067 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3068 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \
3069 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias")
3071 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
3072 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD)
3075 static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
3076 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3079 static const char * const tegra210_reset_sources[] = {
3088 static const struct tegra_wake_event tegra210_wake_events[] = {
3089 TEGRA_WAKE_IRQ("rtc", 16, 2),
3090 TEGRA_WAKE_IRQ("pmu", 51, 86),
3093 static const struct tegra_pmc_soc tegra210_pmc_soc = {
3094 .num_powergates = ARRAY_SIZE(tegra210_powergates),
3095 .powergates = tegra210_powergates,
3096 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
3097 .cpu_powergates = tegra210_cpu_powergates,
3098 .has_tsense_reset = true,
3099 .has_gpu_clamps = true,
3100 .needs_mbist_war = true,
3101 .has_impl_33v_pwr = false,
3102 .maybe_tz_only = true,
3103 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
3104 .io_pads = tegra210_io_pads,
3105 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
3106 .pin_descs = tegra210_pin_descs,
3107 .regs = &tegra20_pmc_regs,
3108 .init = tegra20_pmc_init,
3109 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3110 .powergate_set = tegra114_powergate_set,
3111 .irq_set_wake = tegra210_pmc_irq_set_wake,
3112 .irq_set_type = tegra210_pmc_irq_set_type,
3113 .reset_sources = tegra210_reset_sources,
3114 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
3115 .reset_levels = NULL,
3116 .num_reset_levels = 0,
3117 .num_wake_events = ARRAY_SIZE(tegra210_wake_events),
3118 .wake_events = tegra210_wake_events,
3119 .pmc_clks_data = tegra_pmc_clks_data,
3120 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3121 .has_blink_output = true,
3124 #define TEGRA186_IO_PAD_TABLE(_pad) \
3125 /* .id .dpd .voltage .name */ \
3126 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3127 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3128 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3129 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3130 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3131 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3132 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3133 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3134 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3135 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3136 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3137 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \
3138 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3139 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3140 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3141 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
3142 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3143 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3144 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3145 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \
3146 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
3147 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
3148 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \
3149 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \
3150 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \
3151 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
3152 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
3153 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
3154 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
3155 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
3156 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
3157 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \
3158 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
3159 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3160 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3161 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
3162 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3163 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3165 static const struct tegra_io_pad_soc tegra186_io_pads[] = {
3166 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD)
3169 static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
3170 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3173 static const struct tegra_pmc_regs tegra186_pmc_regs = {
3178 .dpd2_status = 0x80,
3180 .rst_source_shift = 0x2,
3181 .rst_source_mask = 0x3c,
3182 .rst_level_shift = 0x0,
3183 .rst_level_mask = 0x3,
3186 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3187 struct device_node *np,
3190 struct resource regs;
3195 index = of_property_match_string(np, "reg-names", "wake");
3197 dev_err(pmc->dev, "failed to find PMC wake registers\n");
3201 of_address_to_resource(np, index, ®s);
3203 wake = ioremap(regs.start, resource_size(®s));
3205 dev_err(pmc->dev, "failed to map PMC wake registers\n");
3209 value = readl(wake + WAKE_AOWAKE_CTRL);
3212 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
3214 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
3216 writel(value, wake + WAKE_AOWAKE_CTRL);
3221 static const char * const tegra186_reset_sources[] = {
3239 static const char * const tegra186_reset_levels[] = {
3240 "L0", "L1", "L2", "WARM"
3243 static const struct tegra_wake_event tegra186_wake_events[] = {
3244 TEGRA_WAKE_IRQ("pmu", 24, 209),
3245 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
3246 TEGRA_WAKE_IRQ("rtc", 73, 10),
3249 static const struct tegra_pmc_soc tegra186_pmc_soc = {
3250 .num_powergates = 0,
3252 .num_cpu_powergates = 0,
3253 .cpu_powergates = NULL,
3254 .has_tsense_reset = false,
3255 .has_gpu_clamps = false,
3256 .needs_mbist_war = false,
3257 .has_impl_33v_pwr = true,
3258 .maybe_tz_only = false,
3259 .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
3260 .io_pads = tegra186_io_pads,
3261 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
3262 .pin_descs = tegra186_pin_descs,
3263 .regs = &tegra186_pmc_regs,
3265 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3266 .irq_set_wake = tegra186_pmc_irq_set_wake,
3267 .irq_set_type = tegra186_pmc_irq_set_type,
3268 .reset_sources = tegra186_reset_sources,
3269 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
3270 .reset_levels = tegra186_reset_levels,
3271 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3272 .num_wake_events = ARRAY_SIZE(tegra186_wake_events),
3273 .wake_events = tegra186_wake_events,
3274 .pmc_clks_data = NULL,
3276 .has_blink_output = false,
3279 #define TEGRA194_IO_PAD_TABLE(_pad) \
3280 /* .id .dpd .voltage .name */ \
3281 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3282 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3283 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3284 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3285 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3286 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3287 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3288 _pad(TEGRA_IO_PAD_EQOS, 8, UINT_MAX, "eqos"), \
3289 _pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \
3290 _pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \
3291 _pad(TEGRA_IO_PAD_DAP3, 11, UINT_MAX, "dap3"), \
3292 _pad(TEGRA_IO_PAD_DAP5, 12, UINT_MAX, "dap5"), \
3293 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3294 _pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \
3295 _pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \
3296 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3297 _pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \
3298 _pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \
3299 _pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \
3300 _pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \
3301 _pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \
3302 _pad(TEGRA_IO_PAD_UART4, 23, UINT_MAX, "uart4"), \
3303 _pad(TEGRA_IO_PAD_UART5, 24, UINT_MAX, "uart5"), \
3304 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
3305 _pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \
3306 _pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \
3307 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3308 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3309 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3310 _pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \
3311 _pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \
3312 _pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \
3313 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
3314 _pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \
3315 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
3316 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
3317 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
3318 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
3319 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
3320 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
3321 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
3322 _pad(TEGRA_IO_PAD_CSIG, 50, UINT_MAX, "csig"), \
3323 _pad(TEGRA_IO_PAD_CSIH, 51, UINT_MAX, "csih"), \
3324 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
3325 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3326 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3327 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
3328 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3329 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3331 static const struct tegra_io_pad_soc tegra194_io_pads[] = {
3332 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PAD)
3335 static const struct pinctrl_pin_desc tegra194_pin_descs[] = {
3336 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3339 static const struct tegra_pmc_regs tegra194_pmc_regs = {
3344 .dpd2_status = 0x80,
3346 .rst_source_shift = 0x2,
3347 .rst_source_mask = 0x7c,
3348 .rst_level_shift = 0x0,
3349 .rst_level_mask = 0x3,
3352 static const char * const tegra194_reset_sources[] = {
3376 static const struct tegra_wake_event tegra194_wake_events[] = {
3377 TEGRA_WAKE_IRQ("pmu", 24, 209),
3378 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
3379 TEGRA_WAKE_IRQ("rtc", 73, 10),
3382 static const struct tegra_pmc_soc tegra194_pmc_soc = {
3383 .num_powergates = 0,
3385 .num_cpu_powergates = 0,
3386 .cpu_powergates = NULL,
3387 .has_tsense_reset = false,
3388 .has_gpu_clamps = false,
3389 .needs_mbist_war = false,
3390 .has_impl_33v_pwr = true,
3391 .maybe_tz_only = false,
3392 .num_io_pads = ARRAY_SIZE(tegra194_io_pads),
3393 .io_pads = tegra194_io_pads,
3394 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs),
3395 .pin_descs = tegra194_pin_descs,
3396 .regs = &tegra194_pmc_regs,
3398 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3399 .irq_set_wake = tegra186_pmc_irq_set_wake,
3400 .irq_set_type = tegra186_pmc_irq_set_type,
3401 .reset_sources = tegra194_reset_sources,
3402 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources),
3403 .reset_levels = tegra186_reset_levels,
3404 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3405 .num_wake_events = ARRAY_SIZE(tegra194_wake_events),
3406 .wake_events = tegra194_wake_events,
3407 .pmc_clks_data = NULL,
3409 .has_blink_output = false,
3412 static const struct tegra_pmc_regs tegra234_pmc_regs = {
3419 .rst_source_shift = 0x2,
3420 .rst_source_mask = 0xfc,
3421 .rst_level_shift = 0x0,
3422 .rst_level_mask = 0x3,
3425 static const char * const tegra234_reset_sources[] = {
3449 static const struct tegra_pmc_soc tegra234_pmc_soc = {
3450 .num_powergates = 0,
3452 .num_cpu_powergates = 0,
3453 .cpu_powergates = NULL,
3454 .has_tsense_reset = false,
3455 .has_gpu_clamps = false,
3456 .needs_mbist_war = false,
3457 .has_impl_33v_pwr = true,
3458 .maybe_tz_only = false,
3463 .regs = &tegra234_pmc_regs,
3465 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3466 .irq_set_wake = tegra186_pmc_irq_set_wake,
3467 .irq_set_type = tegra186_pmc_irq_set_type,
3468 .reset_sources = tegra234_reset_sources,
3469 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources),
3470 .reset_levels = tegra186_reset_levels,
3471 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3472 .num_wake_events = 0,
3473 .wake_events = NULL,
3474 .pmc_clks_data = NULL,
3476 .has_blink_output = false,
3479 static const struct of_device_id tegra_pmc_match[] = {
3480 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
3481 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
3482 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
3483 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
3484 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
3485 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
3486 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
3487 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
3488 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
3492 static struct platform_driver tegra_pmc_driver = {
3494 .name = "tegra-pmc",
3495 .suppress_bind_attrs = true,
3496 .of_match_table = tegra_pmc_match,
3497 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
3498 .pm = &tegra_pmc_pm_ops,
3501 .probe = tegra_pmc_probe,
3503 builtin_platform_driver(tegra_pmc_driver);
3505 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
3509 saved = readl(pmc->base + pmc->soc->regs->scratch0);
3510 value = saved ^ 0xffffffff;
3512 if (value == 0xffffffff)
3515 /* write pattern and read it back */
3516 writel(value, pmc->base + pmc->soc->regs->scratch0);
3517 value = readl(pmc->base + pmc->soc->regs->scratch0);
3519 /* if we read all-zeroes, access is restricted to TZ only */
3521 pr_info("access to PMC is restricted to TZ\n");
3525 /* restore original value */
3526 writel(saved, pmc->base + pmc->soc->regs->scratch0);
3532 * Early initialization to allow access to registers in the very early boot
3535 static int __init tegra_pmc_early_init(void)
3537 const struct of_device_id *match;
3538 struct device_node *np;
3539 struct resource regs;
3543 mutex_init(&pmc->powergates_lock);
3545 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
3548 * Fall back to legacy initialization for 32-bit ARM only. All
3549 * 64-bit ARM device tree files for Tegra are required to have
3552 * This is for backwards-compatibility with old device trees
3553 * that didn't contain a PMC node. Note that in this case the
3554 * SoC data can't be matched and therefore powergating is
3557 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
3558 pr_warn("DT node not found, powergating disabled\n");
3560 regs.start = 0x7000e400;
3561 regs.end = 0x7000e7ff;
3562 regs.flags = IORESOURCE_MEM;
3564 pr_warn("Using memory region %pR\n", ®s);
3567 * At this point we're not running on Tegra, so play
3568 * nice with multi-platform kernels.
3574 * Extract information from the device tree if we've found a
3577 if (of_address_to_resource(np, 0, ®s) < 0) {
3578 pr_err("failed to get PMC registers\n");
3584 pmc->base = ioremap(regs.start, resource_size(®s));
3586 pr_err("failed to map PMC registers\n");
3592 pmc->soc = match->data;
3594 if (pmc->soc->maybe_tz_only)
3595 pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
3597 /* Create a bitmap of the available and valid partitions */
3598 for (i = 0; i < pmc->soc->num_powergates; i++)
3599 if (pmc->soc->powergates[i])
3600 set_bit(i, pmc->powergates_available);
3603 * Invert the interrupt polarity if a PMC device tree node
3604 * exists and contains the nvidia,invert-interrupt property.
3606 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
3608 pmc->soc->setup_irq_polarity(pmc, np, invert);
3615 early_initcall(tegra_pmc_early_init);