1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mach-at91/pm_slow_clock.S
5 * Copyright (C) 2006 Savin Zlobec
8 * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee>
10 #include <linux/linkage.h>
11 #include <linux/clk/at91_pmc.h>
13 #include "pm_data-offsets.h"
15 #define SRAMC_SELF_FRESH_ACTIVE 0x01
16 #define SRAMC_SELF_FRESH_EXIT 0x00
23 * Wait until master clock is ready (after switching master clock source)
26 1: ldr tmp1, [pmc, #AT91_PMC_SR]
27 tst tmp1, #AT91_PMC_MCKRDY
32 * Wait until master oscillator has stabilized.
35 1: ldr tmp1, [pmc, #AT91_PMC_SR]
36 tst tmp1, #AT91_PMC_MOSCS
41 * Wait for main oscillator selection is done
44 1: ldr tmp1, [pmc, #AT91_PMC_SR]
45 tst tmp1, #AT91_PMC_MOSCSELS
50 * Put the processor to enter the idle state
54 #if defined(CONFIG_CPU_V7)
55 mov tmp1, #AT91_PMC_PCK
56 str tmp1, [pmc, #AT91_PMC_SCDR]
60 wfi @ Wait For Interrupt
62 mcr p15, 0, tmp1, c7, c0, 4
72 * void at91_suspend_sram_fn(struct at91_pm_data*)
74 * @r0: base address of struct at91_pm_data
76 /* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
78 ENTRY(at91_pm_suspend_in_sram)
79 /* Save registers on stack */
80 stmfd sp!, {r4 - r12, lr}
82 /* Drain write buffer */
84 mcr p15, 0, tmp1, c7, c10, 4
86 ldr tmp1, [r0, #PM_DATA_PMC]
88 ldr tmp1, [r0, #PM_DATA_RAMC0]
90 ldr tmp1, [r0, #PM_DATA_RAMC1]
91 str tmp1, .sramc1_base
92 ldr tmp1, [r0, #PM_DATA_MEMCTRL]
94 ldr tmp1, [r0, #PM_DATA_MODE]
96 /* Both ldrne below are here to preload their address in the TLB */
97 ldr tmp1, [r0, #PM_DATA_SHDWC]
100 ldrne tmp2, [tmp1, #0]
101 ldr tmp1, [r0, #PM_DATA_SFRBU]
104 ldrne tmp2, [tmp1, #0x10]
106 /* Active the self-refresh mode */
107 mov r0, #SRAMC_SELF_FRESH_ACTIVE
108 bl at91_sramc_self_refresh
111 cmp r0, #AT91_PM_STANDBY
113 cmp r0, #AT91_PM_BACKUP
120 /* Wait for interrupt */
130 /* Exit the self-refresh mode */
131 mov r0, #SRAMC_SELF_FRESH_EXIT
132 bl at91_sramc_self_refresh
134 /* Restore registers, and return */
135 ldmfd sp!, {r4 - r12, pc}
136 ENDPROC(at91_pm_suspend_in_sram)
138 ENTRY(at91_backup_mode)
139 /* Switch the master clock source to slow clock. */
141 ldr tmp1, [pmc, #AT91_PMC_MCKR]
142 bic tmp1, tmp1, #AT91_PMC_CSS
143 str tmp1, [pmc, #AT91_PMC_MCKR]
150 str tmp1, [r0, #0x10]
154 mov tmp1, #0xA5000000
157 ENDPROC(at91_backup_mode)
159 .macro at91_pm_ulp0_mode
162 /* Turn off the crystal oscillator */
163 ldr tmp1, [pmc, #AT91_CKGR_MOR]
164 bic tmp1, tmp1, #AT91_PMC_MOSCEN
165 orr tmp1, tmp1, #AT91_PMC_KEY
166 str tmp1, [pmc, #AT91_CKGR_MOR]
168 /* Save RC oscillator state */
169 ldr tmp1, [pmc, #AT91_PMC_SR]
170 str tmp1, .saved_osc_status
171 tst tmp1, #AT91_PMC_MOSCRCS
174 /* Turn off RC oscillator */
175 ldr tmp1, [pmc, #AT91_CKGR_MOR]
176 bic tmp1, tmp1, #AT91_PMC_MOSCRCEN
177 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
178 orr tmp1, tmp1, #AT91_PMC_KEY
179 str tmp1, [pmc, #AT91_CKGR_MOR]
181 /* Wait main RC disabled done */
182 2: ldr tmp1, [pmc, #AT91_PMC_SR]
183 tst tmp1, #AT91_PMC_MOSCRCS
186 /* Wait for interrupt */
189 /* Restore RC oscillator state */
190 ldr tmp1, .saved_osc_status
191 tst tmp1, #AT91_PMC_MOSCRCS
194 /* Turn on RC oscillator */
195 ldr tmp1, [pmc, #AT91_CKGR_MOR]
196 orr tmp1, tmp1, #AT91_PMC_MOSCRCEN
197 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
198 orr tmp1, tmp1, #AT91_PMC_KEY
199 str tmp1, [pmc, #AT91_CKGR_MOR]
201 /* Wait main RC stabilization */
202 3: ldr tmp1, [pmc, #AT91_PMC_SR]
203 tst tmp1, #AT91_PMC_MOSCRCS
206 /* Turn on the crystal oscillator */
207 4: ldr tmp1, [pmc, #AT91_CKGR_MOR]
208 orr tmp1, tmp1, #AT91_PMC_MOSCEN
209 orr tmp1, tmp1, #AT91_PMC_KEY
210 str tmp1, [pmc, #AT91_CKGR_MOR]
216 * Note: This procedure only applies on the platform which uses
217 * the external crystal oscillator as a main clock source.
219 .macro at91_pm_ulp1_mode
222 /* Save RC oscillator state and check if it is enabled. */
223 ldr tmp1, [pmc, #AT91_PMC_SR]
224 str tmp1, .saved_osc_status
225 tst tmp1, #AT91_PMC_MOSCRCS
228 /* Enable RC oscillator */
229 ldr tmp1, [pmc, #AT91_CKGR_MOR]
230 orr tmp1, tmp1, #AT91_PMC_MOSCRCEN
231 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
232 orr tmp1, tmp1, #AT91_PMC_KEY
233 str tmp1, [pmc, #AT91_CKGR_MOR]
235 /* Wait main RC stabilization */
236 1: ldr tmp1, [pmc, #AT91_PMC_SR]
237 tst tmp1, #AT91_PMC_MOSCRCS
240 /* Switch the main clock source to 12-MHz RC oscillator */
241 2: ldr tmp1, [pmc, #AT91_CKGR_MOR]
242 bic tmp1, tmp1, #AT91_PMC_MOSCSEL
243 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
244 orr tmp1, tmp1, #AT91_PMC_KEY
245 str tmp1, [pmc, #AT91_CKGR_MOR]
249 /* Disable the crystal oscillator */
250 ldr tmp1, [pmc, #AT91_CKGR_MOR]
251 bic tmp1, tmp1, #AT91_PMC_MOSCEN
252 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
253 orr tmp1, tmp1, #AT91_PMC_KEY
254 str tmp1, [pmc, #AT91_CKGR_MOR]
256 /* Switch the master clock source to main clock */
257 ldr tmp1, [pmc, #AT91_PMC_MCKR]
258 bic tmp1, tmp1, #AT91_PMC_CSS
259 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
260 str tmp1, [pmc, #AT91_PMC_MCKR]
264 /* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */
265 ldr tmp1, [pmc, #AT91_CKGR_MOR]
266 orr tmp1, tmp1, #AT91_PMC_WAITMODE
267 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
268 orr tmp1, tmp1, #AT91_PMC_KEY
269 str tmp1, [pmc, #AT91_CKGR_MOR]
271 /* Quirk for SAM9X60's PMC */
277 /* Enable the crystal oscillator */
278 ldr tmp1, [pmc, #AT91_CKGR_MOR]
279 orr tmp1, tmp1, #AT91_PMC_MOSCEN
280 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
281 orr tmp1, tmp1, #AT91_PMC_KEY
282 str tmp1, [pmc, #AT91_CKGR_MOR]
286 /* Switch the master clock source to slow clock */
287 ldr tmp1, [pmc, #AT91_PMC_MCKR]
288 bic tmp1, tmp1, #AT91_PMC_CSS
289 str tmp1, [pmc, #AT91_PMC_MCKR]
293 /* Switch main clock source to crystal oscillator */
294 ldr tmp1, [pmc, #AT91_CKGR_MOR]
295 orr tmp1, tmp1, #AT91_PMC_MOSCSEL
296 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
297 orr tmp1, tmp1, #AT91_PMC_KEY
298 str tmp1, [pmc, #AT91_CKGR_MOR]
302 /* Switch the master clock source to main clock */
303 ldr tmp1, [pmc, #AT91_PMC_MCKR]
304 bic tmp1, tmp1, #AT91_PMC_CSS
305 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
306 str tmp1, [pmc, #AT91_PMC_MCKR]
310 /* Restore RC oscillator state */
311 ldr tmp1, .saved_osc_status
312 tst tmp1, #AT91_PMC_MOSCRCS
315 /* Disable RC oscillator */
316 ldr tmp1, [pmc, #AT91_CKGR_MOR]
317 bic tmp1, tmp1, #AT91_PMC_MOSCRCEN
318 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
319 orr tmp1, tmp1, #AT91_PMC_KEY
320 str tmp1, [pmc, #AT91_CKGR_MOR]
322 /* Wait RC oscillator disable done */
323 4: ldr tmp1, [pmc, #AT91_PMC_SR]
324 tst tmp1, #AT91_PMC_MOSCRCS
333 /* Save Master clock setting */
334 ldr tmp1, [pmc, #AT91_PMC_MCKR]
335 str tmp1, .saved_mckr
338 * Set the Master clock source to slow clock
340 bic tmp1, tmp1, #AT91_PMC_CSS
341 str tmp1, [pmc, #AT91_PMC_MCKR]
346 cmp r0, #AT91_PM_ULP1
360 * Restore master clock setting
362 ldr tmp1, .saved_mckr
363 str tmp1, [pmc, #AT91_PMC_MCKR]
368 ENDPROC(at91_ulp_mode)
371 * void at91_sramc_self_refresh(unsigned int is_active)
374 * @r0: 1 - active self-refresh mode
375 * 0 - exit self-refresh mode
378 * @r2: base address of the sram controller
381 ENTRY(at91_sramc_self_refresh)
385 cmp r1, #AT91_MEMCTRL_MC
389 * at91rm9200 Memory controller
393 * For exiting the self-refresh mode, do nothing,
394 * automatically exit the self-refresh mode.
396 tst r0, #SRAMC_SELF_FRESH_ACTIVE
399 /* Active SDRAM self-refresh mode */
401 str r3, [r2, #AT91_MC_SDRAMC_SRR]
405 cmp r1, #AT91_MEMCTRL_DDRSDR
409 * DDR Memory controller
411 tst r0, #SRAMC_SELF_FRESH_ACTIVE
414 /* LPDDR1 --> force DDR2 mode during self-refresh */
415 ldr r3, [r2, #AT91_DDRSDRC_MDR]
416 str r3, .saved_sam9_mdr
417 bic r3, r3, #~AT91_DDRSDRC_MD
418 cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
419 ldreq r3, [r2, #AT91_DDRSDRC_MDR]
420 biceq r3, r3, #AT91_DDRSDRC_MD
421 orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
422 streq r3, [r2, #AT91_DDRSDRC_MDR]
424 /* Active DDRC self-refresh mode */
425 ldr r3, [r2, #AT91_DDRSDRC_LPR]
426 str r3, .saved_sam9_lpr
427 bic r3, r3, #AT91_DDRSDRC_LPCB
428 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
429 str r3, [r2, #AT91_DDRSDRC_LPR]
431 /* If using the 2nd ddr controller */
436 ldr r3, [r2, #AT91_DDRSDRC_MDR]
437 str r3, .saved_sam9_mdr1
438 bic r3, r3, #~AT91_DDRSDRC_MD
439 cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
440 ldreq r3, [r2, #AT91_DDRSDRC_MDR]
441 biceq r3, r3, #AT91_DDRSDRC_MD
442 orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
443 streq r3, [r2, #AT91_DDRSDRC_MDR]
445 /* Active DDRC self-refresh mode */
446 ldr r3, [r2, #AT91_DDRSDRC_LPR]
447 str r3, .saved_sam9_lpr1
448 bic r3, r3, #AT91_DDRSDRC_LPCB
449 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
450 str r3, [r2, #AT91_DDRSDRC_LPR]
456 /* Restore MDR in case of LPDDR1 */
457 ldr r3, .saved_sam9_mdr
458 str r3, [r2, #AT91_DDRSDRC_MDR]
459 /* Restore LPR on AT91 with DDRAM */
460 ldr r3, .saved_sam9_lpr
461 str r3, [r2, #AT91_DDRSDRC_LPR]
463 /* If using the 2nd ddr controller */
466 ldrne r3, .saved_sam9_mdr1
467 strne r3, [r2, #AT91_DDRSDRC_MDR]
468 ldrne r3, .saved_sam9_lpr1
469 strne r3, [r2, #AT91_DDRSDRC_LPR]
474 * SDRAMC Memory controller
477 tst r0, #SRAMC_SELF_FRESH_ACTIVE
480 /* Active SDRAMC self-refresh mode */
481 ldr r3, [r2, #AT91_SDRAMC_LPR]
482 str r3, .saved_sam9_lpr
483 bic r3, r3, #AT91_SDRAMC_LPCB
484 orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
485 str r3, [r2, #AT91_SDRAMC_LPR]
488 ldr r3, .saved_sam9_lpr
489 str r3, [r2, #AT91_SDRAMC_LPR]
493 ENDPROC(at91_sramc_self_refresh)
522 ENTRY(at91_pm_suspend_in_sram_sz)
523 .word .-at91_pm_suspend_in_sram