2 * arch/arm/mach-at91/pm.c
3 * AT91 Power Management
5 * Copyright (C) 2005 David Brownell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/gpio.h>
14 #include <linux/suspend.h>
15 #include <linux/sched.h>
16 #include <linux/proc_fs.h>
17 #include <linux/genalloc.h>
18 #include <linux/interrupt.h>
19 #include <linux/sysfs.h>
20 #include <linux/module.h>
22 #include <linux/of_platform.h>
23 #include <linux/of_address.h>
24 #include <linux/platform_device.h>
26 #include <linux/clk/at91_pmc.h>
29 #include <linux/atomic.h>
30 #include <asm/mach/time.h>
31 #include <asm/mach/irq.h>
32 #include <asm/fncpy.h>
33 #include <asm/cacheflush.h>
39 * FIXME: this is needed to communicate between the pinctrl driver and
40 * the PM implementation in the machine. Possibly part of the PM
41 * implementation should be moved down into the pinctrl driver and get
42 * called as part of the generic suspend/resume path.
44 #ifdef CONFIG_PINCTRL_AT91
45 extern void at91_pinctrl_gpio_suspend(void);
46 extern void at91_pinctrl_gpio_resume(void);
50 unsigned long uhp_udp_mask;
54 void __iomem *at91_ramc_base[2];
56 static int at91_pm_valid_state(suspend_state_t state)
60 case PM_SUSPEND_STANDBY:
70 static suspend_state_t target_state;
73 * Called after processes are frozen, but before we shutdown devices.
75 static int at91_pm_begin(suspend_state_t state)
82 * Verify that all the clocks are correct before entering
85 static int at91_pm_verify_clocks(void)
90 scsr = at91_pmc_read(AT91_PMC_SCSR);
92 /* USB must not be using PLLB */
93 if ((scsr & at91_pm_data.uhp_udp_mask) != 0) {
94 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
98 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
99 for (i = 0; i < 4; i++) {
102 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
105 css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
106 if (css != AT91_PMC_CSS_SLOW) {
107 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
116 * Call this from platform driver suspend() to see how deeply to suspend.
117 * For example, some controllers (like OHCI) need one of the PLL clocks
118 * in order to act as a wakeup source, and those are not available when
119 * going into slow clock mode.
121 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
122 * the very same problem (but not using at91 main_clk), and it'd be better
123 * to add one generic API rather than lots of platform-specific ones.
125 int at91_suspend_entering_slow_clock(void)
127 return (target_state == PM_SUSPEND_MEM);
129 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
131 static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0,
132 void __iomem *ramc1, int memctrl);
134 extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0,
135 void __iomem *ramc1, int memctrl);
136 extern u32 at91_pm_suspend_in_sram_sz;
138 static void at91_pm_suspend(suspend_state_t state)
140 unsigned int pm_data = at91_pm_data.memctrl;
142 pm_data |= (state == PM_SUSPEND_MEM) ?
143 AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
148 at91_suspend_sram_fn(at91_pmc_base, at91_ramc_base[0],
149 at91_ramc_base[1], pm_data);
154 static int at91_pm_enter(suspend_state_t state)
156 #ifdef CONFIG_PINCTRL_AT91
157 at91_pinctrl_gpio_suspend();
161 * Suspend-to-RAM is like STANDBY plus slow clock mode, so
162 * drivers must suspend more deeply, the master clock switches
163 * to the clk32k and turns off the main oscillator
167 * Ensure that clocks are in a valid state.
169 if (!at91_pm_verify_clocks())
172 at91_pm_suspend(state);
177 * STANDBY mode has *all* drivers suspended; ignores irqs not
178 * marked as 'wakeup' event sources; and reduces DRAM power.
179 * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
180 * nothing fancy done with main or cpu clocks.
182 case PM_SUSPEND_STANDBY:
183 at91_pm_suspend(state);
191 pr_debug("AT91: PM - bogus suspend state %d\n", state);
196 target_state = PM_SUSPEND_ON;
198 #ifdef CONFIG_PINCTRL_AT91
199 at91_pinctrl_gpio_resume();
205 * Called right prior to thawing processes.
207 static void at91_pm_end(void)
209 target_state = PM_SUSPEND_ON;
213 static const struct platform_suspend_ops at91_pm_ops = {
214 .valid = at91_pm_valid_state,
215 .begin = at91_pm_begin,
216 .enter = at91_pm_enter,
220 static struct platform_device at91_cpuidle_device = {
221 .name = "cpuidle-at91",
224 static void at91_pm_set_standby(void (*at91_standby)(void))
227 at91_cpuidle_device.dev.platform_data = at91_standby;
231 * The AT91RM9200 goes into self-refresh mode with this command, and will
232 * terminate self-refresh automatically on the next SDRAM access.
234 * Self-refresh mode is exited as soon as a memory access is made, but we don't
235 * know for sure when that happens. However, we need to restore the low-power
236 * mode if it was enabled before going idle. Restoring low-power mode while
237 * still in self-refresh is "not recommended", but seems to work.
239 static void at91rm9200_standby(void)
241 u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR);
246 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
247 " str %0, [%1, %2]\n\t"
248 " str %3, [%1, %4]\n\t"
249 " mcr p15, 0, %0, c7, c0, 4\n\t"
252 : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_MC_SDRAMC_LPR),
253 "r" (1), "r" (AT91_MC_SDRAMC_SRR),
257 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
260 static void at91_ddr_standby(void)
262 /* Those two values allow us to delay self-refresh activation
265 u32 saved_lpr0, saved_lpr1 = 0;
267 if (at91_ramc_base[1]) {
268 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
269 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
270 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
273 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
274 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
275 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
277 /* self-refresh mode now */
278 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
279 if (at91_ramc_base[1])
280 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
284 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
285 if (at91_ramc_base[1])
286 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
289 static void sama5d3_ddr_standby(void)
294 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
295 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
296 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
298 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
302 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
305 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
308 static void at91sam9_sdram_standby(void)
311 u32 saved_lpr0, saved_lpr1 = 0;
313 if (at91_ramc_base[1]) {
314 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
315 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
316 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
319 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
320 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
321 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
323 /* self-refresh mode now */
324 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
325 if (at91_ramc_base[1])
326 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
330 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
331 if (at91_ramc_base[1])
332 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
335 static const struct of_device_id ramc_ids[] __initconst = {
336 { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
337 { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
338 { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
339 { .compatible = "atmel,sama5d3-ddramc", .data = sama5d3_ddr_standby },
343 static __init void at91_dt_ramc(void)
345 struct device_node *np;
346 const struct of_device_id *of_id;
348 const void *standby = NULL;
350 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
351 at91_ramc_base[idx] = of_iomap(np, 0);
352 if (!at91_ramc_base[idx])
353 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
356 standby = of_id->data;
362 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
365 pr_warn("ramc no standby function available\n");
369 at91_pm_set_standby(standby);
372 static void __init at91_pm_sram_init(void)
374 struct gen_pool *sram_pool;
375 phys_addr_t sram_pbase;
376 unsigned long sram_base;
377 struct device_node *node;
378 struct platform_device *pdev = NULL;
380 for_each_compatible_node(node, NULL, "mmio-sram") {
381 pdev = of_find_device_by_node(node);
389 pr_warn("%s: failed to find sram device!\n", __func__);
393 sram_pool = gen_pool_get(&pdev->dev, NULL);
395 pr_warn("%s: sram pool unavailable!\n", __func__);
399 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
401 pr_warn("%s: unable to alloc sram!\n", __func__);
405 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
406 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
407 at91_pm_suspend_in_sram_sz, false);
408 if (!at91_suspend_sram_fn) {
409 pr_warn("SRAM: Could not map\n");
413 /* Copy the pm suspend handler to SRAM */
414 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
415 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
419 put_device(&pdev->dev);
423 static void __init at91_pm_init(void)
427 if (at91_cpuidle_device.dev.platform_data)
428 platform_device_register(&at91_cpuidle_device);
430 if (at91_suspend_sram_fn)
431 suspend_set_ops(&at91_pm_ops);
433 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
436 void __init at91rm9200_pm_init(void)
441 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
443 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
445 at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
446 at91_pm_data.memctrl = AT91_MEMCTRL_MC;
451 void __init at91sam9260_pm_init(void)
454 at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
455 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
456 return at91_pm_init();
459 void __init at91sam9g45_pm_init(void)
462 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
463 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
464 return at91_pm_init();
467 void __init at91sam9x5_pm_init(void)
470 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
471 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
472 return at91_pm_init();